Bridgetek FT801, FT800 Programming Manual

This document is a programmer guide for the FT800 series chip. This guide details the chip features and procedures for use. For FT801 specific features and procedures, please see the chapter FT801.

FT800 Series Programmer Guide

Version 2.1

Issue Date: 2016-09-19

1

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Table of Content

1 Introduction .............................................................. 9

1.1 Overview ............................................................................. 9

1.2 Scope .................................................................................. 9

1.3 API reference definitions..................................................... 9

2 Programming Model ................................................ 11

2.1 General Software architecture .......................................... 11

2.2 Display configuration and initialization ............................. 12

2.2.1 Horizontal timing ..................................................................... 13

2.2.2 Vertical timing ........................................................................ 14

2.2.3 Signals updating timing control ................................................. 14

2.2.4 Timing example: 480x272 at 60Hz ............................................ 15

2.2.5 Initialization Sequence ............................................................. 16

2.3 Sound Synthesizer ............................................................. 17

2.4 Audio playback .................................................................. 18

2.5 Graphics routines .............................................................. 19

2.5.1 Getting started ........................................................................ 19

2.5.2 Coordinate Plane ..................................................................... 20

2.5.3 Drawing pattern ...................................................................... 21

2.5.4 Writing display lists ................................................................. 26

2.5.5 Bitmap transformation matrix ................................................... 27

2.5.6 Color and transparency ............................................................ 27

2.5.7 VERTEX2II and VERTEX2F ........................................................ 28

2.5.8 Screenshot ............................................................................. 30

2.5.9 Performance ........................................................................... 30

3 Register Description ................................................ 32

3.1 Graphics Engine Registers ................................................. 32

2

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

3.2 Touch Engine Registers (FT800 only) ................................ 47

3.3 Audio Engine Registers ...................................................... 62

3.4 Co-processor Engine Registers .......................................... 68

3.5 Miscellaneous Registers .................................................... 70

4 Display list commands ............................................. 81

4.1 Graphics State ................................................................... 81

4.2 Command encoding ........................................................... 82

4.3 Command groups .............................................................. 83

4.3.1 Setting Graphics state .............................................................. 83

4.3.2 Drawing actions ...................................................................... 84

4.3.3 Execution control..................................................................... 84

4.4 ALPHA_FUNC ..................................................................... 85

4.5 BEGIN................................................................................ 86

4.6 BITMAP_HANDLE............................................................... 88

4.7 BITMAP_LAYOUT ............................................................... 89

4.8 BITMAP_SIZE .................................................................... 94

4.9 BITMAP_SOURCE ............................................................... 97

4.10 BITMAP_TRANSFORM_A ................................................. 99

4.11 BITMAP_TRANSFORM_B ............................................... 101

4.12 BITMAP_TRANSFORM_C ............................................... 102

4.13 BITMAP_TRANSFORM_D ............................................... 103

4.14 BITMAP_TRANSFORM_E ............................................... 104

4.15 BITMAP_TRANSFORM_F ............................................... 106

4.16 BLEND_FUNC ................................................................ 107

4.17 CALL ............................................................................. 110

4.18 CELL .............................................................................. 111

4.19 CLEAR ........................................................................... 112

3

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.20 CLEAR_COLOR_A .......................................................... 114

4.21 CLEAR_COLOR_RGB ...................................................... 115

4.22 CLEAR_STENCIL ............................................................ 117

4.23 CLEAR_TAG ................................................................... 118

4.24 COLOR_A ...................................................................... 119

4.25 COLOR_MASK ................................................................ 120

4.26 COLOR_RGB .................................................................. 122

4.27 DISPLAY ....................................................................... 123

4.28 END ............................................................................... 124

4.29 JUMP ............................................................................. 125

4.30 LINE_WIDTH ................................................................ 126

4.31 MACRO .......................................................................... 127

4.32 POINT_SIZE .................................................................. 128

4.33 RESTORE_CONTEXT ...................................................... 129

4.34 RETURN ........................................................................ 130

4.35 SAVE CONTEXT ............................................................. 131

4.36 SCISSOR_SIZE .............................................................. 132

4.37 SCISSOR_XY ................................................................. 134

4.38 STENCIL_FUNC ............................................................. 135

4.39 STENCIL_MASK ............................................................. 137

4.40 STENCIL_OP ................................................................. 138

4.41 TAG ............................................................................... 140

4.42 TAG_MASK .................................................................... 141

4.43 VERTEX2F ..................................................................... 142

4.44 VERTEX2II .................................................................... 143

5 Co-Processor Engine commands ............................ 144

4

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

5.1 Co-processor handling of Display list commands ............. 146

5.2 Synchronization .............................................................. 146

5.3 ROM and RAM Fonts ........................................................ 147

5.4 Cautions .......................................................................... 148

5.5 Fault Scenarios ................................................................ 149

5.6 widgets physical dimension ............................................. 149

5.7 widgets color settings ..................................................... 149

5.8 Co-processor engine graphics state ................................ 150

5.9 Definition of parameter OPTION ...................................... 151

5.10 Co-processor engine resources ..................................... 153

5.11 Command groups .......................................................... 153

5.12 CMD_DLSTART - start a new display list ....................... 155

5.13 CMD_SWAP - swap the current display list ................... 156

5.14 CMD_COLDSTART - set co-processor engine state to

default values ......................................................................... 156

5.15 CMD_INTERRUPT - trigger interrupt INT_CMDFLAG ...... 158

5.16 CMD_APPEND - append memory to display list ............. 159

5.17 CMD_REGREAD - read a register value .......................... 160

5.18 CMD_MEMWRITE - write bytes into memory ................. 161

5.19 CMD_INFLATE - decompress data into memory ............ 163

5.20 CMD_LOADIMAGE - load a JPEG image ......................... 164

5.21 CMD_MEMCRC - compute a CRC-32 for memory ............ 166

5.22 CMD_MEMZERO - write zero to a block of memory ........ 167

5.23 CMD_MEMSET - fill memory with a byte value .............. 168

5.24 CMD_MEMCPY - copy a block of memory ....................... 169

5.25 CMD_BUTTON - draw a button ...................................... 170

5.26 CMD_CLOCK - draw an analog clock .............................. 173

5

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

5.27 CMD_FGCOLOR - set the foreground color .................... 178

5.28 CMD_BGCOLOR - set the background color ................... 179

5.29 CMD_GRADCOLOR - set the 3D button highlight color .. 181

5.30 CMD_GAUGE - draw a gauge ......................................... 183

5.31 CMD_GRADIENT - draw a smooth color gradient .......... 190

5.32 CMD_KEYS - draw a row of keys ................................... 194

5.33 CMD_PROGRESS - draw a progress bar ......................... 199

5.34 CMD_SCROLLBAR – draw a scroll bar ............................ 202

5.35 CMD_SLIDER – draw a slider ........................................ 205

5.36 CMD_DIAL – draw a rotary dial control ......................... 208

5.37 CMD_TOGGLE – draw a toggle switch ........................... 211

5.38 CMD_TEXT - draw text .................................................. 214

5.39 CMD_NUMBER - draw a decimal number ....................... 218

5.40 CMD_SETMATRIX - write the current matrix to the display list 221

5.41 CMD_GETMATRIX - retrieves the current matrix

coefficients ............................................................................. 221

5.42 CMD_GETPTR - get the end memory address of inflated data 223

5.43 CMD_GETPROPS - get the image properties decompressed

by CMD_LOADIMAGE ............................................................... 224

5.44 CMD_SCALE - apply a scale to the current matrix ......... 224

5.45 CMD_ROTATE - apply a rotation to the current matrix .. 227

5.46 CMD_TRANSLATE - apply a translation to the current

matrix ..................................................................................... 229

5.47 CMD_CALIBRATE - execute the touch screen calibration

routine .................................................................................... 231

5.48 CMD_SPINNER - start an animated spinner .................. 232

6

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

5.49 CMD_SCREENSAVER - start an animated screensaver ... 236

5.50 CMD_SKETCH - start a continuous sketch update ......... 237

5.51 CMD_STOP - stop any of spinner, screensaver or sketch 239

5.52 CMD_SETFONT - set up a custom font ........................... 240

5.53 CMD_TRACK - track touches for a graphics object ........ 241

5.54 CMD_SNAPSHOT - take a snapshot of the current screen 245

5.55 CMD_LOGO - play FTDI logo animation ......................... 246

6 FT801 operation .................................................... 247

6.1 FT801 introduction .......................................................... 247

6.2 FT801 touch engine ......................................................... 247

6.3 FT801 touch registers ..................................................... 247

6.4 Register summary ........................................................... 253

6.5 Calibration ....................................................................... 253

6.6 CMD_CSKETCH – Capacitive touch specific sketch ........... 254

7 Contact Information .............................................. 256

Appendix A – References ........................................... 257

Document References ............................................................. 257

Acronyms & Abbreviations ...................................................... 257

Appendix B – List of Figures & Tables ........................ 258

List of Figures ......................................................................... 258

List of Tables ........................................................................... 258

Appendix C – Memory Map ......................................... 259

Appendix D - List of Code Snippet .............................. 260

Appendix E - List of Registers .................................... 261

7

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Appendix F – Revision History ................................... 263

8

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

1 Introduction

This document captures programming details of FT800 series chips including graphics commands, widget commands and configurations to control FT800 series chips for smooth and vibrant screen effects.

The FT800 series chips are graphics controllers with add-on features such as audio playback and touch capabilities. They consist of a rich set of graphics objects (primitive and widgets) that can be used for displaying various menus and screen shots for a range of products including home appliances, toys, industrial machinery, home automation, elevators, and many more.

1.1 Overview

This document will be useful to understand the command set and demonstrate the ease of usage in the examples given for each specific instruction. In addition, it also covers various power modes, audio, and touch features as well as their usage.

Information on pin settings, hardware model and hardware configuration can be found in the FT800 data sheet (DS_FT800_Embedded_Video_Engine) or FT801 datasheet (DS_FT801).

1.2 Scope

This document is targeted for software programmers and system designers to develop graphical user interface (GUI) applications on any system processor with either an SPI or I2C master port.

1.3 API reference definitions

Functionality and nomenclature of the APIs used in this document.

wr8() – write 8 bits to intended address location

wr16() – write 16 bits to intended address location

wr32() – write 32 bits to intended address location

wr8s() – write 8 bits string to intended address location

rd8() – read 8 bits from intended address location

rd16() – read 16 bits from intended address location

rd32() – read 32 bits from intended address location

rd8s() – read 8 bits string from intended address location

cmd() – write 32 bits command to co-processor engine FIFO RAM_CMD

9

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

cmd_*() – Write 32 bits co-processor engine command with its necessary parameters to the co-processor engine FIFO (RAM_CMD).

dl() – Write the specified 32 bits display list command to RAM_DL. Refer to section 2.5.4 Writing display lists for more information.

host_command() – send host command to FT800. Refer to the FT800 data sheet for more information.

10

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2 Programming Model

The FT800 appears to the host MCU as a memory-mapped SPI or I2C device. The host communicates with the FT800 using Read or Write to 8MB address space.

Within this document, endianness of DL commands, co-processor engine commands, register values read/write, input RGB bitmap data and ADPCM input data are in ‘Little Endian’ format.

2.1 General Software architecture

The software architecture can be broadly classified into layers such as custom applications, graphics/GUI manager, video manger, audio manager, drivers etc. FT800 higher level graphics engine commands and co-processor engine widget commands are part of the graphics/GUI manager. Control & data paths of video and audio are part of video manager and audio manager. Communication between graphics/GUI manager and the hardware is via the SPI or I2C driver.

Typically the display screen shot is constructed by the custom application based on the framework exposed by the graphics/GUI manager.

11

Product Page

MPU

FT800

Custom

APP0

Graphics/GUI manager

Video Manager

Audio Manager

SPI/I2C Driver

Hardware

Custom

APP1

Custom

APP2

Host

software

stack

FT800 graphics

objects &

widgets to be

part of

graphics

manager

Figure 1: Software Architecture

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.2 Display configuration and initialization

To configure the display, load the timing control registers with values for the particular display. These registers control horizontal timing:

 REG_PCLK  REG_PCLK_POL  REG_HCYCLE  REG_HOFFSET  REG_HSIZE  REG_HSYNC0  REG_HSYNC1

These registers control vertical timing:

12

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

 REG_VCYCLE  REG_VOFFSET  REG_VSIZE  REG_VSYNC0  REG_VSYNC1

And the REG_CSPREAD register changes color clock timing to reduce system noise.

GPIO bit 7 is used for the display enable pin of the LCD module. By setting the direction of the GPIO bit to out direction, the display can be enabled by writing value of 1 into GPIO bit 7 or the display can be disabled by writing a value of 0 into GPIO bit 7. By default GPIO bit 7 direction is output and the value is 0.

Note: Refer to FT800 data sheet for information on display register set.

2.2.1 Horizontal timing

Figure 2: Horizontal Timing

REG_PCLK controls the frequency of PCLK. The register specifies a divisor for the main 48 MHz clock, so a value of 4 gives a 12 MHz PCLK. If REG_PCLK is zero, then all display output is suspended. REG_PCLK_POL controls the polarity of PCLK. Zero means that display data is clocked out on the rising edge of PCLK. One means data is clocked on the falling edge.

The total number of PCLKs in a horizontal line is REG_HCYCLE. Within this horizontal line are the scanned out pixels, REG_HSIZE in total. They start after REG_HOFFSET cycles. Signal DE is high while pixels are being scanned out.

Horizontal sync timing on signal HSYNC is controlled by REG_HSYNC0 and REG_HSYNC1. They specify the time at which HSYNC falls and rises respectively.

13

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.2.2 Vertical timing

Figure 3: Vertical Timing

Vertical timing is specified in number of lines. The total number of lines in a frame is REG_VCYCLE. There are REG_VSIZE rows of pixels in total. They start after REG_VOFFSET cycles.

Vertical sync timing on signal VSYNC is controlled by REG_VSYNC0 and REG_VSYNC1. They specify the lines at which VSYNC falls and rises respectively.

2.2.3 Signals updating timing control

With REG_CSPREAD disabled, all color signals are updated at the same time:

Figure 4: Pixel clocking with no CSPREAD

But with REG_CSPREAD enabled, the color signal timings are adjusted slightly so that fewer signals change simultaneously:

Figure 5: Pixel clocking with CSPREAD

14

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.2.4 Timing example: 480x272 at 60Hz

For a display updating at 60Hz, there are 48000000/60= 800000 fast clocks per frame. Setting the PCLK divisor REG_PCLK to 5 gives a PCLK frequency of 9.6 MHz and

800000/5= 160000PCLKs per frame.

For a 480 x 272 display, the typical horizontal period is 525 clocks, and vertical period is 286 lines. A little searching shows that a 548 x 292 size gives a period of 160016 clocks, very close to the target. So with a REG_HCYCLE=548 and REG_VCYCLE=292 the display frequency is almost exactly 60Hz. The other register settings can be set directly from the display panel datasheet.

15

Product Page

MCU_SPI_CLK_Freq(<11MHz);//use the MCU SPI clock less than 11MHz

host_command(CLKEXT);//send command to "CLKEXT" to FT800 host_command(ACTIVE);//send host command "ACTIVE" to FT800

/* Configure display registers - demonstration for WQVGA resolution */

wr16(REG_HCYCLE, 548); wr16(REG_HOFFSET, 43); wr16(REG_HSYNC0, 0); wr16(REG_HSYNC1, 41); wr16(REG_VCYCLE, 292); wr16(REG_VOFFSET, 12); wr16(REG_VSYNC0, 0); wr16(REG_VSYNC1, 10); wr8(REG_SWIZZLE, 0); wr8(REG_PCLK_POL, 1); wr8(REG_CSPREAD, 1); wr16(REG_HSIZE, 480); wr16(REG_VSIZE, 272);

/* write first display list */

wr32(RAM_DL+0,CLEAR_COLOR_RGB(0,0,0)); wr32(RAM_DL+4,CLEAR(1,1,1)); wr32(RAM_DL+8,DISPLAY());

wr8(REG_DLSWAP,DLSWAP_FRAME);//display list swap

wr8(REG_GPIO_DIR,0x80 | Ft_Gpu_Hal_Rd8(phost,REG_GPIO_DIR)); wr8(REG_GPIO,0x080 | Ft_Gpu_Hal_Rd8(phost,REG_GPIO));//enable display bit

wr8(REG_PCLK,5);//after this display is visible on the LCD

MCU_SPI_CLK_Freq(<30Mhz);//use the MCU SPI clock upto 30MHz

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.2.5 Initialization Sequence

This section describes the initialization sequence in the different scenario.

 Initialization Sequence during the boot up:

1. Use MCU SPI clock not more than 11MHz

2. Send Host command “CLKEXT” to FT800

3. Send Host command “ACTIVE” to enable clock to FT800.

4. Configure video timing registers, except REG_PCLK

5. Write first display list

6. Write REG_DLSWAP, FT800 swaps display list immediately

7. Enable back light control for display

8. Write REG_PCLK, video output begins with the first display list

9. Use MCU SPI clock not more than 30MHz

Code snippet 1 Initialization sequence

 Initialization Sequence from Power Down using PD_N pin:

16

Product Page

wr8(REG_VOL_SOUND,0xFF); //set the volume to maximum wr16(REG_SOUND, (0x6C<< 8) | 0x41); // C8 MIDI note on xylophone wr8(REG_PLAY, 1); // play the sound

Sound_status = rd8(REG_PLAY);//1-play is going on, 0-play has finished

wr16(REG_SOUND,0x0);//configure silence as sound to be played wr8(REG_PLAY,1);//play sound Sound_status = rd8(REG_PLAY);//1-play is going on, 0-play has finished

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

1. Drive the PD_N pin high

2. Wait for at least 20ms

3. Execute ”Initialization Sequence during the Boot UP” from steps 1 to 9

 Initialization Sequence from Sleep Mode:

1. Send Host command “ACTIVE” to enable clock to FT800

2. Wait for at least 20ms

3. Execute “Initialization Sequence during Boot Up” from steps 5 to 8

 Initialization sequence from standby mode:

Execute all the steps mentioned in “Initialization Sequence from Sleep Mode”

except waiting for at least 20ms in step 2.

Note: Refer to FT800 data sheet for information on power modes. Follow section 2.3 for audio management during power down and reset operations.

2.3 Sound Synthesizer

Sample code to play C8 on the xylophone:

Code snippet 2 sound synthesizer play C8 on the xylophone

Sample code to check the status of sound play:

Code snippet 3 sound synthesizer check the status of sound playing

Sample code to stop sound play:

Code snippet 4 sound synthesizer stop playing sound

To avoid an audio pop sound on reset or power state change, trigger a "mute" sound, and wait for it to complete (completion of sound play is when REG_PLAY contains a value of 0). This sets the output value to 0 level. On reboot, the audio engine plays back the "unmute" sound to drive the output to the half way level.

Note: Refer to FT800 data sheet for more information on sound synthesizer and audio playback.

17

Product Page

wr8(REG_VOL_PB,0xFF);//configure audio playback volume wr32(REG_PLAYBACK_START,0);//configure audio buffer starting address wr32(REG_PLAYBACK_LENGTH,100*1024);//configure audio buffer length wr16(REG_PLAYBACK_FREQ,44100);//configure audio sampling frequency wr8(REG_PLAYBACK_FORMAT,ULAW_SAMPLES);//configure audio format wr8(REG_PLAYBACK_LOOP,0);//configure once or continuous playback wr8(REG_PLAYBACK_PLAY,1);//start the audio playback

AudioPlay_Status = rd8(REG_PLAYBACK_PLAY);//1-audio playback is going on,

0-audio playback has finished

wr32(REG_PLAYBACK_LENGTH,0);//configure the playback length to 0 wr8(REG_PLAYBACK_PLAY,1);//start audio playback

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.4 Audio playback

FT800 supports three types of audio format: 4 Bit IMA ADPCM, 8 Bit signed PCM, 8 Bit uLaw. For IMA ADPCM format, please note the byte order: within one byte, first sample (4 bits) shall locate from bit 0 to bit 3, while the second sample (4 bits) shall locate from bit 4 to bit 7.

For the audio data in FT800 RAM to play, FT800 requires the start address in REG_PLAYBACK_START to be 64 bit (8 Bytes) aligned. In addition, the length of audio data specified by REG_PLAYBACK_LENGTH is required to be 64 bit (8 Bytes) aligned.

To learn how to play back the audio data, please check the sample code below:

Code snippet 5 Audio playback

Code snippet 6 Check the status of audio playback

Code snippet 7 Stop the audio playback

18

Product Page

wr32(RAM_DL + 0, CLEAR(1, 1, 1)); // clear screen wr32(RAM_DL + 4, BEGIN(BITMAPS)); // start drawing bitmaps wr32(RAM_DL + 8, VERTEX2II(220, 110, 31, 'F')); // ascii F in font 31 wr32(RAM_DL + 12, VERTEX2II(244, 110, 31, 'T')); // ascii T wr32(RAM_DL + 16, VERTEX2II(270, 110, 31, 'D')); // ascii D wr32(RAM_DL + 20, VERTEX2II(299, 110, 31, 'I')); // ascii I wr32(RAM_DL + 24, END()); wr32(RAM_DL + 28, COLOR_RGB(160, 22, 22)); // change color to red wr32(RAM_DL + 32, POINT_SIZE(320)); // set point size to 20 pixels in

radius

wr32(RAM_DL + 36, BEGIN(POINTS)); // start drawing points wr32(RAM_DL + 40, VERTEX2II(192, 133, 0, 0)); // red point wr32(RAM_DL + 44, END()); wr32(RAM_DL + 48, DISPLAY()); // display the image

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.5 Graphics routines

This section describes graphics features and captures a few of examples.

2.5.1 Getting started

This short example creates a screen with the text "FTDI" on it, with a red dot.

Figure 6: Getting Start Example Image

The code to draw the screen is:

Code snippet 8 Getting Started

19

Product Page

Visible Area

(511,511)

511

(0,0)

511

Y

Figure 7: FT800 graphics coordinates plane in pixel precision

X

-1024

1023

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

After the above drawing commands are loaded into display list RAM, register REG_DLSWAP is required to be set to 0x02 in order to make the new display list active on the next frame refresh. Note:

 The display list always starts at address RAM_DL  The address always increments by 4(bytes) as each command is 32 bit width.  Command CLEAR is recommended to be used before any other drawing

operation, in order to put FT800 graphics engine in a known state.

 The end of the display list is always flagged with the command DISPLAY

2.5.2 Coordinate Plane

The figure below illustrates the graphics coordinate plane and its visible area.

The valid X and Y coordinate ranges from -1024 to 1023 in pixel precision, i.e., from

-16384 to 16383 in 1/16th pixel precision.

20

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.5.3 Drawing pattern

The general pattern for drawing is:

 BEGIN with one of the primitive types  Input one or more vertices, which specify the placement of the primitive on

the screen

 END to mark the end of the primitive

(note: In many examples the END command is not explicitly listed)

The primitive types that the graphics engine support are:

 BITMAPS - rectangular pixel arrays, in various color formats  POINTS - anti-aliased points, point radius is 1-256 pixels  LINES - anti-aliased lines, with width from 0 to 4095 1/16th of pixel units.

(width is from center of the line to boundary)

 LINE_STRIP - anti-aliased lines, connected head-to-tail  RECTS - round-cornered rectangles, curvature of the corners can be adjusted

using LINE_WIDTH.

 EDGE_STRIP_A/B/L/R - edge strips

Examples

Draw points with varying radius from 5 pixels to 13 pixels with different colors:

dl( COLOR_RGB(128, 0, 0) );

dl( POINT_SIZE(5 * 16) );

dl( BEGIN(POINTS) );

dl( VERTEX2F(30 * 16,17 * 16) );

dl( COLOR_RGB(0, 128, 0) );

dl( POINT_SIZE(8 * 16) );

dl( VERTEX2F(90 * 16, 17 * 16) );

dl( COLOR_RGB(0, 0, 128) );

dl( POINT_SIZE(10 * 16) );

dl( VERTEX2F(30 * 16, 51 * 16) );

dl( COLOR_RGB(128, 128, 0) );

dl( POINT_SIZE(13 * 16) );

dl( VERTEX2F(90 * 16, 51 * 16) );

21

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

The VERTEX2F command gives the location of the circle center.

Draw lines with varying sizes from 2 pixels to 6 pixels with different colors (line width size is from center of the line till boundary):

dl( COLOR_RGB(128, 0, 0) );

dl( LINE_WIDTH(2 * 16) );

dl( BEGIN(LINES) );

dl( VERTEX2F(30 * 16,38 * 16) );

dl( VERTEX2F(30 * 16,63 * 16) );

dl( COLOR_RGB(0, 128, 0) );

dl( LINE_WIDTH(4 * 16) );

dl( VERTEX2F(60 * 16,25 * 16) );

dl( VERTEX2F(60 * 16,63 * 16) );

dl( COLOR_RGB(128, 128, 0) );

dl( LINE_WIDTH(6 * 16) );

dl( VERTEX2F(90 * 16, 13 * 16) );

dl( VERTEX2F(90 * 16, 63 * 16) );

The VERTEX2F commands are in pairs to define the start and finish point of the line.

Draw rectangle with sizes of 5x25, 10x38 and 15x50 dimensions (line width size is used for corner curvature, LINE_WIDTH pixels are added on both directions in addition to rectangle dimension):

dl( COLOR_RGB(128, 0, 0) );

dl( LINE_WIDTH(1 * 16) );

dl( BEGIN(RECTS) );

dl( VERTEX2F(28 * 16,38 * 16) );

dl( VERTEX2F(33 * 16,63 * 16) );

dl( COLOR_RGB(0, 128, 0) );

dl( LINE_WIDTH(5 * 16) );

dl( VERTEX2F(50 * 16,25 * 16) );

dl( VERTEX2F(60 * 16,63 * 16) );

dl( COLOR_RGB(128, 128, 0) );

dl( LINE_WIDTH(10 * 16) );

22

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

dl( VERTEX2F(83 * 16, 13 * 16) );

dl( VERTEX2F(98 * 16, 63 * 16) );

The VERTEX2F commands are in pairs to define the top left and bottom right corners of the rectangle.

Draw line strips for sets of coordinates:

dl( CLEAR_COLOR_RGB(5, 45, 110) );

dl( COLOR_RGB(255, 168, 64) );

dl( CLEAR(1 ,1 ,1) );

Draw Edge strips for above:

Draw Edge strips for below:

dl( BEGIN(LINE_STRIP) );

dl( VERTEX2F(5 * 16,5 * 16) );

dl( VERTEX2F(50 * 16,30 * 16) );

dl( VERTEX2F(63 * 16,50 * 16) );

dl( CLEAR_COLOR_RGB(5, 45, 110) );

dl( COLOR_RGB(255, 168, 64) );

dl( CLEAR(1 ,1 ,1) );

dl( BEGIN(EDGE_STRIP_A) );

dl( VERTEX2F(5 * 16,5 * 16) );

dl( VERTEX2F(50 * 16,30 * 16) );

dl( VERTEX2F(63 * 16,50 * 16) );

dl( CLEAR_COLOR_RGB(5, 45, 110) );

dl( COLOR_RGB(255, 168, 64) );

dl( CLEAR(1 ,1 ,1) );

dl( BEGIN(EDGE_STRIP_B) );

dl( VERTEX2F(5 * 16,5 * 16) );

23

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

dl( VERTEX2F(50 * 16,30 * 16) );

dl( VERTEX2F(63 * 16,50 * 16) );

24

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Draw Edge strips for right:

dl( CLEAR_COLOR_RGB(5, 45, 110) );

dl( COLOR_RGB(255, 168, 64) );

dl( CLEAR(1 ,1 ,1) );

dl( BEGIN(EDGE_STRIP_R) );

dl( VERTEX2F(5 * 16,5 * 16) );

dl( VERTEX2F(50 * 16,30 * 16) );

dl( VERTEX2F(63 * 16,50 * 16) );

Draw Edge strips for left:

dl( CLEAR_COLOR_RGB(5, 45, 110) );

dl( COLOR_RGB(255, 168, 64) );

dl( CLEAR(1 ,1 ,1) );

dl( BEGIN(EDGE_STRIP_L) );

dl( VERTEX2F(5 * 16,5 * 16) );

dl( VERTEX2F(50 * 16,30 * 16) );

dl( VERTEX2F(63 * 16,50 * 16) );

25

Product Page

static size_t dli; static void dl(unsigned long cmd)

{

wr32(RAM_DL + dli, cmd); dli += 4;

} ...

dli = 0; // start writing the display list dl(CLEAR(1, 1, 1)); // clear screen dl(BEGIN(BITMAPS)); // start drawing bitmaps dl(VERTEX2II(220, 110, 31, 'F')); // ascii F in font 31 dl(VERTEX2II(244, 110, 31, 'T')); // ascii T dl(VERTEX2II(270, 110, 31, 'D')); // ascii D dl(VERTEX2II(299, 110, 31, 'I')); // ascii I dl(END()); dl(COLOR_RGB(160, 22, 22)); // change color to red dl(POINT_SIZE(320)); // set point size dl(BEGIN(POINTS)); // start drawing points dl(VERTEX2II(192, 133, 0, 0)); // red point dl(END()); dl(DISPLAY()); // display the image

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.5.4 Writing display lists

Writing display list entries with wr32() is time-consuming and error-prone, so instead a function might be used:

Code snippet 9 dl function definition

26

Product Page

dl(COLOR_RGB(255, 64, 64)); // red at (200, 120) dl(VERTEX2II(200, 120, 0, 0)); dl(COLOR_RGB(64, 180, 64)); // green at (216, 136) dl(VERTEX2II(216, 136, 0, 0)); dl(COLOR_RGB(255, 255, 64)); // transparent yellow at (232, 152) dl(COLOR_A(150)); dl(VERTEX2II(232, 152, 0, 0));

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.5.5 Bitmap transformation matrix

To achieve the bitmap transformation, the bitmap transform matrix below is specified in the FT800 and denoted as m

  

m = 󰇣

  

󰇤

by default m = 󰇣

     

󰇤, it is named as identity matrix.

The coordinates 󰆒 , 

󰆒

after transforming is calculated in following equation:

󰆒



󰆒



 = m × 󰇩





 

󰇪



i.e.:

󰆒        󰆒     

where A,B,C,E,D,E,F stands for the values assigned by commands

BITMAP_TRANSFORM_A-F.

2.5.6 Color and transparency

The same bitmap can be drawn in more places on the screen, in different colors and transparency:

Code snippet 10 color and transparency

27

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

The COLOR_RGB command changes the current drawing color, which colors the bitmap. The COLOR_A command changes the current drawing alpha, changing the transparency of the drawing: an alpha of 0 means fully transparent and an alpha of 255 is fully opaque. Here a value of 150 gives a partially transparent effect.

2.5.7 VERTEX2II and VERTEX2F

The VERTEX2II command used above only allows positive screen coordinates. If the bitmap is partially off screen, for example during a screen scroll, then it is necessary to specify negative screen coordinates. The VERTEX2F command allows negative coordinates. It also allows fractional coordinates, because it specifies screen (x,y) in units of 1/16 of a pixel.

For example, drawing the same bitmap at screen position (-10,-10) using VERTEX2F:

28

Product Page

dl(BEGIN(BITMAPS)); dl(VERTEX2F(-160, -160)); dl(END());

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Code snippet 11 negative screen coordinates example

29

Product Page

#define SCREEN_WIDTH 480 #define SCREEN_HEIGHT 272

uint32 screenshot[SCREEN_WIDTH*SCREEN_HEIGHT];

wr8(REG_SCREENSHOT_EN, 1);

for (int ly = 0; ly < SCREEN_HEIGHT; ly++) {

wr16(REG_SCREENSHOT_Y, ly); wr8(REG_SCREENSHOT_START, 1);

//Read 64 bit registers to see if it is busy while (rd32(REG_SCREENSHOT_BUSY) | rd32(REG_SCREENSHOT_BUSY + 4));

wr8(REG_SCREENSHOT_READ , 1); for (int lx = 0; lx < SCREEN_WIDTH; lx ++) { //Read 32 bit pixel value from RAM_SCREENSHOT //The pixel format is BGRA: Blue is in lowest address and Alpha

is in highest address

screenshot[ly*SCREEN_HEIGHT + lx] = rd32(RAM_SCREENSHOT + lx*4); } wr8(REG_SCREENSHOT_READ, 0);

}

wr8(REG_SCREENSHOT_EN, 0);

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

2.5.8 Screenshot

The code below demonstrates how to utilize the registers and RAM_SCREENSHOT to capture the current screen with full pixel value. Each pixel is represented in 32 bits and BGRA format. However, this process may cause the flicking and tearing effect.

Code Snippet 12 Screenshot with full pixel value

2.5.9 Performance

The graphics engine has no frame buffer: it uses dynamic compositing to build up each display line during scan out. Because of this, there is a finite amount of time available to draw each line. This time depends on the scan out parameters (REG_PCLK and REG_HCYCLE) but is never less than 2048 internal clock cycles.

Some performance limits:

 The display list length must be less than 2048 instructions, because the

graphics engine fetches display list commands one per clock.

 The graphics engine performance rending pixels is 4 pixels per clock, for any

line with 2048 display commands the total pixels performance drawn must be less than 8192.

 For some bitmap formats, the drawing rate is 1 pixel per clock. These are

TEXT8X8, TEXTVGA and PALETTED.

 For bilinear filtered pixels, the drawing rate is reduced to ¼ pixel per clock.

Most bitmap formats draw at 1 pixel per clock, and the above formats (TEXT8X8, TEXTVGA and PALETTED) draw at 1 pixel every 4 clocks.

30

Product Page

Filter Mode

Format

Rate

Nearest

TEXT8X8, TEXTVGA and PALETTED

1 pixel per clock Nearest

all other formats

4 pixel per clock

BILINEAR

TEXT8X8, TEXTVGA and PALETTED

1/4 pixel per clock BILINEAR

all other formats

1 pixel per clock

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

To summarize:

Table 1 Bitmap rendering performance

31

Product Page

31 8 7 0

Address: 0x10246C Reset Value: 0x0

Note: NONE

REG_PCLK Definition

Bit 0 - 7 : These bits are set to divide the main clock for PCLK. If the typical main clock was 48MHz and the value of these bits are 5, the PCLK will be 9.6 MHz. If the value of these bits are zero, there will be no PCLK output.

R/W

Reserved

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

3 Register Description

In this chapter, all the registers in the FT800 are classified into 5 groups: Graphics Engine Registers, Audio Engine Registers, Touch Engine Registers, and Co-processor Engine Registers as well as Miscellaneous Registers. This chapter gives the detailed definition for each register. To view the register summary of the FT800, please check the datasheet instead.

In addition, please note that all the reserved bits are read-only and shall be zero. All the hexadecimal values are prefixed with 0x. Readers are strongly encouraged to crossreference the other chapters of this document for a better understanding.

3.1 Graphics Engine Registers

Register Definition 1 REG_PCLK Definition

32

Product Page

R/W

31 1 0

Address: 0x102468

Reset Value: 0x0

Note: NONE

Bit 0 : This bit controls the polarity of PCLK. If it is set to zero, PCLK polarity is on the rising edge. If it is set to one, PCLK polarity is on the falling edge.

Reserved

REG_PCLK_POL Definition

R/W

31 1 0

Address: 0x102464

Reset Value: 0x1

Note: NONE

Bit 0 : This bit controls the transition of RGB signals with PCLK active clock edge. When REG_CSPREAD=0, R[7:2],G[7:2] and B[7:2] signals change following the active edge of PCLK. When REG_CSPREAD=1, R[7:2] changes a PCLK clock early and B[7:2] a PCLK clock later, which helps reduce the system noise .

Bit 1 - 31: Reserved.

Reserved

REG_CSPREAD Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 2 REG_PCLK_POL Definition

Register Definition 3 REG_CSPREAD Definition

Please check the sector 2.2.3 for more details.

33

Product Page

31 4 3 0

Address: 0x102460

Reset Value: 0x0

Note: NONE

Bit 0 - 3 : These bits are set to control the arrangement of output RGB pins, which may help support different LCD panel. Please check the table above for details.

Reserved

R/W

REG_SWIZZLE Definition

REG_SWIZZLE

PINS

b3

b2

b1

b0

R7, R6, R5, R4, R3, R2

G7, G6, G5, G4, G3, G2

B7, B6, B5, B4, B3, B2

0 X 0 0 R[7:2]

G[7:2]

B[7:2]

Power on Default

0 X 0 1 R[2:7]

G[2:7]

B[2:7]

0 X 1 0

B[7:2]

G[7:2]

R[7:2]

0 X 1 1

B[2:7]

G[2:7]

R[2:7]

1 0 0 0

G[7:2]

B[7:2]

R[7:2]

1 0 0 1 G[2:7]

B[2:7]

R[2:7]

1 0 1 0 G[7:2]

R[7:2]

B[7:2]

1 0 1 1 G[2:7]

R[2:7]

B[2:7]

1 1 0 0 B[7:2]

R[7:2]

G[7:2]

1 1 0 1

B[2:7]

R[2:7]

G[2:7]

1 1 1 0

R[7:2]

B[7:2]

G[7:2]

1 1 1 1

R[2:7]

B[2:7]

G[2:7]

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 4 REG_SWIZZLE Definition

Table 2 REG_SWIZZLE and RGB pins mapping table

34

Product Page

R/W

31 1 0

Address: 0x10245C Reset Value: 0x1B6

Bit 0 : Set to 1 to enable dithering feature of output RGB signals. Set to 0 to disable dithering feature. Reading 1 from this bit means dithering feature is enabled. Reading 0 from this bit means dithering feature is disabled.

Reserved

Note: Please refer to REG_SWIZZLE and RGB pins mapping table for details

REG_DITHER Definition

31 9 8 0

Address: 0x102458 Reset Value: 0x1B6

Note: NONE

R/W

Reserved

Bit 0 - 8: These 9 bits are split into 3 groups for Red, Green and Blue color output signals: Bit 0 - 2: Blue color signal lines number. Reset value is 6. Bit 3 - 5: Green Color signal lines number. Reset value is 6. Bit 6 - 8: Red Color signal lines number. Reset value is 6. Host can write these bits to control the numbers of output signals for each color.

REG_OUTBITS Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 5 REG_DITHER Definition

Register Definition 6 REG_OUTBITS Definition

35

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

36

Product Page

R/W

31 1 0

Address: 0x102454

Reset Value: 0x00

REG_ROTATE Definition

Note: After rotation is turned on, please do the screen calibration again

Bit 0: 180 degree screen Rotation switch. Writing this bit to 0 will turn off the rotation functionality. Writing this bit to 1 will turn on the rotation functionality and 180 degree rotation will take place at the next frame rendered. Reading this bit will reflect the current rotation switch

Reserved

31 10 9 0

Note: NONE

Bit0 - 9: The value of these bits specifies how many lines for signal VSYNC takes at the start of new frame.

R/W

Address: 0x10244C

Reset Value: 0x00A

REG_VSYNC1 Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 7 REG_ROTATE Definition

Register Definition 8 REG_VSYNC1 Definition

37

Product Page

31 9 0

Note: NONE

REG_VSYNC0 Definition

Bit0 - 9: The value of these bits specifies how many lines for the high state of signal VSYNC takes at the start of new frame.

R/W

Address: 0x102448

Reset Value: 0x000

31 10 9 0

Note:

REG_VSIZE Definition

Bit0 - 9: The value of these bits specifies how many lines of pixels in one frame.

R/W

Address: 0x102444

Reset Value: 0x110

Reserved

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 9 REG_VSYNC0 Definition

Register Definition 10 REG_VSIZE Definition

38

Product Page

31 9 0

Note:

REG_VOFFSET Definition

Bit0 - 9: The value of these bits specifies how many lines takes after the start of new frame.

R/W

Address: 0x102440

Reset Value: 0x00C

Reserved

31 10 9 0

Note:

REG_VCYCLE Definition

Bit0 - 9: The value of these bits specifies how many lines in one frame.

R/W

Address: 0x10243C

Reset Value: 0x124

Reserved

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 11 REG_VOFFSET Definition

Register Definition 12 REG_VCYCLE Definition

39

Product Page

31 9 0

Note: NONE

Bit0 - 9: The value of these bits specifies how many PCLK cycles for HSYNC during start of line.

REG_HSYNC1 Definition

R/W

Address: 0x102438

Reset Value: 0x029

Reserved

31 10 9 0

Note: NONE

Bit0 - 9: The value of these bits specifies how many PCLK cycles of HSYNC high state during start of line.

R/W

Address: 0x102434

Reset Value: 0x0

Reserved

REG_HSYNC0 Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 13 REG_HSYNC1 Definition

Register Definition 14 REG_HSYNC0 Definition

40

Product Page

31 10 9 0

Address: 0x102430

Reset Value: 0x1E0

Note: NONE

Bit0 - 9: These bits are used to specify the numbers of PCLK cycles per horizonal line.

R/W

Reserved

REG_HSIZE Definition

31 10 9 0

Address: 0x10242C Reset Value: 0x2B

Note: NONE

Bit0 - 9: These bits are used to specify the numbers of PCLK cycles before pixels are scanned out.

R/W

Reserved

REG_HOFFSET Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 15 REG_HSIZE Definition

Please reference to section 2.2.1

Register Definition 16 REG_HOFFSET Definition

Please reference to section 2.2.1

41

Product Page

31 9 0

Address: 0x102428

Reset Value: 0x224

Note: NONE

REG_HCYCLE Definition

Bit0 - 9: These bits are the number of total PCLK cycles per horizontal line scan. The default value is 548 and supposed to support 480x272 screen resolution display. Please check the display panel specification for more details.

R/W

Reserved

31 0

Address: 0x102424

Reset Value: 0xFFFFFFFF

Note: NONE

R/W

Bit0 - 31: These bits are used to mask the value of RGB output signals. The result will be used to caculate the CRC value which will be updated into REG_TAP_CRC.

REG_TAP_MASK Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 17 REG_HCYCLE

Please reference to section 2.2.1

Register Definition 18 REG_TAP_MASK

42

Product Page

31 0

Address: 0x102420

Reset Value: 0x00000000

Note: NONE

Read Only

Bit0 - 31: These bits are set by FT800 as the CRC value of RGB signals output. It updates once every time display list is rendered.

REG_TAP_CRC Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 19 REG_TAP_CRC Definition

43

Product Page

Reserved

31 2 1 0

Address: 0x102450 Reset Value: 0x00

REG_DLSWAP Definition

Note:

R/W

Bit 0 - 1: These bits can be set by the host to val i date the dis play list buffer of the FT800. The FT800 gra phics engine wil l determine when to render the screen , depending on what values of these bits are set: 01: Graphics engine will render the screen immediately after current line is scanned out. It may caus e teari ng effect. 10: Graphics engine wil l render the screen immediately after current frame is s canned out. This i s recommended in most of ca s es. 00: Do not write this value into this register. 11: Do not write this value into this register. These bits can be al so be read by the host to check the avai labili ty of the display l i st buffer of the FT800. If the value is read as zero, the displ ay l i st buffer of the FT800 i s safe and ready to wri te. Otherwise, the host needs to wait till it becomes zero.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 20 REG_DLSWAP Definition

44

Product Page

31 8 7 0

REG_TAG Definition

Address: 0x102478

Reset Value: 0x0

Note: Please note the difference between REG_TAG and REG_TOUCH_TAG. REG_TAG is updated based on the X,Y given by REG_TAG_X and REG_TAG_Y. However, REG_TOUCH_TAG is updated based on the current touching point given by FT800 touch engine.

Bit 0 - 7 : These bits are updated with tag value by FT800 graphics engine. The tag value here is corresponding to the touching point coordinator given in REG_TAG_X and REG_TAG_Y. Host can read this register to check which graphics object is touched.

Reserved

R/O

31 9 8 0

Address: 0x102474 Reset Value: 0x0

Note: NONE

REG_TAG_Y Definition

Bit 0 - 8 : These bits are set by host as Y coordinate of touching point, which will enable the host to query the tag value. This register shall be used together with REG_TAG_X and REG_TAG. Normally, in the case the host has already captured the touching point's coordinator, this register can be updated to query the tag value of respective touching point.

Reserved

R/W

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 21 REG_TAG Definition

Register Definition 22 REG_TAG_Y Definition

45

Product Page

31 9 8 0

Address: 0x102470 Reset Value: 0x0

Note: NONE

REG_TAG_X Definition

Bit 0 - 8 : These bits are set by host as X coordinate of touching point, which will enable host to query the tag value. This register shall be used together with REG_TAG_Y and REG_TAG. Normally, in the case the host has already captured the touching point's coordinator, this register can be updated to query the tag value of the respective touching point.

Reserved

R/W

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 23 REG_TAG_X Definition

46

Product Page

Reserved

31 26 25 16 15 10 9 0

REG_TOUCH_DIRECT_Z1Z2 Definition

Address: 0x102578

Note: To know it is touched or not, please check the 31st bit of REG_TOUCH_DIRECT_XY. FT800 touch engine will do the postprocessing for these Z1 and Z2 values and update the result in REG_TOUCH_RZ.

Bit 0 - 9 : The 10 bit ADC value for touch screen resistance Z2. Bit 16-25: The 10 bit ADC value for touch screen resistance Z1.

Reset Value: NA

RO

Reserved

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

3.2 Touch Engine Registers (FT800 only)

Register Definition 24 REG_TOUCH_DIRECT_Z1Z2 Definition

47

Product Page

RO Reserved Reserved

31 26 25 16 15 10 9 0

RO

REG_TOUCH_DIRECT_XY Definition

Address: 0x102574

Note:

Bit 0 - 9 : The 10 bit ADC value for Y coordinate Bit 16-25: The 10 bit ADC value for X coordinate. Bit 31 : If this bit is zero, it means a touch is being sensed and the two fields above contains the sensed data. If this bit is one, it means no touch is being sensed and the data in the two fields above shall be ignored.

Reset Value: 0x0

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 25 REG_TOUCH_DIRECT_XY

48

Product Page

31 30 16 15 0

R/W

REG_TOUCH_TRANSFORM_F Definition

Address: 0x102530

Note: This register represents fixed point number and the default value is +0.0 after reset.

Bit 0 - 15 : The value of these bits represents the fractional part of a fixed point number.

Bit 16 - 30 : The value of these bits represents the integer part of a fixed point number.

Reset Value: 0x0

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 26 REG_TOUCH_TRANSFORM_F Definition

49

Product Page

31 30 16 15 0

R/W

REG_TOUCH_TRANSFORM_E Definition

Address: 0x10252C

Note: This register represents fixed point number and the default value is +1.0 after reset.

Bit 0 - 15 : The value of these bits represents the fractional part of the fixed point number.

Bit 16 - 30 : The value of these bits represents the integer part of the fixed point number.

Bit 31 : The sign bit for fixed point number

Reset Value: 0x10000

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 27 REG_TOUCH_TRANSFORM_E Definition

50

Product Page

31 30 16 15 0

R/W

REG_TOUCH_TRANSFORM_D Definition

Address: 0x102528

Note: This register represents fixed point number and the default value is +0.0 after reset.

Bit 0 - 15 : The value of these bits represents the fractional part of the fixed point number.

Bit 16 - 30 : The value of these bits represents the integer part of the fixed point number.

Bit 31 : The sign bit for fixed point number

Reset Value: 0x0

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 28 REG_TOUCH_TRANSFORM_D Definition

51

Product Page

31 30 16 15 0

R/W

REG_TOUCH_TRANSFORM_C Definition

Address: 0x102524

Note: This register represents fixed point number and the default value is +0.0 after reset.

Bit 0 - 15 : The value of these bits represents the fractional part of the fixed point number.

Bit 16 - 30 : The value of these bits represents the integer part of the fixed point number.

Bit 31 : The sign bit for fixed point number

Reset Value: 0x0

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 29 REG_TOUCH_TRANSFORM_C Definition

52

Product Page

31 30 16 15 0

R/W

REG_TOUCH_TRANSFORM_B Definition

Address: 0x102520

Note: This register represents fixed point number and the default value is +0.0 after reset.

Bit 0 - 15 : The value of these bits represents the fractional part of the fixed point number.

Bit 16 - 30 : The value of these bits represents the integer part of the fixed point number.

Bit 31 : The sign bit for fixed point number

Reset Value: 0x0

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 30 REG_TOUCH_TRANSFORM_B Definition

53

Product Page

31 30 16 15 0

R/W

REG_TOUCH_TRANSFORM_A Definition

Address: 0x10251C

Note: This register represents fixed point number and the default value is +1.0 after reset.

Bit 0 - 15 : The value of these bits represents the fractional part of the fixed point number.

Bit 16 - 30 : The value of these bits represents the integer part of the fixed point number.

Bit 31 : The sign bit for fixed point number

Reset Value: 0x10000

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 31 REG_TOUCH_TRANSFORM_A Definition

54

Product Page

31 8 7 0

Address: 0x102518

Reset Value: 0

Note: The valid tag value range is from 1 to 255 ,therefore the default value of this register is zero, meaning there is no touch by default.

Bit 0 - 7 : These bits are set as the tag value of the specific graphics object on the screen which is being touched. These bits are updated once when all the lines of the current frame is scanned out to the screen. Bit 8 - 31: These bits are reserved.

REG_TOUCH_TAG Definition

RESERVED

RO

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 32 REG_TOUCH_TAG Definition

55

Product Page

31 16 15 0

RO

REG_TOUCH_TAG_XY Definition

Address: 0x102514

Reset Value: 0

Note: Host can read this register to check the coordinates used by the touch engine to update the tag register REG_TOUCH_TAG.

Bit 0 - 15 : The value of these bits are the Y coordinates of the touch screen, which was used by the touch engine to look up the tag result. Bit 16 - 31: The value of these bits are X coordinates of the touch screen, which was used by the touch engine to look up the tag result.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 33 REG_TOUCH_TAG_XY Definition

56

Product Page

31 16 15 0

REG_TOUCH_SCREEN_XY Definition

Address: 0x102510

Note: This register is the final computation output of the touch engine of the FT800. It has been mapped into screen size.

Bit 0 - 15 : The value of these bits are the Y coordinates of the touch screen. After doing calibration, it shall be within the height of the screen size. If the touch screen is not being touched, it shall be 0x8000. Bit 16 - 31: The value of these bits are the X coordinates of the touch screen. After doing calibration, it shall be within the width of the screen size. If the touch screen is not being touched, it shall be 0x8000.

RO

Reset Value: 0x80008000

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 34 REG_TOUCH_SCREEN_XY Definition

57

Product Page

31 16 15 0

REG_TOUCH_RZ Definition

Address: 0x10250C

Reset Value: 0x7FFF

Bit 0 - 15 : These bits are the resistance of touching on the touch screen . The valid value is from 0 to 0x7FFF. The highest value(0x7FFF) means no touch and the lowest value (0) menas the maximum pressure. Bit 16 - 31: Reserved

RO

Reserved

31 16 15 0

REG_TOUCH_RAW_XY Definition

Address: 0x102508

Note: The coordinates in this register have not mapped into the screen coordinates. To get the screen coordinates, please refer to REG_TOUCH_SCREEN_XY .

Bit 0 - 15 : These bits are the raw Y coordinates of the touch screen before going through transformation matrix. The valid range is from 0 to 1023. If there is no touch on screen, the value shall be 0xFFFF. Bit 16 - 31: These bits are the raw X coordinates going through transformation matrix. The valid range is from 0 to 1023. If there is no touch on screen, the value shall be 0xFFFF.

RO

Reserved

Reset Value: 0xFFFFFFFF

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 35 REG_TOUCH_RZ Definition

Register Definition 36 REG_TOUCH_RAW_XY Definition

58

Product Page

31 16 15 0

REG_TOUCH_RZTHRESH Definition

Address: 0x102504

Reset Value: 0xFFFF

Bit 0 - 15 : These bits control the touch screen resistance threshold. Host can adjust the touch screen touching sensitivity by setting this register. The default value after reset is 0xFFFF and it means the lightest touch will be accepted by the touch engine of the FT800. The host can set this register by doing experiments. The typical value is 1200.

R/W

Reserved

31 4 3 0

REG_TOUCH_OVERSAMPLE Definition

Address: 0x102500

Reset Value: 0x7

Bit 0 - 3 : These bits control the touch screen oversample factor. The higher value of this register causes more accuracy with more power consumption, but may not be necessary. The valid range is from 1 to 15.

R/W

Reserved

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 37 REG_TOUCH_RZTHRESH Definition

Register Definition 38 REG_TOUCH_OVERSAMPLE Definition

59

Product Page

31 4 3 0

REG_TOUCH_SETTLE Definition

Address: 0x1024FC

Reset Value: 0x3

Note: .

Bit 0 - 3 : These bits control the touch screen settle time , in the unit of 6 clocks. The default value is 3, meaning the settle time is 18 (3*6) system clock cycles.

R/W

Reserved

31 16 15 0

REG_TOUCH_CHARGE Definition

Address: 0x1024F8

Reset Value: 0x1770

Note: .

Bit 0 - 15 : These bits control the touch-screen charge time, in the unit of 6 system clocks. The default value after reset is 6000, i.e. the charge time will be 6000*6 clock cycles.

R/W

Reserved

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 39 REG_TOUCH_SETTLE Definition

Register Definition 40 REG_TOUCH_CHARGE Definition

60

Product Page

R/W

31 1 0

Reserved

REG_TOUCH_ADC_MODE Definition

Address: 0x1024F4

Reset Value: 0x1

Note: .

Bit 0 : The host can set this bit to control the ADC sampling mode of the FT800, as per: 0: Single Ended mode . It causes l ower power consumption but with le ss accuracy. 1: Differe ntial Mode. It causes higher power consumpti on but with more accuracy. The default mode after reset.

31 2 1 0

Bit 0 - 1 : The host can set these two bits to control the touch screen sampling mode of the FT800 touch engine, as per: 00: Off mode. No sampling happens. 01: Single mode. Cause one single sample to occur. 10: Frame mode. Cause a sample at the start of each frame. 11: Continuous mode. Up to 1000 times per seconds. Default mode after reset.

R/W

Reserved

REG_TOUCH_MODE Definition

Address: 0x1024F0

Reset Value: 0x3

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 41 REG_TOUCH_ADC_MODE Definition

Register Definition 42 REG_TOUCH_MODE Definition

61

Product Page

31 1 0

Address: 0x102488

Reset Value: 0x0

Note: Please refer to the datasheet sector "Sound Synthesizer" for the details of this register.

Bit 0 : A write to this bit triggers the play of synthesized sound effect specified in REG_SOUND. Reading value 1 in this bit means the sound effect is playing. To stop the sound effect, the host needs to select the silence sound effect by setting up REG_SOUND and set this register to play.

Reserved

31 16 15 0

R/W

REG_SOUND Definition

Address: 0x102484

Reset Value: 0x0000

Note: Please refer to the datasheet sector "Sound Synthesizer" for the details of this register.

Bit 0 - 15 : These bits are used to select the synthesized sound effect. They are split into two group Bit 0 - 7, Bit 8- 15. Bit 0 - 7 : These bits define the sound effect. Some of them are pitch adjustable and the pitch is defined in Bits 8 - 15. Some of them are not pitch adjustable and the Bits 8 - 15 will be ignored. Bit 8 - 15: The MIDI note for the sound effect defined in Bits 0 - 7.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

3.3 Audio Engine Registers

Register Definition 43 REG_PLAY Definition

Register Definition 44 REG_SOUND Definition

62

Product Page

31 8 7 0

REG_VOL_SOUND Definition

Address: 0x102480

Reset Value: 0xFF

Note:

Bit 0 - 7 : These bits control the volume of the synthesizer sound. The default value 0xFF is highest volume. The value zero means mute.

Reserved

R/W

31 8 7 0

REG_VOL_PB Definition

Address: 0x10247C

Reset Value: 0xFF

Note:

Bit 0 - 7 : These bits control the volume of the audio file playback. The default value 0xFF is highest volume. The value zero means mute.

Reserved

R/W

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 45 REG_VOL_SOUND Definition

Register Definition 46 REG_VOL_PB Definition

63

Product Page

R/W

31 1 0

REG_PLAYBCK_PLAY Definition

Address: 0x1024BC

Reset Value: 0x0

Note: Please refer to the datasheet section "Audio Playback" for the details of this register.

Reserved

Bit 0 : A write to this bit triggers the start of audio playback, regardless of

writing ‘0’ or ‘1’. It will read back ‘1’ when playback is ongoing, and ‘0’ when

playback completes.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 47 REG_PLAYBACK_PLAY Definition

64

Product Page

R/W

31 1 0

REG_PLAYBACK_LOOP Definition

Address: 0x1024B8

Reset Value: 0x0

Note: Please refer to the datasheet section "Audio Playback" for the details of this register.

Reserved

Bit 0 : this bit controls the audio engine to play back the audio data in RAM_G from the start address once it consumes all the data. A value of 1 means LOOP is enabled, a value of 0 means LOOP is disabled.

Address: 0x1024B4

Reset Value: 0x0

Note: Please read the datasheet section "Audio Playback" for more details.

Bit 0 - 1 : These bits define the format of the audio data in RAM_G. FT800 supports: 00: Linear Sample format 01: uLaw Sample format 10: 4 bit IMA ADPCM Sample format 11: Undefined.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 48 REG_PLAYBACK_LOOP Definition

Register Definition 49 REG_PLAYBACK_FORMAT Definition

65

Product Page

31 16 15 0

REG_PLAYBACK_FREQ Definition

Address: 0x1024B0

Reset Value: 0x1F40

Note: Please read the datasheet section "Audio Playback" for more details.

Bit 0 - 15 : These bits specify the sampling fequency of audio playback data. Units is in Hz.

Reserved

R/O

31 20 19 0

Note: Please read the datasheet section "Audio Playback" for more details.

Bit 0 - 19 : These bits are updated by the FT800 audio engine while playing audio data from RAM_G. It is the current audio data address which is playing back. The host can read this register to check if the audio engine has consumed all the audio data.

Reserved

R/O

REG_PLAYBACK_READPTR Definition

Address: 0x1024AC

Reset Value: 0x00000

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 50 REG_PLAYBACK_FREQ Definition

Register Definition 51 REG_PLAYBACK_READPTR Definition

66

Product Page

31 20 19 0

Note: Please read the datasheet section "Audio Playback" for more details.

Bit 0 - 19 : These bits specify the length of audio data in RAM_G to playback, starting from the address specified in REG_PLAYBACK_START register.

Reserved

R/W

REG_PLAYBACK_LENGTH Definition

Address: 0x1024A8

Reset Value: 0x00000

31 20 19 0

Note: Please read the datasheet section "Audio Playback" for more details.

Bit 0 - 19 : These bits specify the start address of audio data in RAM_G to playback.

Reserved

R/W

REG_PLAYBACK_START Definition

Address: 0x1024A4

Reset Value: 0x00000

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 52 REG_PLAYBACK_LENGTH Definition

Register Definition 53 REG_PLAYBACK_START Definition

67

Product Page

31 14 13 0

REG_CMD_DL Definition

Address: 0x1024EC

Reset Value: 0x0000

Note: .

R/W

Reserved

Bit 0 - 13 : These bits indicate the offset from RAM_DL of a display list command generated by the coprocessor engine. The coprocessor engine depends on these bits to determine the address in the display list buffer of generated display list commands. The coprocessor engine will update this register as long as the display list commands are generated into the display list buffer. By setting this register properly, the host can specify the starting address in the display list buffer for the coprocessor engine to generate display commands. The valid value range is from 0 to 8195.

Address: 0x1024E8

Reset Value: 0x0

Note: FIFO size of command buffer is 4096 bytes and each co-processor instruction is of 4 bytes in size. The value to be written into this register must be 4 bytes aligned.

Bit 0 - 11 : These bits are updated by the host MCU to inform the coprocessor engine of the ending address of valid data feeding into its FIFO. Typically, the host will update this register after it has downloaded the coprocessor commands into its FIFO. The valid range is from 0 to 4095, i.e. within the size of the FIFO.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

3.4 Co-processor Engine Registers

Register Definition 54 REG_CMD_DL Definition

Register Definition 55 REG_CMD_WRITE Definition

68

Product Page

31 12 11 0

Address: 0x1024E4

Reset Value: 0x000

Note: The host shall not write into this register unless in error recovery case. Its default value is zero after the coprocessor engine is reset.

Bit 0 - 11 : These bits are updated by the coprocessor engine as long as the coprocessor engine fetched the command from its FIFO. The host can read this register to determine the FIFO fullness of the coprocessor engine. The valid value range is from 0 to 4095. In the case of error, the coprocessor engine writes 0xFFF to this register.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 56 REG_CMD_READ Definition

Register Definition 57 REG_TRACKER Definition

69

Product Page

31 16 15 0

Address: 0x109000

Reset Value: 0x0

Note: NONE

REG_TRACK Definition

Read Only

Track Value

Tag Value

Bit 16 - 31: These bits are set to indicate the tracking value for the tracked graphics objects.

The coprocessor caculates how much the current touching points take within the predefined

range. Please check the CMD_TRACK for more details.

Bit0 - 15: These bits are set to indicate the tag value of a graphics object which is being

touched.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

3.5 Miscellaneous Registers

In this chapter, the miscellaneous registers covers backlight control, interrupt, GPIO, and other functionality registers.

Register Definition 58 REG_PWM_DUTY Definition

70

Product Page

Reserved

31 8 7 0

R/W

REG_PWM_DUTY Definition

Address: 0x1024C4

Reset Value: 0x80

Note:

Bit 0 - 7 : These bits define the backlight PWM output duty cycle. The valid range is from 0 to 128. 0 means backlight complete off, 128 means backlight in max brightness.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

71

Product Page

31 14 13 0

REG_PWM_HZ Definition

Address: 0x1024C0

Reset Value: 0xFA

Note:

Bit 0 - 13 : These bits define the backlight PWM output frequency in HZ. The default is 250 Hz after reset. The valid frequency is from 250Hz to 10000Hz.

R/W

Reserved

31 8 7 0

Note: Please read the datasheet section "Interrupts" for more details.

Bit 0 - 7 : These bits are used to mask the corresponding interrupt. 1 means to enable the corresponding interrupt source, 0 means to disable the corresponding interrupt source. After reset , all the interrupt source are eligible to trigger interrupt by default.

Reserved

R/W

REG_INT_MASK Definition

Address: 0x1024A0

Reset Value: 0xFF

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 59 REG_PWM_HZ Definition

Register Definition 60 REG_INT_MASK Definition

72

Product Page

R/W

31 1 0

REG_INT_EN Definition

Address: 0x10249C

Reset Value: 0x0

Note: Please refer to the datasheet section "Interrupts" for the details of this register.

Reserved

Bit 0 : The host can set this bit to 1 to enable the global interrupt of FT800. To disable the global interrupt of FT800, the host can set this bit to 0.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 61 REG_INT_EN Definition

73

Product Page

31 8 7 0

Reserved

R/C

REG_INT_FLAGS Definition

Address: 0x102498

Reset Value: 0x00

Note: Please read the datasheet section "Interrupts" for more details.

Bit 0 - 7 : These bits are interrupt flags set by the FT800. The host can read these bits to determine which interrupt takes place. These bits are cleared automatically by reading. The host shall not write this register. After reset, there are no interrupts happen by default , therefore, it is 0x00.

31 8 7 0

Note: Please read the datasheet section "General Purpose IO pins" for more details.

Bit 0 - 7 : These bits are versatile. Bit 0 , 1, 7 are used to control GPIO pin values. Bit 2 - 6 : These are used to configure the drive strength of the pins.

R/W

Reserved

REG_GPIO Definition

Address: 0x102490

Reset Value: 0x00

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 62 REG_INT_FLAGS Definition

Register Definition 63 REG_GPIO Definition

74

Product Page

31 8 7 0

REG_GPIO_DIR Definition

Address: 0x10248C

Reset Value: 0x80

Bit 0 - 7 : These bits configure the direction of GPIO pins of the FT800. Bit 0 controls the direction of GPIO0 and Bit 7 controls the direction of GPIO7. The bit value 1 means the GPIO pin is set as an output, otherwise it means an input. After reset, only the GPIO7 is set to output by default.

R/W

Reserved

RW

31 1 0

Address: 0x10241C Reset Value: 0x00

Bit 1 - 31: Reserved

Bit 0: Write this bit to 1 will set the coprocessor engines of the FT800 into the reset state. Write this bit to 0 will resume from reset state to normal operational mode. If this bit is read as 1, the FT800 coprocessor engines are in reset state. Otherwise, FT800 corpocessor engines are in normal state.

Reserved

REG_CPURESET Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 64 REG_GPIO_DIR Definition

Register Definition 65 REG_CPURESET Definition

75

Product Page

Reserved R/W

31 1 0

Address: 0x102554

Reset Value: 0x0

Bit 0 : Set this bit to enable the readout of screenshot of selected Y line. Bit 1~31: Reserved.

REG_SCREENSHOT_READ Definition

Note: After the REG_SCREENSHOT_BUSY register is clear, this register is required to set before reading out the screenshot of selected Y lines. The screenshot resides in RAM_SCREENSHOT and the format of each pixel is in 32 bit BGRA format: Blue channel is in lowest address and Alpha is in highest address.

63 0

Address: 0x1024D8 Reset Value: 0x0

Read Only

Bit 0～63: Screen shot busy flag. Any non-zero value in these 64 bits represents the busy status of screen shot. Zero value in these 64 bits represents the screen shot is done.

REG_SCREENSHOT_BUSY Definition

Note: After the screen shot is started, host shall read this register to determine when the screen shot is complete.

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 66 REG_SCREENSHOT_READ Definition

Register Definition 67 REG_SCREENSHOT_BUSY Definition

76

Product Page

R/W

31 1 0

Address: 0x102418

Reset Value: 0x0

Note: NONE

Bit 0 : Set this bit to start screen shot if screen shot is already enabled. Screen shot is automatically stopped when screen shot is disabled. Bit 1~31: Reserved.

REG_SCREENSHOT_START Definition

Reserved

31 9

Address: 0x102414

Reset Value: 0x000

Note: NONE

Bit 0~8 : The value of these 9 bits specifies the line number to capture in horizontal direction when screen shot is enabled. Bit 9~31: Reserved.

REG_SCREENSHOT_Y Definition

8 0

Reserved

R/W

31 1 0

Address: 0x102410

Reset Value: 0x0

Bit 0 : Set this bit to enable screen shot for current frame. Clear this bit to disable the screen shot. Bit 1-31: Reserved.

REG_SCREENSHOT_EN Definition

Reserved

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 68 REG_SCREENSHOT_START Definition

Register Definition 69 REG_SCREENSHOT_Y Definition

Register Definition 70 REG_SCREENSHOT_EN Definition

77

Product Page

31 0

Address: 0x10240C Reset Value: 0x2DC6C00

Read / Write

Bit0 - 31: These bits are set 0x2DC6C00 after reset, i.e. The main clock frequency is 48MHz by default. The value is in HZ. If the host selects the alternative frequency by using host command CLK36M, this register must be updated accordingly.

REG_FREQUENCY Definition

31 0

Address: 0x102408

Reset Value: 0x00000000

Read Only

Bit0 - 31: These bits are set to zero after reset. The register counts the number of FT800 main clock cycles since reset. If the FT800 main clock's frequency is 48Mhz, it will wrap around after about 89 seconds.

REG_CLOCK Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 71 REG_FREQUENCY Definition

Register Definition 72 REG_CLOCK Definition

78

Product Page

31 0

Address: 0x102404

Reset Value: 0x00000000

Read Only

Bit0 - 31: These bits are set to zero after reset. The register counts the number of screen frames. If the refresh rate is 60Hz, it will wrap up till about 828 days after reset.

REG_FRAMES Definition

31 8 7 0

Address: 0x102400

Reset Value: 0x7C

Bit0 - 7: These bits are the built-in register ID. The host can read it to determine if the chip is FT800. The value shall always be 0x7C.

Reserved

RO

REG_ID Definition

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 73 REG_FRAMES Definition

Register Definition 74 REG_ID Definition

79

Product Page

31 5 4 0

Address: 0x10256C Reset Value: 0x0

REG_TRIM Definition

Note: Please check the application note AN_299_FT800_FT801_Internal_Clock_Trimming for more details.

Bit 0 - 4: These bits are set to trim the interanl clock. Bit 5 - 31: Reserved

Reserved

R/W

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Register Definition 75 REG_TRIM Definition

80

Product Page

Parameters

Default values

Commands

func & ref

ALWAYS, 0

ALPHA_FUNC

func & ref

ALWAYS, 0

STENCIL_FUNC

Src & dst

SRC_ALPHA, ONE_MINUS_SRC_ALPHA

BLEND_FUNC Cell value

0

CELL

Alpha value

0

COLOR_A

Red, Blue, Green colors

(255,255,255)

COLOR_RGB

Line width in 1/16 pixels

16

LINE_WIDTH

Point size in 1/16 pixels

16

POINT_SIZE

Width & height of scissor

512,512

SCISSOR_SIZE

Starting coordinates of scissor

(x, y) = (0,0)

SCISSOR_XY Current bitmap handle

0

BITMAP_HANDLE

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4 Display list commands

The graphics engine of FT800 takes the instructions from display list memory RAM_DL in the form of commands. Each command is 4 bytes long and one display list can be filled up to 2048 commands since the size of RAM_DL is 8K bytes. The graphics engine of the FT800 performs respective operation according to the definition of commands.

4.1 Graphics State

The graphics state which controls drawing is stored in the graphics context. Individual pieces of state can be changed by the appropriate display list commands (e.g. COLOR_RGB) and the entire state can be saved and restored using the SAVE_CONTEXT and RESTORE_CONTEXT commands.

Note that the bitmap drawing state is special: Although the bitmap handle is part of the graphics context, the parameters for each bitmap handle are not part of the graphics context. They are neither saved nor restored by SAVE_CONTEXT and RESTORE_CONTEXT. These parameters are changed using the BITMAP_SOURCE, BITMAP_LAYOUT, and BITMAP_SIZE commands. Once these parameters are set up, they can be utilized at any display list until they were changed.

SAVE_CONTEXT and RESTORE_CONTEXT are comprised of a 4 level stack in addition to the current graphics context. The table below details the various parameters in the graphics context.

Table 3 Graphics Context

81

Product Page

Parameters

Default values

Commands

Bitmap transform coefficients

+1.0,0,0,0,+1.0,0

BITMAP_TRANSFORM_A-F Stencil clear value

0

CLEAR_STENCIL

Tag clear value

0

CLEAR_TAG

Mask value of stencil

255

STENCIL_MASK

spass and sfail

KEEP,KEEP

STENCIL_OP

Tag buffer value

255

TAG

Tag mask value

1

TAG_MASK

Alpha clear value

0

CLEAR_COLOR_A

RGB clear color

(0,0,0)

CLEAR_COLOR_RGB

Graphics Primitive

Primitive value

BITMAPS

1

POINTS

2

LINES

3

LINE_STRIP

4

EDGE_STRIP_R

5

EDGE_STRIP_L

6

EDGE_STRIP_A

7

EDGE_STRIP_B

8

RECTS

9

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Each display list command in this section lists any graphics context it sets.

4.2 Command encoding

Each display list command has a 32-bit encoding. The most significant bits of the code determine the command. Command parameters (if any) are present in the least significant bits. Any bits marked reserved must be zero.

The graphics primitives supported by FT800 and their respective values are mentioned below

Table 4 FT800 Graphics Primitives list

Various bitmap formats supported by FT800 and their respective values are mentioned below

82

Product Page

Bitmap format

Bitmap format value

ARGB1555

0

L1 1 L4 2 L8 3 RGB332

4

ARGB2

5

ARGB4

6

RGB565

7

PALETTED

8

TEXT8X8

9

TEXTVGA

10

BARGRAPH

11

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Table 5 Graphics Bitmap Format table

4.3 Command groups

4.3.1 Setting Graphics state

ALPHA_FUNC set the alpha test function

BITMAP_HANDLE set the bitmap handle

BITMAP_LAYOUT set the source bitmap memory format and layout for the

current handle

BITMAP_SIZE set the screen drawing of bitmaps for the current handle

BITMAP_SOURCE set the source address for bitmap graphics

BITMAP_TRANSFORM_A-F set the components of the bitmap transform matrix

BLEND_FUNC set pixel arithmetic

CELL set the bitmap cell number for the VERTEX2F command

CLEAR clear buffers to preset values

CLEAR_COLOR_A set clear value for the alpha channel

CLEAR_COLOR_RGB set clear values for red, green and blue channels

CLEAR_STENCIL set clear value for the stencil buffer

CLEAR_TAG set clear value for the tag buffer

83

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

COLOR_A set the current color alpha

COLOR_MASK enable or disable writing of color components

COLOR_RGB set the current color red, green and blue

LINE_WIDTH set the line width

POINT_SIZE set point size

RESTORE_CONTEXT restore the current graphics context from the context stack

SAVE_CONTEXT push the current graphics context on the context stack

SCISSOR_SIZE set the size of the scissor clip rectangle

SCISSOR_XY set the top left corner of the scissor clip rectangle

STENCIL_FUNC set function and reference value for stencil testing

STENCIL_MASK control the writing of individual bits in the stencil planes

STENCIL_OP set stencil test actions

TAG set the current tag value

TAG_MASK control the writing of the tag buffer

4.3.2 Drawing actions

BEGIN start drawing a graphics primitive

END finish drawing a graphics primitive

VERTEX2F supply a vertex with fractional coordinates

VERTEX2II supply a vertex with positive integer coordinates

4.3.3 Execution control

JUMP execute commands at another location in the display list

MACRO execute a single command from a macro register

CALL execute a sequence of commands at another location in the

display list

RETURN return from a previous CALL command

DISPLAY end the display list

84

Product Page

31 24

23 11

10 8

7 6 5 4 3 2 1

0

0x09

Reserved

func

ref

NAME VALUE NEVER 0 LESS 1 LEQUAL 2 GREATER 3 GEQUAL 4 EQUAL 5 NOTEQUAL 6 ALWAYS 7

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.4 ALPHA_FUNC

Specify the alpha test function

Encoding

Parameters

func

Specifies the test function, one of NEVER, LESS, LEQUAL, GREATER, GEQUAL, EQUAL, NOTEQUAL, or ALWAYS. The initial value is ALWAYS (7)

Figure 8: The constants of ALPHA_FUNC

ref

Graphics context

The values of func and ref are part of the graphics context, as described in section

4.1

See also

None

85

Product Page

Specifies the reference value for the alpha test. The initial value is 0

31 24

23 4

3 2 1

0

0x1F

Reserved

prim

NAME VALUE Description BITMAPS 1

Bitmap drawing primitive

POINTS 2

Point drawing primitive

LINES 3

Line drawing primitive

LINE_STRIP 4

Line strip drawing primitive

EDGE_STRIP_R 5

Edge strip right side drawing primitive

EDGE_STRIP_L 6

Edge strip left side drawing primitive

EDGE_STRIP_A 7

Edge strip above drawing primitive

EDGE_STRIP_B 8

Edge strip below side drawing primitive

RECTS 9 Rectangle drawing primitive

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.5 BEGIN

Begin drawing a graphics primitive

Encoding

Parameters

prim

Graphics primitive. The valid value is defined as below:

Table 6 FT800 graphics primitive operation definition

Description

All primitives supported by the FT800 are defined in the table above. The primitive to be drawn is selected by the BEGIN command. Once the primitive is selected, it will be valid till the new primitive is selected by the BEGIN command.

Please note that the primitive drawing operation will not be performed until VERTEX2II or VERTEX2F is executed.

86

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Examples

Drawing points, lines and bitmaps:

dl( BEGIN(POINTS) );

dl( VERTEX2II(50, 5, 0, 0) );

dl( VERTEX2II(110, 15, 0, 0) );

dl( BEGIN(LINES) );

dl( VERTEX2II(50, 45, 0, 0) );

dl( VERTEX2II(110, 55, 0, 0) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(50, 65, 31, 0x45) );

dl( VERTEX2II(110, 75, 31, 0x46) );

Graphics context

None

See also

END

87

Product Page

31 24

23 5

4

3 2 1

0

0x05

reserved

handle

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.6 BITMAP_HANDLE

Specify the bitmap handle

Encoding

Parameters

handle

Bitmap handle. The initial value is 0. The valid value range is from 0 to 31.

Description

Handles 16 to 31 are defined by the FT800 for built-in font and handle 15 is defined in the co-processor engine commands CMD_GRADIENT, CMD_BUTTON and CMD_KEYS. Users can define new bitmaps using handles from 0 to 14. If there is no co-processor engine command CMD_GRADIENT, CMD_BUTTON and CMD_KEYS in the current display list, users can even define a bitmap using handle 15.

Graphics context

The value of handle is part of the graphics context, as described in section 4.1

See also

BITMAP_LAYOUT, BITMAP_SIZE

88

Product Page

31 24

23

22

21

20

19

18 9

8 0

0x07

format

linestride

Height

NAME VALUE ARGB1555 0 L1 1 L4 2 L8 3 RGB332 4 ARGB2 5 ARGB4 6 RGB565 7 PALETTED 8 TEXT8X8 9 TEXTVGA 10 BARGRAPH 11

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.7 BITMAP_LAYOUT

Specify the source bitmap memory format and layout for the current handle.

Encoding

Parameters

format

Bitmap pixel format. The valid range is from 0 to 11 and defined as per the table below.

Table 7 BITMAP_LAYOUT format list

Various bitmap formats supported are:

89

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

BARGRAPH - render data as a bar graph. Looks up the x coordinate in a byte array, then gives an opaque pixel if the byte value is less than y, otherwise a transparent pixel. The result is a bar graph of the bitmap data. A maximum of 256x256 size bitmap can be drawn using the BARGRAPH format. Orientation, width and height of the graph can be altered using the bitmap transform matrix.

TEXT8X8 - lookup in a fixed 8x8 font. The bitmap is a byte array present in the graphics ram and each byte indexes into an internal 8x8 CP437 [2] font (inbuilt font bitmap handles 16 & 17 are used for drawing TEXT8X8 format). The result is that the bitmap

90

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

acts like a character grid. A single bitmap can be drawn which covers all or part of the display; each byte in the bitmap data corresponds to one 8x8 pixel character cell.

TEXTVGA – lookup in a fixed 8x16 font with TEXTVGA syntax. The bitmap is a TEXTVGA array present in the graphics ram, each element indexes into an internal 8x16 CP437 [2] font (inbuilt font bitmap handles 18 & 19 are used for drawing TEXTVGA format with control information such as background color, foreground color and cursor etc). The result is that the bitmap acts like a TEXTVGA grid. A single bitmap can be drawn which covers all or part of the display; each TEXTVGA data type in the bitmap corresponds to one 8x16 pixel character cell.

PALETTED - bitmap bytes are indices into a palette table. By using a palette table which contains 32-bit RGBA colors - a significant amount of memory can be saved. The 256 color palette is stored in a dedicated 1K (256x4) byte RAM_PAL.

linestride

Bitmap linestride, in bytes. Please note the alignment requirement which is described below.

height

Bitmap height, in lines

Description

The bitmap formats supported are L1, L4, L8, RGB332, ARGB2, ARGB4, ARGB1555, RGB565 and Palette.

For L1 format, the line stride must be a multiple of 8 bits; For L4 format the line stride must be multiple of 2 nibbles. (Aligned to byte)

For more details about alignment, please refer to the figures below:

91

Product Page

Byte Order

Pixel 0 Bit 7 Pixel 1 Bit 6

Pixel 7 Bit 0

Byte Order

Pixel 0 Bit 7-4 Pixel 1 Bit 3-0

Byte Order

Pixel 0 Bit 7-0

Byte 0

pixel 1 Bit 15-8

Byte 1

pixel 2 Bit 23-16

Byte 2

L8 format layout

L1 format layout

L4 format layout

Byte 0 Byte 0

……

Byte Order

A Bit 7-6 R Bit 5-4 G Bit 3-2 B Bit 1-0

Byte Order

A Bit 15 R Bit 14-10 G Bit 9- 5 B Bit 4-0

ARGB2 format layout

ARGB1555 format layout

Byte 0

Byte 1 Byte 0

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Figure 9: Pixel format for L1/L4/L8

Figure 10: Pixel format for ARGB2/1555

92

Product Page

Byte Order

A Bit 15-12 R Bit 11-8 G Bit 7-4 B Bit 3-0

Byte Order

R Bit 7-5 G Bit 4-2 B Bit 1-0

Byte Order

R Bit 15-11 G Bit 10-5 B Bit 4-0

Byte Order

A

Bit 31-24

Byte 3

R Bit 23-16

Byte 2

G Bit 15-8

Byte 1

B Bit 7-0

Byte 0

Palette format layout

Byte 0

RGB565 format layout

Byte 1 Byte 0

ARGB4 format layout

RGB332 pixel layout

Byte 1

Byte 0

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Figure 11: Pixel format for ARGB4, RGB332, RGB565 and Palette

Graphics context

None

See also

BITMAP_HANDLE, BITMAP_SIZE, BITMAP_SOURCE

93

Product Page

31 24

23 21

20

19

18

17 9

8 0

0x08

reserved

filter

wrapx

wrapy

width

height

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.8 BITMAP_SIZE

Specify the screen drawing of bitmaps for the current handle

Encoding

Parameters

filter

Bitmap filtering mode, one of NEAREST or BILINEAR

The value of NEAREST is 0 and the value of BILINEAR is 1.

wrapx

Bitmap x wrap mode, one of REPEAT or BORDER

The value of BORDER is 0 and the value of REPEAT is 1.

wrapy

Bitmap y wrap mode, one of REPEAT or BORDER

width

Drawn bitmap width, in pixels

height

Drawn bitmap height, in pixels

Description

This command controls the drawing of bitmaps: the on-screen size of the bitmap, the behavior for wrapping, and the filtering function. Please note that if wrapx or wrapy is REPEAT then the corresponding memory layout dimension (BITMAP_LAYOUT line stride or height) must be power of two, otherwise the result is undefined.

For parameter width and height, the value from 1 to 511 means the bitmap width and height in pixel. The value of zero means the 512 pixels in width or height.

94

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Examples

Drawing a 64 x 64 bitmap:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_SIZE(NEAREST, BORDER, BORDER, 64, 64) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(48, 28, 0, 0) );

Reducing the size to 32 x 50:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_SIZE(NEAREST, BORDER, BORDER, 32, 50) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(48, 28, 0, 0) );

Using the REPEAT wrap mode to tile the bitmap:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_SIZE(NEAREST, REPEAT, REPEAT, 160, 120) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(0, 0, 0, 0) );

95

Product Page

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4X zoom - 128 X 128 - using a bitmap transform:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_TRANSFORM_A(128) );

dl( BITMAP_TRANSFORM_E(128) );

dl( BITMAP_SIZE(NEAREST, BORDER, BORDER, 128, 128) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(16, 0, 0, 0) );

Using a bilinear filter makes the zoomed image a little smoother:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_TRANSFORM_A(128) );

dl( BITMAP_TRANSFORM_E(128) );

dl( BITMAP_SIZE(BILINEAR, BORDER, BORDER, 128, 128) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(16, 0, 0, 0) );

Graphics context

None

See also

BITMAP_HANDLE, BITMAP_LAYOUT, BITMAP_SOURCE

96

Product Page

31 24

23 20

19 0

0x01

Reserved

addr

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.9 BITMAP_SOURCE

Specify the source address of bitmap data in FT800 graphics memory RAM_G.

Encoding

Parameters

addr

Bitmap address in graphics SRAM FT800, aligned with respect to the bitmap format.

For example, if the bitmap format is RGB565/ARGB4/ARGB1555, the bitmap source shall be aligned to 2 bytes.

Description

The bitmap source address is normally the address in main memory where the

bitmap graphic data is loaded.

Examples

Drawing a 64 x 64 bitmap, loaded at address 0:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_SIZE(NEAREST, BORDER, BORDER, 64, 64) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(48, 28, 0, 0) );

Using the same graphics data, but with source and size changed to show only a

32 x 32 detail:

dl( BITMAP_SOURCE(128 * 16 + 32) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_SIZE(NEAREST, BORDER, BORDER, 32, 32) );

97

Product Page

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(48, 28, 0, 0) );

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Graphics context

None

See also

BITMAP_LAYOUT, BITMAP_SIZE

98

Product Page

31 24

23 17

16 0

0x15

Reserved

a

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

4.10 BITMAP_TRANSFORM_A

Specify the A coefficient of the bitmap transform matrix.

Encoding

Parameters

a

Coefficient A of the bitmap transform matrix, in signed 8.8 bit fixed-point form. The initial value is 256.

Description

BITMAP_TRANSFORM_A-F coefficients are used to perform bitmap transform functionalities such as scaling, rotation and translation. These are similar to openGL transform functionality.

Examples

A value of 0.5 (128) causes the bitmap appear double width:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_TRANSFORM_A(128) );

dl( BITMAP_SIZE(NEAREST, BORDER, BORDER, 128, 128) );

dl( BEGIN(BITMAPS) );

dl( VERTEX2II(16, 0, 0, 0) );

A value of 2.0 (512) gives a half-width bitmap:

dl( BITMAP_SOURCE(0) );

dl( BITMAP_LAYOUT(RGB565, 128, 64) );

dl( BITMAP_TRANSFORM_A(512) );

99

Product Page

dl( BITMAP_SIZE(NEAREST, BORDER, BORDER, 128, 128) );

dl( BEGIN(BITMAPS) ); dl( VERTEX2II(16, 0, 0, 0) );

FT800 Series Programmer Guide

Version 2.1

Document Reference No.: BRT_000030 Clearance No.: BRT#037

Graphics context

The value of a is part of the graphics context, as described in section 4.1

See also

None

100

Product Page

Bridgetek FT801, FT800 Programming Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Overview

1.2 Scope

1.3 API reference definitions

2 Programming Model

2.1 General Software architecture

2.2 Display configuration and initialization

2.2.1 Horizontal timing

2.2.2 Vertical timing

2.2.3 Signals updating timing control

2.2.4 Timing example: 480x272 at 60Hz

2.2.5 Initialization Sequence

2.3 Sound Synthesizer

2.4 Audio playback

2.5 Graphics routines

2.5.1 Getting started

2.5.2 Coordinate Plane

2.5.3 Drawing pattern

2.5.4 Writing display lists

2.5.5 Bitmap transformation matrix

2.5.6 Color and transparency

2.5.7 VERTEX2II and VERTEX2F

2.5.8 Screenshot

2.5.9 Performance

3 Register Description

3.1 Graphics Engine Registers

3.2 Touch Engine Registers (FT800 only)

3.3 Audio Engine Registers

3.4 Co-processor Engine Registers

3.5 Miscellaneous Registers

4 Display list commands

4.1 Graphics State

4.2 Command encoding

4.3 Command groups

4.3.1 Setting Graphics state

4.3.2 Drawing actions

4.3.3 Execution control

4.4 ALPHA_FUNC

4.5 BEGIN

4.6 BITMAP_HANDLE

4.7 BITMAP_LAYOUT

4.8 BITMAP_SIZE

4.9 BITMAP_SOURCE

4.10 BITMAP_TRANSFORM_A