1
2
3 4 5 6 7 8 9 10
11
A
B
Optical Input
(1) DIR
C
SPDIF Input
Page = 2 of 5
(2) DSP
Page = 3 of 5
(3) SRC-BiDir
Page = 4 of 5
(4) CPU (I2C)
D
Page = 5 of 5
MB circuit diagram
E
F
G
BLOCK DIAGRAM
OT1-200121
R
H
AuBit
FRAMINGHAM, MA 01701-9168
ControlSpace
ESP-88C/ESP-00 Processors
Dolby/DTS PCB Assy., Rev. B
Part Number 302210
Sheet 1 of 5
R
SPDIFIN
CN100
A
MR552LS(BLK)
B
C
D
E
1
1
2
3
FG103
OPEN
1
2
3
4
OPTIN
FG102
OPEN
1
2
3
4
FG101
FG
Z107
GAP
FG
D100
OPEN
2
L102
BK2125HM102
3
O1I
G
2
Z106
GAP
M100
TORX173
C102
OPEN
5C16
3 4 5 6 7 8 9 10
PP117
L101
NFM21CC223
Z102
GAP
FG
1
OUT
2
GND
3
VCC
4
GND
C2
Z105
GAP
FG
Z101
GAP
Z104
GAP
R101
150
Z100
GAP
Z103
GAP
C104
0.022u
R100
150
PP104
PP116
/RSTDIR
D5V
L100
47uH
C119
0.022u
PP133
D3R3V
C103
0.1uZ
C108
0.022u
PP118
16V10u
0.022u
R102
150
NFM21CC223
1
C101
C115
0.022u
C118
PP119
L103
I
O
G
2
PP130
C117
0.022u
3
PP124
PP132
R106
33k
R105
3.3k
PP122
C116
0.022u
C100
0.1uZ
PP131
PP123
PP121
PP127
PP129
C107
0.022u
C110
1000p
C109
1000p
PP120
R107
10k
9
10
11
12
13
14
1
RXP3
2
RXP2
3
RXP1
4
RXP0
5
RXN
6
VA
7
AGND
8
___
FILT
RST
RXP4
RXP5
RXP6
__
RXP7
AD0/CS
PP128
C106
0.022u
M101
CS8416
CDOUT/SDA
0.022u
OLRCK
OSCLK
SDOUT
OMCK
RMCK
VD
DGND
VL
GPO0
GPO1
GPO2/AD2
CCLK/SCL
CDIN/AD1
C105
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PP113
PP112
PP111
C111
0.1uZ
C113
0.1uZ
PP125
PP115
PP126
R103
10k
PP110
PP109
R104
10k
C112
16V10u
C114
16V10u
PP114
D3R3V
R112
10k
Selection of
soft/hard mode
R111
OPEN
RA100
RA33
1
8
2
7
3
6
4
5
D3R3V
R109
OPEN
R114
0
R110
OPEN
PP108
PP107
PP106
PP105
R108
33
256FS
OMCK = 256FS
PP103
PP102
R113
0
AFSX1
AXR1[4]
DIRFLG1
PP101
PP100
11
ACLKX1
AHCLKX1
DIRFLG0
I2C1_SDA
I2C1_SCL
FG100
C121
22p
PP135
R116
33
I2C1_SDA
C120
F
22p
PP134
R115
33
I2C1_SCL
G
G
(1)DIR
OT1-200121
R
H
AuBit
FRAMINGHAM, MA 01701-9168
ControlSpace
ESP-88C/ESP-00 Processors
Dolby/DTS PCB Assy., Rev. B
Part Number 302210
Sheet 2 of 5
R