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FEATURES
• Up to four DTEs or DCEs per link. Share
the same port, in any combination.
• Compensate for systems having
different clock sources, syncing data
and control-character transmission.
• Ideal for synchronous network
environments.
• Individual subchannels enable and
disable switches.
• Anti-streaming automatically removes
a defective terminal from service.
OVERVIEW
So you want a cost-effective way to expand your existing
leased-line polled network without adding computers or
communication links?
Sure, others offer high-speed modem and port-sharing tools,
but they probably don’t support bidirectional buffering on each
port. To get that, you might have to buy additional tail-circuit
buffers. Do you really want that many boxes in your data
stream?
The simple, affordable solution is the X.21 LS Buffer.
Up to four DTE or DCE devices can share the same port, in
any combination, using the contention and control protocols
normally found in host hardware and software. The ports are
DTE/DCE selectable and meet the ITU X.21 standard, so you can
be assured of synchronous operation in the network by both
data terminal and data circuit equipment.
Once installed, the buffer boosts the efficiency of your system
and network by drawing upon the host processor‘s power and
reducing the idle time associated with many host-terminal traffic
sessions. The buffer temporarily stores information sent and
received between multiple devices with different data-handling
speeds and abilities. It then releases the data at slower speeds.
Ideal for synchronous network environments, the X.21 LS
is protocol-transparent at data rates up to 1.024 Mbps. Data
arrives at the master port and is continually broadcast to all
subchannels.
The 512-bit buffer also clocks data between different
network carriers, synchronizing the transmission of data and
control characters. This adjustable capacity and data clocking
make it an ideal choice for VSAT or land-line applications. It
reclocks data when the clock rate is at the same rate, but it
won’t lock onto the frequency of the different network carriers,
so no external tail-circuit buffers are needed. This elastic tailcircuit buffer compensates for different clock sources. Clocking
may be accomplished from any port of the unit, and two modes
are available for fallback clocking.
In applications where both the master port and the selected
port provide their own clocks, data is clocked into the buffer at
the receive rate of the active port and clocked out using the
master port transmit clock.
What’s more, the 4-port buffers feature a Channel 4-only
mode, which forces Port 4 as the active port to the master port.
Data and clock are then rebroadcast out to Ports 1–3 after
passing through the master port.
And, unlike most other sharing devices, the buffer can
be adjusted as your network changes. Using FieldProgrammable Gate Array (FPGA) technology, you’re able
to reprogram the buffer when sharing devices are added,
so the X.21 LS can, therefore, grow with your network
without needing new hardware. Your investment is
protected.
The X.21 LS is housed in a sturdy rackmount metal
enclosure and is equipped with a 110/220-VAC switchselectable linear power supply.
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The X.21 LS Buffer also features the following functions:
Automatic Removal—The buffer contains circuitry that,
when enabled, will automatically remove a streaming DCE
or DTE from service.
Each channel has a green and yellow LED to indicate
subchannel activity. If a terminal goes into the streaming
condition (Control continually high), the DTE will automatically be removed from service until you correct the
DTE fault. All other DTEs will continue to be serviced.
Upon installation, you can set or fine-tune the timer
to your network requirements.
Internal Clock Selection —The device also provides circuitry
that allows you to select internal clocks. Though the X.21 LS is
externally timed by the telco provider, the internal clock rates
are very useful for testing and diagnostic purposes.
Subchannel Scanning—This allows equal access to the
communications link for all connected DCE or DTE devices.
The subchannels are scanned in sequence, and the attached
subchannel that raises Control (C) or Indicate (I) will have
access to the communications link. After the subchannel drops
(C) or (I), the buffer will continue scanning in sequential order.
Technically Speaking