BBK DL3103DC Schematics C3103R-1
321
4
D
1.0 INPUT& RT2011.sch
C3103-11.sch
C
B
2.0 DC_DC & G a m ma.sch
C3103-12.sch
3.0 PANE L.sch
C3103-13.sch
4.0 MCU. sch
C3103-14.sch
ECN.sch
ECN.sch
D
C
B
A
1 2 34
Title
B
Date: 31-Mar-20 05 Sheet of
File: F:\P- DV D\D L 31 03\C 3103R -1. DDB Drawn By:
DL3103 驱动板原理图
Number RevisionSize
15
A
Page 1 of 5 2005-3-31 10:16
151413121110987654321
FB109
3DVCC
FBSMT
1 2
1 2
C150
0.1uF
T47uF/16V
C151
0.1uF
C152
0.1uF
1 2
12
12
+
12
+
C111
C153
0.1uF
1 2
PLL_GND
1
R113
100K
C174
T10uF/16V
1 2
B
R105 1M-10M
C156 47nF
G
R
C155
0.1uF
1 2
C154
C157
0.1uF
0.1uF
1 2
1 2
1TP102
C112
C113
0.1uF
0.1uF
1 2
AHS
AVS
C158 47nF
C160 47nF
12
C167
22pF
C168
12
22pF
1
2
3
4 5
1
2
3
4 5
RTD_SCK
RTD_SDIO
RTD_SCS
C114
0.1uF
1 2
1 2
0.1uF
12
R117
1M
C115
0.1uF
1 2
C161
12
12R115 10k
12R116 100ohm
8RP101
7
6
33RP
8RP102
7
6
33RP
C116
0.1uF
1 2
101
103
94
93
92
96
95
99
98
97
90
91
88
89
100
87
78
77
79
82
84
83
85
86
75
76
73
Y101
24.576MHz
74
80
81
122
114
115
116
117
118
119
120
121
C117
0.1uF
1 2
GNDO9GNDO24GNDO37GNDO52GNDO65GNDO
AHS
AVS
ADC_B_ VDD
B
ADC_B_ GND
SOG
G
ADC_R_ VDD
R
ADC_R_ GND
ADC_VDD
ADC_GND1
ADC_GND0
ADC_REFIO
GUARD_VDD
GUARD_GND
DPLL_VDD
DPLL_GND
APLL1_ VDD
APLL1_ GND
APLL2_ VDD
APLL2_ GND
APLL3_ VDD
APLL3_ GND
PLL_GUARD_VDD
PLL_GUARD_GND
XI
XO
PLL_TEST1
PLL_TEST2
BCLK
B0
B1
B2
B3
B4
B5
B6
B7
1 2
R103
1K
3PVCC
1 2R101 33ohm
1 2R102 33ohm
R104
2K
1 2
3AVCC
C143
0.1uF
1 2
C142
0.1uF
1 2
PCB
3DVCC
FB127
FBSMT
R430
DNC
FB125
FBSMT
铜皮处理
ADC_VCC
12
12
+
C144
22uF/16V
PLL_GND
C145
22pF
1 2
12
+
C146
22uF/16V
1 2
C110
0.1uF
1 2
1 2
C147
12pF
C148
0.1uF
1 2
C149
0.1uF
C178 22pF
PANEL_PW
C179 22pF
J101
1
1
2
2
FB101 FBSMT
D
C
10
11
12
13
14
15
16
17
18
19
20
CON20
J102
10
11
12
13
14
15
16
17
18
19
20
CON20
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
FB102 FBSMT
FB103 FBSMT
FB104 FBSMT
FB105 FBSMT
FB106 FBSMT(DNS)
FB129 FBSMT
FB10 7 120 Ohm
FB108 FBSMT
FB114 FBSMT
FB115 FBSMT
FB116 FBSMT
FB117 FBSMT
FB118 FBSMT
FB119 FBSMT
FB120 FBSMT
FB121 FBSMT
FB122 FBSMT
FB123 FBSMT
FB124 FBSMT
3
3
PANEL_PW
RTD_RESET
N/P
RTD_SCK
RTD_SCS
RTD_SD IO
1R#
VCC
BL-SW
BL-GND
BL-9V
B/VGA
G/VGA
R/VGA
HSIN
VSIN
CKB
UV0
UV1
UV2
UV3
UV4
UV5
UV6
UV7
RTD_RESE T
N/P
RTD_SCK
RTD_SCS
RTD_SD IO
1R#
VCC
BL-SW
BL-9V
B/VGA
G/VGA
R/VGA
HSIN
VSIN
CKB
UV0
UV1
UV2
UV3
UV4
UV5
UV6
UV7
C102 22pF
C103 22pF
C104 22pF
C105 22pF（ＤＮＳ）
C106 22pF
1 2C101 T100uF/16V
C107 0.1uF
C108 22pF
C109 0.1uF
C180 TVS
C180 TVS
C182 TVS
C135 22pF
C136 22pF
C137 22pF
C128 22pF
C138 22pF
C129 22pF
C139 22pF
C130 22pF
C140 22pF
C131 22pF
C141 22pF
HSIN
VSIN
3PVCC
3AVCC
input interfac e
L103
R112
100ohm
C163
5p
R111 100ohm
C164
5p
R124 100ohm
C172
5p
C165
22pF
C166
22pF
C173
22pF
B
CKB
UV0
UV1
UV2
UV3
UV4
UV5
UV6
G
R
UV7
RTD_RESET
RESET BY 8051
CKB
UV0
UV1
UV2
UV3
UV4
UV5
UV6
UV7
R3DVCC
L102
R108
75ohm
R109
75ohm
R123
75ohm
FEB_0603
L101
FEB_0603
FEB_0603
B/VGA
D101
B
3
BAT54S
D102
3
BAT54S
D103
3
A
BAT54S
3AVCC
2
2
3
1
1
G/VGA
3AVCC
2
2
3
1
1
R/VGA
3AVCC
2
2
3
1
1
R3DVCC 2.5DVCCR2.5 DVCC
C119
C120
C121
C118
0.1uF
0.1uF
1 2
102
105
124
GNDO
GNDO
106
VCCO10VCCO23VCCO38VCCO51VCCO66VCCO
123
VCCO
VCCK11VCCK26VCCK54VCCK71VCCK
0.1uF
1 2
1 2
126
109
39
VCCK
VCCK
GNDK12GNDK25GNDK53GNDK72GNDK
RTD201 1
PWM031PWM1/REF_CLK32DDC_SCL
SDI/SDO
SCLK
SCSB
RESET#
112
113
111
104
DDC_SDA
108
107
R126
100ohm
12
R127
100ohm
12
0.1uF
1 2
40
GNDK
DHS33DCLK34DVS60DEN
110
DBBLU0
DBBLU1
DBBLU2
DBBLU3
DBBLU4
DBBLU5
DBBLU6
DBBLU7
DBGRN0
DBGRN1
DBGRN2
DBGRN3
DBGRN4
DBGRN5
DBGRN6
DBGRN7
DBRED0
DBRED1
DBRED2
DBRED3
DBRED4
DBRED5
DBRED6
DBRED7
DABLU0
DABLU1
DABLU2
DABLU3
DABLU4
DABLU5
DABLU6
DABLU7
DAGRN0
DAGRN1
DAGRN2
DAGRN3
DAGRN4
DAGRN5
DAGRN6
DAGRN7
DARED0
DARED1
DARED2
DARED3
DARED4
DARED5
DARED6
DARED7
59
DDC_SDA
DDC_SCL
C122
0.1uF
1 2
125
GNDK
Title
A0
Date: 31-Mar-2005 Sheet of
File: F: \P- D V D \D L3103 \C3 103R- 1.D D B Drawn B y:
C123
0.1uF
1 2
127
128
1
2
3
4
5
6
7
8
13
14
15
16
17
18
19
20
21
22
27
28
29
30
35
36
41
42
43
44
45
46
47
48
49
50
55
56
57
58
61
62
63
64
67
68
69
70
Pin Na mes Visible
Pin Numbers Visible
Pin Nu mber s Visib le
TCON-1
TCON-0
TCON-ECLK
DDC_SDA
DDC_SCL
DL3103驱动板原理图
Number RevisionSize
C124
0.1uF
1 2
BOA0
BOA1
BOA2
BOA3
BOA4
BOA5
GOA0
GOA1
GOA2
GOA3
GOA4
GOA5
ROA0
ROA1
ROA2
ROA3
ROA4
ROA5
1 2R122 33ohm
1 2R121 33ohm
1 2R128 33ohm
12R118 33ohm
12R119 33ohm
12R120 33ohm
1 2
C125
0.1uF
12
+
C126
T47uF/10V
DGND
12R106 33ohm
STH
STV
CKH
C175
12pF
DGND
FB110
FBSMT
C169
20pF(DNS)
25
C176
20pF(DNS)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DGND
BOA[0:5]
CPV
GOA[0:5]
DGND
POL
LD
DGND
ROA[0:5]
1 2
C127
0.1uF
OE
2.5DVCC
OE
C162
20pF(DNS)
CPV
C170
20pF(DNS)
POL
LD
C171
20pF(DNS)
STH
STV
CKH
C177
20pF(DNS)
DGND
16
D
C
B
A
Page 2 of 5 2005-3-31 10:16
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