2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES)DEVICES
3. CONTROL BUTTON LOCATIONS AND EXPLANATIONS
4. PREVERTION OF STATIC ELECTRICITY DISCHARGE
5. ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT
5.1 OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST
5.2 MISCELLANEOUS
6. ELECTRICAL CONFIRMATION
6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION
6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION
7. MPEG BOARD CHECK WAVEFORM
1
1
2
3
4
4
6
7
7
8
9
8. IC BLOCK DIAGRAM & DESCRIPTION
8.1 MT133610
8.2 MT1379
8.3 AM29LV160D34
8.4 HY57V641620HG
9. SCHEMATIC & PCB WIRING DIAGRAM
10. SPARE PARTS LIST57
10
18
39
42
1.1 GENERAL GUIDELINES
1. SAFETY PREAUTIONS
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO
ELECTROSTATICALLY SENSITIVE(ES)DEVICES
1
1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have
been overheated or damaged by the short circuit.
2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers
shields are properly installed.
3. After servicing, make the following leakage current checks to prevent the customer from being exposed
to shock hazards.
Some semiconductor(solid state)devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive(ES)Devices. Examples of typical ES devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain
off any ESD on your body by touching a known earth ground. Alternatively, obtain and wear a commercially
availabel discharging ESD wrist strap, which should be removed for potential shock reasons prior to
applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES
devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are
ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam, alminum foil or comparable conductive material).
7. Immediately before removing the protective material from the leads of a replacement ES device, touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD).
notice (1885x323x2 tiff)
Fr ont Panel I l l u s t r at i o n
2
2
Power indicator
2
IR SENSOR
3
4
OPEN/CLOSE button
5
PLAY/PAUSE button
54679
7
PREV button
8
8
NEXT button
3
Display window
6
STOP button
9
POWER switch
The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
body. Use due caution to electrostatic breakdown when servicing and handling the laser diode.
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
1. Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the
3. The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
3
4.PREVENTION OF STATIC ELECTRICITY DISCHARGE
4.1.Grounding for electrostatic breakdown prevention
grounding works is completed.
4.1.1. Worktable grounding
sheet.
4.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity from your body.
safety_3 (1577x409x2 tiff)
4.1.3.Handling of optical pickup
1. To keep the good quality of the optical pickup maintenance parts during transportation and before
installation, the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure. (See this Technical Guide).
2. Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
4.2. Handling precautions for Traverse Unit (Optical Pickup)
1. Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2. When replacing the optical pickup, install the flexible cable and cut is short land with a nipper. See the
optical pickup replacement procedure in this Technical Guide. Before replacing the traverse unit, remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
4. The half-fixed resistor for laser power adjustment cannot be adjusted. Do not turn the resistor.
5.1 Optical pickup Unit Explosed View and Part List
5. Assembling and disassembling the mechanism unit
4
Pic (1)
Materials to Pic (1)
5
No. PARTS CODE PARTS NAME Qty
14692200 SF-HD60 1
1
1EA0311A06300 ASSY, CHASSIS, COMPLETE 1
2
Or
3
4
5
6
7
8
9
10
11
21
Or
31
32
1EA0M10A15500 ASSY, MOTOR, SLED 1
1EA0M10A15501 ASSY, MOTOR, SLED 1
1EA2451A24700 HOLDER, SHAFT 3
1EA2511A29100 GEAR, RACK 1
1EA2511A29200 GEAR, DRIVE 1
1EA2511A29300 GEAR, MIDDLE, A 1
1EA2511A29400 GEAR, MIDDLE, B 1
1EA2744A03000 SHAFT, SLIDE 1
1EA2744A03100 SHAFT, SLIDE, SUB 1
1EA2812A15300 SPRING, COMP, TYOUSEI 3
1EA2812A15400 SPRING, COMP, RACK 1
1EA0B10B20100 ASSY, PWB 1
1EA0B10B20200 ASSY, PWB 1
SEXEA25700--- SPECIAL SCREW BIN+-M2X11 3
SEXEA25900--- SPECIAL SCREW M1.7X2.2 2
33
34
35
Note : This parts list is not for service parts supply.
SFBPN204R0SE- SCR S-TPG PAN 2X4 2
SFSFN266R0SE- SCR S-TPG FLT 2.6X6 1
SWXEA15400--- SPECIAL WASHER 1.8X4 X0.25 2
2 MISCELLANEOUS
6
5.
5.2.1 Protection of the LD(Laser diode)
Short the parts of LD circuit pattern by soldering.
5.2.2 Cautions on assembly and adjustment
Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are
grounded,and that personnel wear wrist straps for ground.
Open the LD short lands quickly with a soldering iron after a circuit is connected.
Keep the power source of the pick-up protected from internal and external sources of electrical
noise.
Refrain from operation and storage in atmospheres containing corrosive gases (such as H2S,SO2,
NO2 and Cl2)or toxic gases or in locations containing substances(especially from the organic silicon,cyan,
formalin and phenol groups)which emit toxic gases.It is particularly important to ensure that none of the
above substances are present inside the unit.Otherwise,the motor may no longer run.
6.1. Video Output (Luminance Signal) Confirmation
6.Electrical Confirmation
7
DO this confirmation after replacing a P.C.B.
Measurement point
Video output terminal
Measuring equipment,tools
200mV/dir,10sec/dir
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
ModeDisc
Color bar 75%
Confirmation value
1000mVp-p±30mV
DVDT-S15
or
DVDT-S01
Do the confirmation after replacing P.C.B.
Screwdriver,Oscilloscope
6.2 Video Output(Chrominance Signal) Confirmation
8
Measurement point
Video output terminal
Measuring equipment,toolsConfirmation value
200mV/dir,10sec/dir
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
ModeDisc
Color bar 75%
621mVp-p±30mV
DVDT-S15
or
DVDT-S01
7.MPEG BOARD CHECK WAVEFORM
7.1 27MHz WAVEFORM
7.2 IC TEA1523 PIN.8 WAVEFORM DIAGRAM
9
8.1 MT1336
8. IC BLOCK DIAGRAM & DESCRIPTION
10
PRELIMINARY, SUBJ ECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1336
GENERAL DESCRIPTION
MT1336 is a high performance CMOS analog front-end IC for both CD_ROM driver up to 48XS and
DVD-ROM driver up to 16XS. It also supports DVD-RAM read up to 4XS Version 2. It contains servo amplifiers
to generate focusing error, 3-beam tracking error, 1 beam radial push-pull signal, RF level and SBAD for servo
functions. It also includes DPD tracking error signal for DVD_ROM application. For DVD- RAM disks, there are
also Differential Push-Pull (DPP) method for generating tracking signal and Differential Astigmatic Detection
(DAD) for processing focusing signal. Programmable equalizer and AGC circuits are also incorporated in this
chip to optimize read channel performance. In addition, this chip has dual automatic laser power control circuits
for DVD- ROM (DVD-RAM) and CD -ROM seperately and reference voltage generators to reduce external
components. Programmable functions are implemented by the access of internal register through bi-directional
serial port to configure modes selection.
FEATURES
n RF equalizer with programmable
13dB.
n MT1336 supports at least eight different kinds of pick-up heads with versatile input configuration for
both RF input stages and servo signal blocks.
n Versatile on -line AGC.
n 3 beams tracking error signal generator for CD_ROM application.
n One beam differential phase tracking error (DPD) generator for DVD_ROM application.
n Differential push pull tracki ng error (DPP) generator for DVD_RAM application.
n Focusing error signal generator for CD-ROM, DVD-ROM and DVD-RAM (DAD method).
n RF level signal generator.
n Sub-beam added signal for 3 beams CD_ROM.
n One beam push-pull signal generator for central servo application.
n High speed RF envelop detection circuit with bandwidth up to 400KHz for CD-ROM.
n Defect and Blank detection circuits.
from 3MHz to 70 MHz and programmable boost from 3dB to
f
c
n Dual automatic laser power control circuits with programmable level of LD monitor voltage.
n Vref=1.4V voltage and V2ref=2.8V voltage generators.
n V20=2.0V voltage for pick-up head reference.
n Bi-directional serial port to access internal registers.
MT1336
11
PRELIMINARY, SUBJ ECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
DVDA
CDA
DVDB
CDB
DVDC
CDC
DVDD
CDD
DVDRFIN
DVDRFIP
MA
MB
MC
MD
SA
SB
SC
SD
DPFN
DPFO
IR
DPDMUTE
TPI
TNI
CDFOP
CDFON
RFGC
RFGCU
RFGCI
AGC1
AGC2
AGC3
RFSUBO
WOBSO
V20
V2REFO
VREFO
ATTENUATOR
INPUT MUX
WOBBLE
DET
VGA
VGAEQ
AGC
AGC
DPD
SBAD
TE
RF
LEVEL
FE
CENTRAL
SERVO
REF and 2VREF
REF and 2VREF
Voltage Generator
Voltage Generator
ENVELOP
ENVELOP
DETECTOR
DETECTOR
PCS
DVD
APC
CD
APC
SERIAL
PORT
OSP
OSN
RFOP
RFON
LRFRP
DEFECT
HRFRP
CRTP
CRTPLP
CSO
LVL
TEO
FEO
REFCOS
HALLCOS
COSPHI
REFSIN
HALLSIN
SINPHI
MDI2
LDO2
MDI1
LDO1
UDGATE
IDGATE
VFO13
SDATA
SLCK
SDEN
MT1336 FUNCTION BLOCKS DIAGRAM
12
MT1336
PRELIMINARY, SUBJ ECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Programmable frequency error gain and phase
error gain of spindle PLL to control spindle motor
on CLV and CAV mode
§
Provide a varipitch speed control for CLV and CAV
mode
§
Built-in ADCs and DACs for digital servo control
§
Provide 2 general PWM
Progressive Scan DVD Player Combo Chip
§
Tray control can be PWM output or digital output
§
Built-in DSP for digital servo control
n Host Micro controller
§
Built-in 8032 micro controller
§
Built-in internal 373 and 8-bit programmable
MT1379
lower address port
§
1024-bytes on-chip RAM
§
Up to 2M bytes FLASH -programming interface
§
Supports 5/3.3-Volt. FLASH interface
§
Supports power-down mode
§
Supports additional serial port
n DVD-ROM/CD-ROM Decoding Logic
§
Supports CD-ROM Mode 1, CD-ROM XA Mode 2
Form 1, CD-ROM XA Mode 2 Form 2, and CD -DA
formats
§
High-speed ECC logic capable of correcting one
error per each P -codeword or Q-codeword
§
Automatic sector Mode and Form detection
§
Automatic sector Header verification
§
8-bit counter for decode completion check
§
Programmable descrambling and error
correction schemes
§
Automatically repeated error corrections
§
8-bit C2 Pointer counter
§
Decoder Error Notification Interrupt that signals
various decoder errors
§
Provide error correction acceleration
n Buffer Memory Controller
§
Supports 16Mb/32Mb/64Mb/128Mb SDRAM
§
Supports 16-bit/32-bit SDRAM data bus interface
§
Build in a DRAM interface programmable clock to
optimize the DRAM performance
§
Provide the se lf-refresh mode SDRAM
§
Programmable DRAM access cycle and refresh
19
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1379
cycle timings
§
Block-based sector addressing
§
Programmable buffering counter for buffer status
tracking
§
Maximum DRAM speed is 133MHz
§
Support 5/3.3-Volt. DRAM Interface
n Video Decode
§
Decodes MPEG 1 video and MPEG2 main level,
main profile video (720/480 and 720x576)
§
Maximum input bit -rate of 15Mbits/sec
§
Smooth digest view function with I, P and B
picture decoding
§
Baseline, extended-sequential and progressive
JPEG image decoding
§
RLE and non-RLE BMP image decoding
§
Support CD-G titles
n Video/OSD/SPU/HLI Processor
§
Arbitrary ratio vertical/horizontal scaling of video,
from 0.25X to 256X
§
65535/256/16/4/2-color bitmap format OSD,
§
256/16 color RLC format OSD
§
Automatic scrolling of OSD image
§
Provides 4-color/32x32-pixel hardware cursor
§
Fade-in, Fade out, and Wipe functions as
specified in the DVD-Audio Specification and
other slide show transition effects
§
Progressive scan output
n Audio Processing
§
Decoder format supports:
- Dolby Digital (AC-3) decoding
- DTS decoding
- MLP decoding for DVD-Audio
- MPEG-1 layer 1/layer 2 audio decoding
- MPEG-2 layer1/layer2 2-channel audio decoding
- Dolby Pro Logic decoding
- High Definition Compatible Digital (HDCD)
decoding
§
Up to 6 channel linear PCM output for DVD Audio
/ DVD Video
§
Downmix function
§
Support IEC 60958/61937 output
- PCM / bit stream / mute mode
- Custom IEC latency up to 2 frames
§
Pink noise and white noise generator
§
Karaoke functions
- Microphone echo with adjustable echo level,
echo -depth and delay length
- Microphone tone control with three custom
second-order IIR filter
- Vocal mute/vocal assistant
- Key shift up to +/- 8 keys controlled by 1/2 key
§
Channel equalizer
§
3D surround processing include virtual surround
and speaker separation
§
Power-down control
§
HDCD certified
n TV Encoder
§
Six 54MHz/12bit DA converters
§
Support NTSC, PAL-BDGHI, PAL-N, PAL-M
interlace TV format and 480p, 576p progressive
TV format
§
Automatically turn off unconnected channel(s).
§
Support PC monitor (VGA)
§
Support Macrovision 7.1
n Progressive Output
§
Automatic detect film or video source
§
3:2 pull down source detection
§
Advanced Motion adaptive de-interlace
§
Minimum external memory requirement
n Audio/Video Output
§
Line-in/SPDIF-in for versatile audio processing
§
CCIR601/656 video input port
§
Support picture -in-picture for video decoding and
input source
n Outline
§
216-pin LQFP package
§
3.3/2.5-Volt. Dual operating voltages
The 2nd general PWM output
20
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1379
P
IN DEFINITIONS
Pin Number Symbol Type Description
1 IREF Analog Input Current reference input. It generates reference current for data
2 PLLVSS Ground Ground pin for data PLL and related analog circuitry
3 LPIOP Analog Output Positive output of the low pass filter
4 LPION Analog Output Negative output of the low pass filter
5 LPFON Analog output Negative output of loop filter amplifier
6 LPFIP Analog Input Positive input of loop filter amplifier
7 LPFIN Analog Input Negative input of loop filter amplifier
8 LPFOP Analog Output Positive output of loop filter amplifier
9 JITFO Analog Output RF jitter meter output
10 JITFN Analog Input Negative input of the operation amplifier for RF jigger meter
11 PLLVDD3 Power 3.3V power pin for data PLL and related analog circuitry
12 FOO Analog Output Focus servo output. PDM output of focus servo compensator
13 TRO Analog Output Tracking servo output. PDM output of tracking servo compensator
14 TROPENPWM Analog Output Tray open output, controlled by microcontroller.
15 PWMOUT1 Analog Output The 1st general PWM output
16 PWMOUT2 Analog Output
17 DVDD2 Power 2.5V power pin for internal fully digital circuitry
18 DMO Analog Output Disk motor control output. PWM output
19 FMO Analog Output Feed motor control. PWM output
20 DVSS Ground Ground pin for internal fully digital circuitry
21 FG Input Motor Hall sensor input
22 HIGHA0 Inout
23 HIGHA1 Inout
24 HIGHA2 Inout
25 HIGHA3 Inout
26 HIGHA4 Inout
27 HIGHA5 Inout
28 DVSS Grou nd Ground pin for internal digital circuitry
PLL.
Connect an external 100K resistor to this pin and PLLVSS.
This is PWM output for TRWMEN27hRW2=1 or is digital output for
TRWMEN27hRW2=0
Microcontroller address 8
2~16MA, SR
PU
Microcontroller address 9
2~16MA, SR
PU
Microcontroller address 10
2~16MA, SR
PU
Microcontroller address 11
2~16MA, SR
PU
Microcontroller address 12
2~16MA, SR
PU
Microcontroller address 13
2~16MA, SR
PU
21
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Pin Number Symbol Type Description
29 HIGHA6 Inout
30 HIGHA7 Inout
31 AD7 Inout
32 AD6 Inout
33 AD5 Inout
34 AD4 Inout
35 DVDD3 Power 3.3V power pin for internal digital circuitry
36 AD3 Inout
37 AD2 Inout
38 AD1 Inout
39 AD0 Inout
40 IOA0 Inout
41 IOA1 Inout
42 DVDD2 Power 2.5V power pin for internal digital circuitry
43 IOA2 Inout
44 IOA3 Inout
45 IOA4 Inout
46 IOA5 Inout
47 IOA6 Inout
Microcontroller address 14
2~16MA, SR
PU
Microcontroller address 15
2~16MA, SR
PU
Microcontroller address/data 7
2~16MA, SR
Microcontroller address/data 6
2~16MA, SR
Microcontroller address/data 5
2~16MA, SR
Microcontroller address/data 4
2~16MA, SR
Microcontroller address/data 3
2~16MA, SR
Microcontroller address/data 2
2~16MA, SR
Microcontroller address/data 1
2~16MA, SR
Microcontroller address/data 0
2~16MA, SR
Microcontroller address 0 / IO
2~16MA, SR
PU
Microcontroller address 1 / IO
2~16MA, SR
PU
Microcontroller address 2 / IO
2~16MA, SR
PU
Microcontroller address 3 / IO
2~16MA, SR
PU
Microcontroller address 4 / IO
2~16MA, SR
PU
Microcontroller address 5 / IO
2~16MA, SR
PU
Microcontroller address 6 / IO
2~16MA, SR
PU
MT1379
22
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Pin Number Symbol Type Description
48 IOA7 Inout
49 A16 Output
50 A17 Output
51 IOA18 Inout
52 IOA19 Inout
53 IOA20 Inout
54 APLLVSS Ground Ground pin for audio clock circuitry
55 APLLVDD3 Power 3.3V Power pin for audio clock circuitry
56 ALE Inout
57 IOOE# Inout
58 IOWR# Inout
59 IOCS# Inout
60 DVSS Ground Ground pin for internal digital circuitry
61 UP1_2 Inout
62 UP1_3 Inout
63 UP1_4 Inout
64 UP1_5 Inout
65 UP1_6 Inout
66 DVDD3 Power 3.3V power pin for internal digital circuitry
Microcontroller address 7 / IO
2~16MA, SR
PU
Flash address 16
2~16MA, SR
Flash address 17
2~16MA, SR
Flash address 18 / IO
2~16MA, SR
SMT
Flash address 19 / IO
2~16MA, SR
SMT
Flash address 20 / IO
2~16MA, SR
SMT
2~16MA, SR
PU, SMT
2~16MA, SR
SMT
2~16MA, SR
SMT
2~16MA, SR
PU, SMT
4MA, SR
PU, SMT
4MA, SR
PU, SMT
4MA, SR
PU, SMT
4MA, SR
PU, SMT
4MA, SR
PU, SMT
OR Videoin Data PortB 0
Microcontroller address latch enable
Flash output enable, active low / IO
Flash write enable, active low / IO
Flash chip select, active low / IO
Microcontroller port 1-2
Microcontroller port 1-3
Microcontroller port 1-4
Microcontroller port 1-5
Microcontroller port 1-6
MT1379
23
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Pin Number Symbol Type Description
67 UP1_7 Inout
68 UP3_0 Inout
69 UP3_1 Inout
70 INT0# Inout
71 IR Input
72 DVDD2 Power 2.5V power pin for internal digital circuitry
73 UP3_4 Inout Microcontroller port 3 -4
74 UP3_5 Inout Microcontroller port 3 -5
75 UWR# Inout
76 URD# Inout
77 DVSS Ground Ground pin for internal digital circuitry
78 RD7 Inout DRAM data 7
79 RD6 Inout DRAM data 6
80 RD5 Inout DRAM data 5
81 RD4 Inout DRAM data 4
82 DVDD2 Power 2.5V power pin for internal digital circuitry
83 RD3 Inout DRAM data 3
84 RD2 Inout DRAM data 2
85 RD1 Inout DRAM data 1
86 RD0 Inout DRAM data 0
87 RWE# Output
88 CAS# Output
89 RAS# Output
90 RCS# Output
91 BA0 Output
92 DVSS Ground Ground pin for internal digital circuitry
93 RD15 Inout
Microcontroller port 1-7
4MA, SR
PU, SMT
Microcontroller port 3-0
4MA, SR
PU, SMT
Microcontroller port 3-1
4MA, SR
PU, SMT
Microcontroller interrupt 0, active low
2~16MA, SR
PU, SMT
IR control signal input
SMT
Microcontroller write s trobe, active low
2~16MA, SR
PU, SMT
Microcontroller read strobe, active low
2~16MA, SR
PU, SMT
DRAM Write enable, active low
2~16MA, SR
DRAM columnaddress strobe, active low
2~16MA, SR
DRAM row address strobe, active low
2~16MA, SR
DRAM chip select, active low
2~16MA, SR
DRAM bank address 0
2~16MA, SR
DRAM data 15
2~16MA, SR
PU/PD, SMT
MT1379
24
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1379
Pin Number Symbol Type Description
94 RD14 Inout
DRAM data 14
2~16MA, SR
PU/PD, SMT
95 RD13 Inout
DRAM data 13
2~16MA, SR
PU/PD, SMT
96 RD12 Inout
DRAM data 12
2~16MA, SR
PU/PD, SMT
97 DVDD3 Power 3.3V power pin for internal digital circuitry
98 RD11 Inout
DRAM data 11
2~16MA, SR
PU/PD, SMT
99 RD10 Inout
DRAM data 10
2~16MA, SR
PU/PD, SMT
100 RD9 Inout
DRAM data 9
2~16MA, SR
PU/PD, SMT
101 RD8 Inout
DRAM data 8
2~16MA, SR
PU/PD, SMT
102 DVSS Ground Ground pin for internal digital circuitry
103 CLK Output
DRAM clock
2~16MA, SR
104 CLE Output
DRAM clock enable
2~16MA, SR
105 RA11 Output
DRAM address bit 11 or audio serial data 3 (channel 7/8)
2~16MA, SR
106 RA9 Output
DRAM address 9
2~16MA, SR
107 RA8 Output
DRAM address 8
2~16MA, SR
108 DMVDD3 Power 3.3V Power pin for DRAM clock circuitry
109 DMVSS Ground Ground pin for DRAM clock circuitry
110 RA7 Output
DRAM address 7
2~16MA, SR
111 DVDD3 Power 3.3V power pin for internal digital circuitry
112 RA6 Output
DRAM address 6
2~16MA, SR
113 RA5 Output
DRAM address 5
2~16MA, SR
114 RA4 Output
DRAM address 4
2~16MA, SR
115 DVSS Ground Ground pin for internal digital circuitry
116 DQM1 Output
Mask for DRAM input/output byte 1
2~16MA, SR
25
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Pin Number Symbol Type Description
117 DQM0 Output
118 BA1 Output
119 RA10 Output
120 DVDD2 Power 2.5V power pin for internal digital circuitry
121 RA0 Output
122 RA1 Output
123 RA2 Output
124 RA3 Output
125 DVSS Ground Ground pin for internal digital circuitry
126 RD31 Inout
127 RD30 Inout
128 RD29 Inout
129 RD28 Inout
130 DVDD3 Power 3.3V power pin for internal digital circuitry
131 RD27 Inout
132 RD26 Inout
133 RD25 Inout
134 RD24 Inout
135 DVSS Ground Ground pin for internal digital circuitry
136 DQM3 Output
137 DQM2 Output
Mask for DRAM input/output byte 0
2~16MA, SR
DRAM bank address 0
2~16MA, SR
DRAM address10
2~16MA, SR
DRAM address 0
2~16MA, SR
DRAM address 1
2~16MA, SR
DRAM address 2
2~16MA, SR
DRAM address 3
2~16MA, SR
DRAM data 31
2~16MA, SR
PU/PD, SMT
DRAM data 30
2~16MA, SR
PU/PD, SMT
DRAM data 29
2~16MA, SR
PU/PD, SMT
DRAM data 28
2~16MA, SR
PU/PD, SMT
DRAM data 27
2~16MA, SR
PU/PD, SMT
DRAM data 26
2~16MA, SR
PU/PD, SMT
DRAM data 25
2~16MA, SR
PU/PD, SMT
DRAM data 24
2~16MA, SR
PU/PD, SMT
Mask for DRAM input/output byte 3
2~16MA, SR
Mask for DRAM input/output byte 2
2~16MA, SR
MT1379
26
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Pin Number Symbol Type Description
138 RD23 Inout
139 RD22 Inout
140 DVDD2 Power 2.5V power pin for internal digital circuitry
141 RD21 Inout
142 RD20 Inout
143 RD19 Inout
144 RD18 Inout
145 DVSS Ground Ground pin for internal digital circuitry
146 RD17 Inout
147 RD16 Inout
148 ABCK Output
149 ALRCK Inout
150 DVDD3 Power 3.3V power pin for internal digital circuitry
151 ACLK Inout
152 MC_DATA Input Microphone serial input
153 SPDIF Output
154 ASDATA0 Inout
155 ASDATA1 Inout
156 ASDATA2 Inout
DRAM data 23 /
2~16MA, SR
PU/PD, SMT
2~16MA, SR
PU/PD, SMT
2~16MA, SR
PU/PD, SMT
2~16MA, SR
PU/PD, SMT
2~16MA, SR
PU/PD, SMT
2~16MA, SR
PU/PD, SMT
2~16MA, SR
PU/PD, SMT
2~16MA, SR
PU/PD, SMT
4MA
4MA,
PD, SMT
4MA
2~16MA,
SR : ON/OFF
4MA
PD SMT
4MA
PD SMT
4MA
PD SMT
Videoin Data PortA 7
DRAM data 22 /
Videoin Data PortA 6
DRAM data 21 /
Videoin Data PortA 5
DRAM data 20 /
Videoin Data PortA 4
DRAM data 19 /
Videoin Data PortA 3
DRAM data 18 /
Videoin Data PortA 2
DRAM data 17 /
Videoin Data PortA 1
DRAM data 16 /
Videoin Data PortA 0
Audio bit clock
(1) Audio left/right channel clock
(2) Trap value in power-on reset :
(1) Audio serial data 0 (left/right channel)
(2) Trap value in power-on reset :
1 : manufactory test mode 0 : normal operation
(1) Audio serial data 1 (surround left/surround right channel)
(2) Trap value in power-on reset :
1 : manufactory test mode 0 : normal operation
(1) Audio serial data 2 (center/left channel)
(2) Trap value in power-on reset :
1 : manufactory test mode 0 : normal operation
MT1379
Analog Y output
27
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Pin Number Symbol Type Description
157 ASDATA3 Inout
158 ASDATA4 Inout
159 DACVDDC Power 3.3V power pin for VIDEO DAC circuitry
160 VREF Analog input Bandgap reference voltage
161 FS Analog output Full scale adjustment
162 YUV0/CIN Output
163 DACVSSC Ground Ground pin for VIDEO DAC circuitry
164 YUV1/C Output
165 DACVDDB Power 3.3V power pin for VIDEO DAC circuitry
166 YUV2/Y Output
167 DACVSSB Ground Ground pin for VIDEO DAC circuitry
168 YUV3/CVBS Output
169 DACVDDA Power 3.3V power pin for VIDEO DAC circuitry
170 YUV4/G Output
171 DACVSSA Ground Ground pin for VIDEO DAC circuitry
172 YUV5/B Output
173 YUV6/R Output
174 ICE
175 BLANK# Inout
176 VSYN Inout
177 YUV7 Inout
178 DVSS Ground Ground pin for internal digital circuitry
179 HSYN Inout
(1) Audio serial data 3 (surround left/surround right channel)
4MA
PD SMT
4MA
PD SMT
4MA, SR
4MA, SR
4MA, SR
4MA, SR
4MA, SR
4MA, SR
4MA, SR
Input
PD, SMT
4MA, SR
SMT
4MA, SR
SMT
4MA, SR
SMT
4MA, SR
SMT
(2) Trap value in power-on reset :
1 : manufactory test mode 0 : normal operation
OR Videoin Data PortB 1
(1) Audio serial data 4 (center/left channel)
(2) Trap value in power-on reset :
1 : manufactory test mode 0 : normal operation
OR Videoin Data PortB 2
Video data output bit 0 /
Compensation capacitor
Video data output bit 1 /
Analog chroma output
Video data output bit 2 /
Video data output bit 3 /
Analog composite output
Video data output bit 4 /
Green or Y
Video data output bit 5 /
Blue or CB
Video data output bit 6 /
Red or CR
Microcontroller ICE mode enable
Video blank area, active low /
Videoin Field_601
Vertical sync /
Videoin Vsync_601
Video data output bit 7 /
Videoin Data PortB 3
Horizontal sync /
Videoin Hsync_601
Videoin Data PortB 4
MT1379
RF serial data output
28
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
Pin Number Symbol Type Description
181 SPDATA Input Audio data of SPDIF input /
182 DVDD2 Power 2.5V power pin for internal digital circuitry
183 SPLRCK Input Audio left/right channel clock of SPDIF input /
184 SPBCK Input Audio bit clock of SPDIF input /
185 DVDD3 Power 3.3V power pin for internal digital circuitry
186 XTALO Output Crystal output
187 XTALI Input Crystal input
188 PRST Input
189 DVSS Ground Ground pin for internal digital circuitry
190 VFO13 Output The 1st, 3rd header VFO pulse output
191 IDGATE Output Header detect signal output
192 DVDD3 Power 3.3V power pin for internal digital circuitry
193 UDGATE Output DVD_RAM recording data gate signal output
194 WOBSI Input Wobble signal input
195 SDATA Output
196 SDEN Output RF serial data latch enable
197 SLCK Output RF serial clock output
198 BDO Input Flag of defect data input status
199 ADCVSS Ground Ground pin for ADC circuitry
200 ADIN Analog Input General A/D input
201 RFSUBI Analog Input RF subtraction signal input terminal
202 TEZISLV Analog Input Tracking error zero crossing low pass input
203 TEI Analog Input Tracking error input
204 CSO Analog Input Central servo input
205 FEI Analog Input Focus error input
206 RFLEVEL Analog Input Sub beam add input or RFRP low pass input
207 RFRP_DC A Input RF ripple detect input
208 RFRP_AC Analog Input RF ripple detect input (through AC coupling)
209 HRFZC Analog Input High frequency RF ripple zero crossing
210 PWMVREF A Input A reference voltage input for PWM circuitry. A typical value of 4.0 v
211 PWM2VREF A Input A reference voltage input for PWM circuitry. A typical value of 2.0 v
212 ADCVDD3 Power 3.3V power pin for ADC circuitry
213 RFDTSLVP Analog Output Positive RF data slicer level output
214 RFDTSLVN Analog Output Negative RF data slicer level output
215 RFIN Analog Input Negative input of RF differential signal
216 RFIP Analog Input Positive input of RF differential signal
Videoin Data PortB 5
Videoin Data PortB 6
Videoin Data PortB 7
Power on reset input, active high
PD, SMT
MT1379
29
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1379
F
UNCTIONAL BLOCK
IR/
VFD
Servo
IO
Servo
DSP
Playback
Controller
System
Controller
DVD module
Analog
Front end
DRAM
Interface
Spindle
Controller
DPU
Processor
Audio
Channel
Decode
Debug
Port
Audio
Output
CSS/
CPPM
System
Parser
Microphone
Input
Video
Decoder
TV encoder
Video
Output
Servo Controller
The servo control is accomplished through the servo DSP (Servo Digital Signal Processor) and its accessory I/O circuits. This servo
DSP is capable of performing complex operations an d also provides a friendly interface for the system controller. By issuing type
1 and type 2 commands from the system controller, the servo DSP can accomplish various complicated servo control functions,
such as tracking, seeking and MT1336/MT1376 chip register programming. As for the servo I/O circuits, it provides interface
between the input servo signals and the Servo DSP. It has built-in ADCs to digitize the servo control signal and DACs to provide
signals for the actuator and sledge motor. It also has a serial interface to communicate with the MT1336/MT1376 chip.
Analog Front End
The analog front end contains a data slicer circuit and a data PLL circuit. The RF analog signal from MT1336/MT1376 is
quantized by the data slicer to form the EFM/EFM+ bit stream, from which the channel bit clock is extracted by the data PLL.The
EFM/EFM+bit stream and bit clock are then output to DPU for channel bit processing.
DPU
Data path unit (DPU) provides protection on data with lost synchronization patterns and demodulates EFM/EFM+ bit stream into
the channel raw data that will be corrected by the decoder. The synchronization protection makes data after the synchronization
pattern to be extracted even if the synchronization pattern is not found.
Spindle Controller
The sp indle controller is used to control disc spindle motor. It includes a varipitch CLV clock generator, a CLV/CAV controller,
and a PWM generator. The varipitch CLV clock enerator generates a reference colck for the speed of operation. The CLV/CAV
DRAMFlash
Audio DAC
SPDIF
MIC
31
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1379
controller changes the mode and speed of operation according to servo register setting. The PWM generator generates
pulse-width-modulated signal to drive disc spindle motor driver.
CSS/CPPM
The CSS/CPPM module provides functions necessary for decoding discs conforming to CSS/CPPM specification.
System Parser
The system parser is used to help the system controller to decode DVD/SVCD/VCD bitstream just after the channel decoder
performing error correction. Acting as a DMA master, it moves bitstream data from RSPC buffer to video, audio, or sub-picture
buffer according to system controller request. It also decrypts the scramble data of the CSS/CPPM sectors. Another function of
system parser is providing system controller/DSP a DRAM memory copy controller to enhance system controller/DSP performance.
Video Decoder
The primary function of MT1379 is to support MPEG1 and MPEG2 video decoding. The video decode engine comprises of
variable length decoder (VLD), inverse transformer (IT), motion compensator (MC), and block reconstructor (BR). The video
decode engine decodes the variable length encoded symbols in MPEG bitstream and performs inverse scan, inverse
quantization, mismatch control and inverse discrete cosine transform onto the variable length decoded data. The motion
compensator fetches prediction data from reference picture buffer according to motion vectors and motion prediciton mode for P
and B pictures. Finally, the block reconstructor combines both the results of inverse transformer and motion compensator to derive
the reconstructed image macroblock and write back to picture buffer.
The video decode engine can also support JPEG and BMP file decoding by common image compression hardware kernels.
Video Output
The Video Output unit contains Video Processor, SPU, OSD, Cursor, TV encoder units, it performs
§
§
§
§
§
§
Video Processor
SPU
Reading decoded video from DRAM buffer
Scaling the image
Gamma/Brightness/Hue/Saturation adjustment and edge enhancement
Reading and decoding SPU and OSD data from DRAM buffer
Generating hardware cursor image
Merging the video data, SPU, OSD and cursor
The Video Processor unit controls the transfer of video data stored in the DRAM to an internal or external TV encoder. It uses
FIFOs to buffer outgoing luminance and chrominance data, and performs YUV420 to YUV422 conversion and arbitrary
vertical/horizontal decimation/interpolation, from 1/4x to 256x. With this arbitrary ratio scaling capability, the Video Processor
can perform arbitrary image conversion, such as PAL to NTSC, NTSC to PAL, MPEG1 to MPEG2, Letterbox, Pan-Scan
conversion or zoom in, zoom out. It is also capible of interlace to progressive conversion.
The Video Processor unit performs the following functions:
§
Requests and receives the decoded picture data from the picture buffer in external DRAM for display
§
Resample vertical data to create 4:2:2 sample format
§
Optionally performs vertical/horizontal resampling of both luminance and chrominance data
§
Performs optional Gamma correction, luminance/chrominance adjustment, and edge enhancement
The V ideo Processor unit contains two 2-tap vertical filters for luminance and chrominance . These filters are used to
interpolate and reposition luminance and chrominance line to improve picture quality. These filters are capble of generating
up to eight, unique subline value between two consecutive scan lines. The generation of lines depends on the ratio between
the height of the source image and the target image. In applications where DRAM bandwidth are critical the filters can be
configured as simple line-repeating to reduce the DRAM bandwidth required.
The Video Processor unit integrates two separate horizontal postprocessing filter, a simple 2-tap linear horizontal filter and
an 8-tap programmable filter. These filters are provided for scaling images horizontally along the scan line. These two filters
is capable of generating up to eight, unique subpixel values between two consecutive pixels on a scan line. The generation
of pixels depends on the ratio between the width of the source image and the target image.
32
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
This is a hardware sub-picture decoder. It decodes the compressed SPU image bitstream and CHG_COLCON commands
according to SPU header information previously decoded by system controller. The SPU module also allows two SPU
objects to be displayed at the same time. SPU image is blended with main video stream.
OSD
The OSD module can operate with 2/4/16/256-color bitmap format (1/2/4/8 bits), and 16/256 color RLC format, all have 16
levels of transparency. In addition, it accepts an special WARP mode, which inserts one programmable RLC code in the
bitmap to reduce the image size stored in DRAM. It also features automatic shadow/outline generation in 2-color mode, 2
Hilight areas, 1 ChangeColor area and 1 OSDVoid area. One OSD area can occupy the full or a partial screen, or multiple
OSDs can occur in a screen at the same time, only if they don't occupy the same horizontal line. The output image is
blended with the video-SPU mixed stream.
Cursor
A hardware cursor generator is integrated in Video Output Unit. The cursor image is a 32x32 4-color bitmap image, each
colors are programmable. Cursor can be enlarged by 2 in both vertical and horizontal directions. Cursor image is multiplexed
with video-SPU-OSD mixed stream.
Audio Interface
Audio interface consists of Audio Output Interface and Microphone Input Interface.
Audio Output Interface
The MT1379 can support up to 8 channel audio outputs. The output formats can be 16, 24, or 32-bit frames. Left alignment,
right alignment, or I2S formats are all supported.
With built-in PLL, MT1379 can provide the audio clock (ACLK) for external audio DAC at 384Fs, where Fs is usually 32KHz,
44.1KHz, 48KHz, 96KHz, or 192KHz. ACLK can also be programmed to be from outside MT1379. When ACLK is input to
MT1379, the frequency could be 128*n Fs, where n is from 1 to 7.
Audio raw (encoded) data or cooked (decoded) data can be output on a single line using S/PDIF interface. The output slew
rate and driving force of this pad are programmable.
Microphone Input Interface
The MT1379 provides a microphone input interface. Two independent microphones’ data could be input to the MT1379.
There are two independent digital volume control for these two input channels. The input data formats can also be left
alignment, right alignment, or I2S formats.
MT1379
System Controller
MT1379 uses an embedded Turbo-8032 as System Controller and provide ICE interface to increase the feasibility of F/W
development. Also, MT1379 includes an build-in internal 373 to latch lower byte address from 8032 Port 0 and provide a
glue-logic free solution. MT1379 supports up to 1M X 16 bits Flash ROM to store 8032 code, H/W related data, User data, etc.
F/W upgrade can be achieved either by debug interface or by disk.
33
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
MT1379
E
LECTRICAL CHARACTERISTICS
Absolute Maximum Rating
Symbol Parameters Value Unit
VDD3 3.3V Supply voltage -0.3 to 3.6 V
VDD2 2.5V Supply voltage -0.3 to 3.0 V
VDDA Analog Supply voltage -0.3 to 3.6 V
VINInput Voltage -0.3 to 5.5 V
V
Output Voltage -0.3 to VDD3+0.3 V
OUT
Ta Ambient Temperature 0 to 70 °C
DC Charateristics
Symbol Parameters Min Typ Max Unit
VIH Input voltage high 2.4 - 3.6 V
VILInput voltage low - - 0.8 V
VOH Output voltage high 3.0 - VDD3 V
VOL Output voltage low - - 0.5 V
IIH High level input current 10 uA
IIL Low level input current -10 uA
PD Power dissapation 1.0 W
P
Power down mode 0.1 W
Down
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
34
8.3 Am29LV160D
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3. 0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■ Manufactured on 0.23 µm process technology
— Fully compatible with 0.32 µm Am29LV160B device
■ High performance
— Access times as fast as 70 ns
■ Ultra low power consumption (typical values at
5MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect featur e allows code
changes in previously locked sectors
■ Unlock Bypass Program Command
— Reduces overall pr ogramming time when issuing
multiple program command sequences
■ Top or bottom boot block configurations
available
■ Minimum 1,000,000 write cycle guarantee
per sector
■ 20-year data retention at 125°C
— Reliable operation for the life of the system
■ Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■ Ready/Busy# pin (RY/ BY#)
— Provides a hardware method of detecting
program or erase cycle completi on (not av ailable
on 44-pin SO)
■ Erase Suspend/Erase Resume
— Suspends an erase operation t o read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the devic e to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modificat ions due to changes in technical specif ic ations.
Publication# 22358Rev: B Amendment/+3
Issue Date: November 10, 2000
PRODUCT SELECTOR GUIDE
35
Family Part NumberAm29LV160D
Speed OptionVoltage Range: V
Max access time, ns (t
Max CE# access time, ns (t
Max OE# access time, ns (t
)7090120
ACC
)7090120
CE
)303550
OE
= 2.7–3.6 V-70-90-120
CC
Note: See “AC Characteristics” for full specifications.
Special handling is required for Flash Memory products
in FBGA packages.
BYTE#A16A15A14A12A13
DQ15/A-1V
SS
DQ13DQ6DQ14DQ7A11A10A8A9
V
CC
DQ4DQ12DQ5A19NCRESET#WE#
DQ11DQ3DQ10DQ2NCA18NCRY/BY#
DQ9DQ1DQ8DQ0A5A6A17A7
CE#A0A1A2A4A3
OE#V
SS
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
A
PIN CONFIGURATION
38
A0–A19= 20 addresses
DQ0–DQ14 =15 data inputs/outputs
DQ15/A-1= DQ15 (data input/output, word mode),
The Hyundai HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•Single 3.3±0.3V power supply
•All device pins are compatible with LVTTL interface
•JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•All inputs and outputs referenced to positive edge of
system clock