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WLNN-EK-DP551
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B&B Electronics WLNN-EK-DP551 Product Specification

Product Specification
802.11a/b/g/n Advanced Enterprise Device Server and Access Point
Revision: 1.2
June 2013
B&B Confidential
Copyright © 2013 B&B ® Inc.
ALL RIGHTS RESERVED. No part of this publication may be copied in any form, by photocopy, microfilm, retrieval
system, or by any other means now known or hereafter invented without the prior written permission of B&B ® Inc. This
document may not be used as the basis for manufacture or sale of any items without the prior written consent of B&B Inc.
B&B Inc. is a registered trademark of B&B Inc.
Airborne™ is a trademark of B&B Inc.
All other trademarks used in this document are the property of their respective owners.
Disclaimer
The information in the document is believed to be correct at the time of print. The reader remains responsible for the
system design and for ensuring that the overall system satisfies its design objectives taking due account of the information
B&B ® Inc. has made commercially reasonable efforts to ensure that the information contained in this document is
accurate and reliable. However, the information is subject to change without notice. No responsibility is assumed by B&B
for the use of the information or for infringements of patents or other rights of third parties. This document is the property
presented herein, the specifications of other associated equipment, and the test environment.
of B&B ® Inc. and does not imply license under patents, copyrights, or trade secrets.
B&B, Inc. Headquarters
B&B ® Inc.
707 Dayton Road
Ottawa, IL, 61350, USA
Telephone: 815-433-5100
Toll Free (USA): 888-948-2248
Fax: 815-433-5109
Technical Support: 800-346-3119 / support@bb-elec.com
Web Site: www.bb-elec.com
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Contents
1.0 Conventions ..................................................................................................................................... 5
1.1 Terminology ................................................................................................................................ 5
1.2 Notes ................................ ................................ ................................................................ ............ 5
1.3 Caution ......................................................................................................................................... 5
1.4 File Format .................................................................................................................................. 5
2.0 Product Description ........................................................................................................................ 6
3.0 Block Diagram ................................................................................................................................. 7
4.0 Model Numbers ............................................................................................................................... 8
5.0 Pin out and Connectors ................................................................................................................. 9
5.1 Digital UART Ports ....................................................................................................................11
5.2 Ethernet PHY Port .....................................................................................................................11
5.3 Serial Peripheral Interface (SPI) .............................................................................................11
5.4 Debug/Console Port ..................................................................................................................12
5.5 General Purpose Input/Output (GPIO) ...................................................................................12
5.6 Connector Definition .................................................................................................................13
6.0 Electrical & RF Specification ........................................................................................................14
6.1 AC Electrical Characteristics – Transmitter ...........................................................................18
6.2 Performance/Range ..................................................................................................................18
7.0 SPI Interface ...................................................................................................................................19
7.1 Pin-out .........................................................................................................................................19
7.2 SPI AC Characteristics .............................................................................................................20
7.3 SPI Protocol ...............................................................................................................................21
7.4 SPI Modes ..................................................................................................................................22
7.5 SPI Commands..........................................................................................................................22
8.0 Antenna ................................................................ ................................................................ ...........25
8.1 Antenna Selection .....................................................................................................................25
8.2 Host Board Mounted Antenna .................................................................................................25
8.3 Host Chassis Mounted Antenna..............................................................................................26
8.4 Embedded Antenna ..................................................................................................................26
8.5 Antenna Location ......................................................................................................................27
8.6 Performance ...............................................................................................................................27
9.0 RESET Function ............................................................................................................................29
10.0 Mechanical Outline ........................................................................................................................30
11.0 Recommended Footprint ..............................................................................................................31
11.1 Mounting Hole Specification ....................................................................................................31
11.2 Alternate Mounting Hardware ..................................................................................................31
12.0 Regulatory Certification and Agency Approvals ........................................................................32
12.1 FCC Statement ..........................................................................................................................32
12.2 FCC RF Exposure Statement ..................................................................................................33
12.3 Information for Canadian Users (IC Notice) ..........................................................................33
12.4 FCC/IC Modular Approval ........................................................................................................34
12.5 End Product Labeling ...............................................................................................................35
12.6 Regulatory Test Mode Support ...............................................................................................36
13.0 Physical & Environmental Approvals ..........................................................................................37
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Figures
Figure 1 – APMN-Q551/WLNN-SE/SP/AN/ER-DP550 Block Diagram ............................................... 7
Figure 2 - SPI Read/Write Timing ............................................................................................................20
Figure 3 - SPI Clock and Select Timing ..................................................................................................20
Figure 4 - Power on RESET Timing .........................................................................................................29
Figure 5 - RESET Timing ..........................................................................................................................29
Figure 6 – DP550 Mechanical Outline .....................................................................................................30
Figure 7 - Recommended PCB Footprint ................................................................................................31
Figure 8 - Full FCC/IC Label .....................................................................................................................36
Figure 9 - Minimum FCC/IC Label ...........................................................................................................36
Tables
Table 1 - Model Numbers ........................................................................................................................... 8
Table 2 – Module Pin Definition ................................................................................................................. 9
Table 3 - UART Pin Definition ...................................................................................................................11
Table 4- Absolute Maximum Values1 .......................................................................................................14
Table 5 – Operating Conditions & DC Specification ..............................................................................14
Table 6 - RF Characteristics – 802.11a/b/g/n .........................................................................................16
Table 7 - Supported Data Rates by Band ...............................................................................................17
Table 8 - Operating Channels ...................................................................................................................17
Table 9 - Radio Typical Performance Range .........................................................................................18
Table 10 - SPI Pinout Details ....................................................................................................................19
Table 11 - SPI Signal Descriptions ..........................................................................................................19
Table 12 - SPI AC Timings ........................................................................................................................20
Table 13 - TX Message Header ...............................................................................................................21
Table 14 - RX Message Header ...............................................................................................................21
Table 15 - SPI Modes ................................................................................................................................22
Table 16 - SPI Command Description .....................................................................................................22
Table 17 - Embedded Antenna Options ..................................................................................................26
Table 18 - RESET Timing ..........................................................................................................................29
Table 19 - Regulatory Approvals ..............................................................................................................32
Table 20 - Modular Grant Numbers .........................................................................................................35
Table 21 - Mechanical Approvals .............................................................................................................37
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The area next to the indicator will identify the specific information and make any references necessary.
The area next to the indicator will identify the specific information and make any references necessary.
1.0 Conventions
The following section outlines the conventions used within the document. Where convention is deviated from the deviation takes precedence and should be followed. If you have any question related to the conventions used or clarification of indicated deviation please contact B&B Sales or Wireless Support.
1.1 Terminology
Airborne Enterprise Device Server and AirborneDirect Enterprise Device Server are used in the opening section to describe the devices detailed in this
document. After this section the term module will be used to describe the devices.
1.2 Notes
A note contains information that requires special attention. The following convention will be used. The area next to the indicator will identify the specific information and make any references necessary.
1.3 Caution
A caution contains information that -- if not followed -- may cause damage to the product or injury to the user. The shaded area next to the indicator will identify the specific information and make any references necessary.
1.4 File Format
These documents are provided as Portable Document Format (PDF) files. To read them, you need Adobe Acrobat Reader 4.0.5 or higher. For your convenience, Adobe Acrobat Reader is provided on the Radio Evaluation Kit CD. Should you not have the CD, go to the Adobe Web site (www.adobe.com) and download the latest version of the free Adobe Acrobat Reader.
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2.0 Product Description
The WLNN-XX-DP550/APMN-Q550 family is the latest generation of 802.11 wireless device servers and adapters from B&B. The radio features the following:
o 802.11a/b/g/n Wi-Fi Radio with 32bit ARM9 CPU (128/256Mb SDRAM, 64Mb
Flash)
o Atheros AR6003 802.11a/b/g/n radio chipset. o Supports Access Point, Infrastructure and AdHoc Client networks (Software
selectable)
o Access Point device includes:
Up to eight (8) simultaneous clients  WEP, WPA-PSK and WPA2-PSK security  Integrated DHCP server  Tx Power Control  MAC address filtering
o Infrastructure device includes:
Supports WEP, WPA, WPA2, 802.11i and 802.1x Supplicant, with
Certificates.
o The wireless device server includes integrated:
802.11a/b/g/n radio driver  TCP/IP stack, UDP, telnet, FTP server  Data bridging and buffering  Command Line Interface  Web interface  WPA Supplicant  802.11 Radio Driver
o Operating Temperature (-40°C to 85°C) o Storage temp (-40°C to 85°C) o 36 pin high density SMT connector (Hirose DF12-36) o Dual (2) Hirose U.FL RF connector for RF antenna o Multiple host interfaces supported:
Dual UART (921.6K BAUD)  Serial (RS232/422/485)  SPI  10/100 Ethernet PHY (Bridge/Router modes supported)
o Advanced low power modes o Rugged mounting options. o No host driver required
o Small form factor module (Dimensions: 40.6mm x 29.6mm x 7.5mm) o Worldwide Regulatory Support
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APMN-Q551 SDRAM memory size is 32MB.
3.0 Block Diagram
The following outlines the block diagram of the radio:
Figure 1 – APMN-Q551/WLNN-SE/SP/AN/ER-DP550 Block Diagram
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Model Number
Description
Wi-Fi
Interface
Security
RoHS
802.11 a/b/g/n
Client
802.11 a/b/g/n
Access Point
UART
RS232
RS485
SPI Ethernet
GPIO
WEP
WPA WPA2
802.11i
WLNN-AN-DP551
802.11a/b/g/n, UART Device Server
2
    
WLNN-ER-DP551
802.11a/b/g/n, 10/100 Ethernet Router Device Adapter
2
WLNN-SE-DP551
802.11a/b/g/n, UART Device Server with RS232/422/485 driver control
2
    
WLNN-SP-DP551
802.11a/b/g/n, SPI Device Server
    
APMN-Q551
802.11a/b/g/n Access Point, Ethernet Bridge/Router, Dual UART Device Server
 2       
 
Evaluation Kits
WLNN-EK-DP551
802.11a/b/g/n Enterprise Class Access Point and Serial Device Server Module Evaluation Kit
4.0 Model Numbers
The following table identifies the model numbers associated with the device server family. Please contact B&B sales for details, quotes and availability.
Table 1 - Model Numbers
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Pin
Name
Device
Type
Description
1
GND
All
Digital Ground
2
TDI
All
JTAG: Test data in
3
VDD
All
3.3VDC 4 VDD
All
3.3VDC 5 RTCK
All
JTAG: Return Test Clock
6
DTXD
All
D
OUT
Debug
7
/RESET
All
Module RESET 8 DRXD
All
DIN Debug
9
RXD2
UART
DIN UART2
RXD2
Serial
DIN UART2
RXD2
SPI
DIN UART2
RXD2
Ethernet
DIN UART2
G6
All
GPIO
10
TDO
All
JTAG: Test data out
11
/FRESET
All
Factory RESET
12
CTS1
UART
Clear-to-Send UART1
CTS
Serial
Clear-to-Send
/SPI_SEL
SPI
SPI Select
CTS1
Ethernet
Clear-to-Send UART1
F5
All
GPIO
13
NC
UART
No Connect
NC
Serial
No Connect
NC
SPI
No Connect
RX+
Ethernet
Ethernet RX+
14
NC
UART
No Connect
NC
Serial
No Connect
NC
SPI
No Connect
RX-
Ethernet
Ethernet RX-
15
GND
All
Digital Ground
16
GND
All
Digital Ground
17
RTS2
UART
Ready-to-Send UART2
/TXEN
Serial
Line Driver Tx enable
RTS2
SPI
Ready-to-Send UART2
RTS2
Ethernet
Ready-to-Send UART2
G2
All
GPIO
18
RTS1
UART
Ready-to-Send UART1
RTS
Serial
Ready-to-Send
SPI_CLK
SPI
SPI Clock Input
RTS1
Ethernet
Ready-to-Send UART1
F4
All
GPIO
19
CTS2
UART
Clear-to-Send UART2
5.0 Pin out and Connectors
Pin definition is dependent upon the device type selected. The specific pin function is defined in Table 2 for each device type. Where multiple options are available for a single device type, these options are software selectable by the device firmware.
Table 2 – Module Pin Definition
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Pin
Name
Device
Type
Description
RXEN
Serial
Line driver Rx enable
CTS2
SPI
Clear-to-Send UART2
CTS2
Ethernet
Clear-to-Send UART2
G1
All
GPIO
20
TCK
All
JTAG: Test clock
21
TXD2
UART
D
OUT
UART2
TXD2
Serial
D
OUT
UART2
TXD2
SPI
D
OUT
UART2
TXD2
Ethernet
D
OUT
UART2
G7
All
GPIO
22
G0
UART
GPIO
SER_MODE
Serial
Serial interface type selection (RS232/422/485)
SPI_INT
SPI
SPI Interrupt
G0
Ethernet
GPIO
23
LED_CON
All
Valid TCP/IP Connection Indicator
F6
GPIO
24
RXD1
UART
DIN UART1
RXD1
Serial
DIN UART1
MOSI
SPI
DIN SPI
RXD1
Ethernet
DIN UART1
F7
All
GPIO
25
LED_POST
All
POST Status Indicator
F0
GPIO
26
LED_WLN_CFG
All
Module TCP/IP Configuration Indicator
F3
GPIO
27
LED_RF_LINK
All
Module RF Link Status Indicator
F2
GPIO
28
TXD1
UART
D
OUT
UART1
TXD1
Serial
D
OUT
UART1
MISO
SPI
D
OUT
SPI
TXD1
Ethernet
D
OUT
UART1
F1
All
GPIO
29
NC
UART
No Connect
NC
Serial
No Connect
NC
SPI
No Connect
TX-
Ethernet
Ethernet TX-
30
NC
UART
No Connect
NC
Serial
No Connect
NC
SPI
No Connect
TX+
Ethernet
Ethernet TX+
31
NTRST
All
JTAG: Test RESET signal
32
TMS
All
JTAG: Test mode select
33
VDD
All
3.3VDC
34
VDD
All
3.3VDC
35
LED_RF_ACT
All
Radio Status Indicator, driven by the radio.
36
GND
All
Digital Ground
10
Device Type
UART
Serial
All
Pin Definition
UART1
Pin
UART2
Pin
UART1
Pin
UART2
Pin
Debug
Data out (D
OUT
)
28
21
28
21
6
Data In (DIN)
24 9 24 9 8
Clear-to-Send (CTS)
12
19
12
Ready-to-Send (RTS)
18
17
18
Transmit Enable (/TXEN)
17
Receive Enable (/RXEN)
19
Serial Mode (SER_MOD)
22
5.1 Digital UART Ports
The device supports two digital UART ports. Use of these ports is determined by the device type choice made in firmware. The details of the ports can be seen in Table 3.
The availability of UART2 is selected in firmware.
Table 3 - UART Pin Definition
The primary UART supports a 4-wire interface. The secondary port supports a 4­wire interface except when being used with the Serial Device type, in which case it is reduced to a 2-wire only.
The primary digital UART can be used as the primary connection for the Serial device type. This type supports a 7-wire interface to allow the definition of the serial interface type (RS232/3422/485) and the data transfer direction. Definitions of this interface can be seen in Table 3.
The UART1 and UART2 interfaces support the following possible configurations: BAUD: 300, 600, 1200, 2400, 4800, 9600, 14400, 19200, 28800, 38400, 57600,
115200, 230400, 460800, 921600 Flow Control: None, Hardware (CTS/RTS), Software (XON/XOFF) Default settings: 9600, 8, N, 1, No Flow Control.
5.2 Ethernet PHY Port
A 10/100 Ethernet PHY interface is supported on all device types (except SPI). It is enabled by default when the Ethernet device type is selected in firmware. This interface is a 10/100Mbps interface that supports auto negotiation and cross-over cabling. The interface also supports both half and full duplex for 10Mbps and 100Mbps.
The interface uses a Broadcom BCM5241A Ethernet PHY. Please refer to the manufacturer’s datasheet for interface details and appropriate design guidelines.
5.3 Serial Peripheral Interface (SPI)
Please refer to section 7.0 for details on this interface.
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CAUTION: Do not use the debug port without contacting B&B Technical Support first. Potential damage to the module may occur.
5.4 Debug/Console Port
A debug/console port is supported by a 2-wire serial interface defined in Table 3. This port is a bi-directional serial port intended for debug of the unit only. It does not support data transfer.
It is recommended that a connection to this port be supported via test points or a two pin header. The default settings for the debug port are 115200, 8, N 1, No Flow Control.
5.5 General Purpose Input/Output (GPIO)
A number of the interface pins support multiple functional definitions. Those alternately defined as GPIO pins can be selected as such via device firmware.
The GPIO pins are digital I/O capable of supporting up to a 16mA drive current at
3.3VDC.
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