AZ10E116
AZ100E116
ECL/PECL Quint Differential Line Receiver
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
ARIZONA MICROTEK, INC.
FEATURES
• 500ps Maximum Propagation Delay
• Dedicated V
CCO
Pin for Each Receiver
• Operating Range of 4.2V to 5.46V
• 75kΩ Internal Input Pulldown Resistors
• Direct Replacement for ON Semiconductor
MC10E116 & MC100E116
DESCRIPTION
The AZ10/100E116 is a quint differential line receiver with emitter-follower outputs. The E116 provides a VBB
output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input
applications, the V
BB
reference should be connected to one side of the Dn/D¯n differential input pair. The input
signal is then fed to the other Dn/D¯ n input. The V
BB
pin should be used only as a bias for the E116 as its sink/source
capability is limited. When used, the V
BB
pin should be bypassed to ground via a 0.01µF capacitor.
The receiver design features clamp circuitry to cause a defined state if both the inverting and non-inverting
inputs are left open; in this case the Q output goes LOW, while the Q¯ output goes HIGH. This feature makes the
device ideal for twisted pair applications.
If both inverting and non-inverting inputs are at an equal potential of > V
CC
-2.5V, the receiver does not go
to a defined state. This condition may produce output voltage levels between HIGH and LOW.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
PACKAGE AVAILABILITY
PACKAGE PART NO. MARKING
PLCC 28 AZ10E116FN AZM10E116
PLCC 28 T&R AZ10E116FNR2 AZM10E116
PLCC 28 AZ100E116FN AZM100E116
PLCC 28 T&R AZ100E116FNR2 AZM100E116