Axiom CML-5485 Hardware User Manual

DOC-0347-010 REV. C

Application Board for Freescale MCF5485 MCU

CML-5485

Hardware User Manual

Axiom Manufacturing • 2813 Industrial Lane • Garland, TX 75041

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Email: [e-mail] Web: http://www.axman.com

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CML-5485 USER MANUAL V1.0 06/22/05

CONTENTS

CAUTIONARY NOTES...........................................................................................................................................................3

TERMINOLOGY......................................................................................................................................................................3

FEATURES................................................................................................................................................................................4

GETTING STARTED...............................................................................................................................................................5

OFTWARE DEVELOPMENT.......................................................................................................................................................5

S

EFERENCE DOCUMENTATION .................................................................................................................................................5

R
CML-5485 S

TARTUP................................................................................................................................................................6

CML-5485 HARDWARE CONFIGURATION AND OPTIONS.........................................................................................6

POWER SUPPLY ...................................................................................................................................................................7

RESET

AND RESET_SW........................................................................................................................................................7

INDICATORS.........................................................................................................................................................................7

ABORT S

WITCH......................................................................................................................................................................7

SYSTEM CLOCK...................................................................................................................................................................8

MEMORY...............................................................................................................................................................................8

COMMUNICATION PERIPHERALS...................................................................................................................................8

CML-5485 PORTS AND CONNECTORS .............................................................................................................................8

PWR - P
COM1

OWER JACK.................................................................................................................................................................8

AND COM2 PORTS.......................................................................................................................................................9

COM PORT OPTIONS........................................................................................................................................................9

ORT .............................................................................................................................................................................10

CAN P

AND J5 ETHERNET PORTS...............................................................................................................................................10

J4

MCU_PORT.......................................................................................................................................................................... 11

BUS_PORT...........................................................................................................................................................................12

ADDRESS_PORT.................................................................................................................................................................13

BDM_PORT.......................................................................................................................................................................... 13

J1 PCI P

ORT...........................................................................................................................................................................14

TROUBLESHOOTING ............................................................................................................................................................16

DBUG MONITOR OPERATION..........................................................................................................................................17

DBUG COMMUNICATION:......................................................................................................................................................17

DBUG SYSTEM INITIALIZATION.............................................................................................................................................17

Interrupt Service Support ..................................................................................................................................................17

DBUG MEMORY MAP............................................................................................................................................................18

DBUG COMMANDS ................................................................................................................................................................19

dBUG Command Table .....................................................................................................................................................19

DBUG ETHERNET SUPPORT ...................................................................................................................................................20

Configuring dBUG Network Parameters ..........................................................................................................................21

APPENDIX 1: DBUG COMMAND SET..............................................................................................................................22

ASM - A
BC - B
BF - B
BM - B
BR - B
BS - B
DC - D
DI - D
DL - D
DLDBUG – D
DN - D
FL – F
GO – E

SSEMBLER...............................................................................................................................................................22

LOCK COMPARE...........................................................................................................................................................23

LOCK FILL....................................................................................................................................................................23

LOCK MOVE................................................................................................................................................................24

REAKPOINTS ................................................................................................................................................................24

LOCK SEARCH..............................................................................................................................................................25

ATA CONVERSION .......................................................................................................................................................26

ISASSEMBLE .................................................................................................................................................................26

OWNLOAD CONSOLE ...................................................................................................................................................27

OWNLOAD DBUG (UPDATE)............................................................................................................................28

OWNLOAD NETWORK..................................................................................................................................................28

LASH LOAD OR ERASE .................................................................................................................................................29

XECUTE USER CODE ....................................................................................................................................................30

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CML-5485 USER MANUAL V1.0 06/22/05

GT - E

XECUTE TO ADDRESS ..................................................................................................................................................30

NTERNAL REGISTER DISPLAY......................................................................................................................................31

IRD - I
IRM - I
HELP - H
LR - L
LW - L
MD - M
MM - M
MMAP - M
RD - R
RM - R
RESET - R
SET - S
SHOW - S
STEP - S
SYMBOL - S
TRACE - T
UP – U
VERSION - D
TRAP #15 F

NTERNAL REGISTER MODIFY......................................................................................................................................31

ELP .........................................................................................................................................................................32

OOP READ....................................................................................................................................................................32

OOP WRITE .................................................................................................................................................................32

EMORY DISPLAY........................................................................................................................................................33

EMORY MODIFY........................................................................................................................................................34

EMORY MAP DISPLAY..........................................................................................................................................34

EGISTER DISPLAY........................................................................................................................................................35

EGISTER MODIFY........................................................................................................................................................35

ESET THE BOARD AND DBUG...............................................................................................................................36

ET CONFIGURATIONS..................................................................................................................................................36

HOW CONFIGURATIONS .........................................................................................................................................37

TEP OVER.................................................................................................................................................................38

YMBOL NAME MANAGEMENT...........................................................................................................................38

RACE INTO ...........................................................................................................................................................39

PLOAD NETWORK........................................................................................................................................................39

ISPLAY DBUG VERSION..................................................................................................................................40

UNCTIONS...........................................................................................................................................................40

OUT_CHAR.......................................................................................................................................................................40

IN_CHAR...........................................................................................................................................................................41

CHAR_PRESENT..............................................................................................................................................................41

EXIT_TO_dBUG ...............................................................................................................................................................42

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CML-5485 USER MANUAL V1.0 06/22/05

Cautionary Notes

1) Electrostatic Discharge (ESD) prevention measures should be applied whenever handling
this product. ESD damage is not a warranty repair item.

2) Axiom Manufacturing reserves the right to make changes without further notice to any

products to improve reliability, function or design. Axiom Manufacturing does not assume any
liability arising out of the application or use of any product or circuit described herein; neither
does it convey any license under patent rights or the rights of others.

3) EMC Information on the CML-5485 board:

a) This product as shipped from the factory with associated power supplies and cables, has

NOT been tested for requirements of CE and the FCC a CLASS A products.

b) This product is designed and intended for use as a development platform for hardware

or software in an educational / professional laboratory or as a component in a larger
system.

c) In a domestic environment this product may cause radio interference in which case the

user may be required to take adequate prevention measures.

d) Attaching additional wiring to this product or modifying the products operation from the

factory default as shipped may effect its performance and also cause interference with
other apparatus in the immediate vicinity. If such interference is detected, suitable
mitigating measures should be taken.

Terminology

This development board applies option selection jumpers. Terminology for application of the
option jumpers is as follows:

Jumper on, in, or installed = jumper is a plastic shunt that fits across 2 pins and the
shunt is installed so that the 2 pins are connected with the shunt.

Jumper off, out, or idle = jumper or shunt is installed so that only 1 pin holds the shunt,
no 2 pins are connected, or jumper is removed. It is recommended that the jumpers be
placed idle by installing on 1 pin so they will not be lost.

This development board applies option selections indicated CT or R designations that require a
razor knife and soldering tool to install or remove. The default closed type connection places
an equivalent Jumper Installed type option. Applying the connection can be performed by
installing a resistor component or small wire for 0 ohms between the option pads. See the
Options sections for more details.

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CML-5485 USER MANUAL V1.0 06/22/05

FEATURES

CML-5485 is a low cost development kit for the Freescale MCF5485 ColdFire®
microcontroller. Application development is quick and easy with the included Axiom CML-5485
evaluation / application board, DB9 serial cable, Ethernet cable, BDM Cable, and GNU
Software Tool Package that includes C compiler and source level debug utilities. The BDM port
is compatible with standard ColdFire® BDM / JTAG development cables.

Features:

 MCF5485 CPU

o 200Mhz operation
o 32K Byte Ram (on chip)
o 32K Byte Data and Instruction Caches
o Double Precision Floating Point Unit (FPU)
o Memory management Unit (MMU)
o Security Encryption Controller (SEC)
o PCI V2.2 bus controller w/ arbitration unit
o 16 Channel DMA Controller
o 4 x 16 bit Timers w/ PWM
o DSPI and IIC Serial Ports
o 4 x UART Ports with IRDA / DMA capability
o USB V2.0 device transceiver, 6 endpoints
o Interrupt Controller
o BDM / JTAG Port
o 3.3V / 1.5V operation

 8M Byte Flash (16 bit, external)
 64M Bytes DDR RAM (32 bit, external)
 25Mhz Reference clock, 200Mhz core operation
 2 x 10/100TX Ethernet Ports w/ RJ45 Connectors,

LNK, DUP, SPD indicators for each port
Auto Negotiation and MDIX connections

 2 x COM Ports (UART0/1) w/ RS232 DB9-S Connectors
 USB type B connector w/ USB device I/O
 2 x CAN Ports w/ 1 M baud transceivers, 5 pin Term Block
 PCI V2.2 Bus connector, 3.3V bus, 50Mhz maximum.
 MCU Port, 50 pins w/ I/O port signals
 ADDRESS Port, 34 pin Demultiplexed Address BUS signals
 BUS Port, 50 pins, Multiplexed Address and Data signals w/ control signals
 BDM / JTAG Port, 26 Pins, development port.
 RESET switch and indicator
 ABORT (IRQ7) switch
 Regulated +5V, 3.3V, 2.5V and 1.5V power supplies w/ 3.3V indicator
 Supplied with DB9 Serial Cable, Cat 5E Ethernet cable, BDM Development Cable,
 Utility / Support CD, Manuals, and 12V Universal Wall Adapter power supply.

CML-5485

Specifications:

Board Size 4.5” x 5.0”, 8 layers
Power Input: +8 - +24VDC, 12VDC typical
Current Consumption: 200ma @ 12VDC input

CML-5485 is a low cost development system for the Freescale MCF5485 Coldfire®
microcontroller. Application development is quick and easy with the included DB9 serial cable,
Ethernet cable, Debug firmware monitor, and GNU c compiler with utilities. The BDM port is
compatible with standard Coldfire BDM / JTAG interface cables and hosting software, allowing
easy application debugging and development.

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CML-5485 USER MANUAL V1.0 06/22/05

GETTING STARTED

The CML-5485 single board computer is a fully assembled, fully functional application board
for the Freescale MCF5485 microcontroller. Provided with wall plug power supply, Ethernet
cable, and serial cable. Support software provided for this development board is for Windows
95/98/NT/2000/XP operating systems.

Development board users should also be familiar with the hardware and software operation of
the target MCF5485 device, refer to the provided Freescale User Guide for the device and the
Coldfire Reference Manual for details. The development board purpose is to assist the user in
quickly developing an application with a known working environment, to provide an evaluation
platform, or as a control module for an applied system. Users should be familiar with memory
mapping, memory types, and embedded software design for the quickest successful
application development.

Software Development

Application development maybe performed by applying the dBUG firmware monitor, or by
applying a compatible Coldfire BDM / JTAG cable with supporting host software. The monitor
provides an effective and low cost command line debug method.

Software development is best performed with a development tool connected to the BDM port.
This provides real-time access to all hardware, peripherals and memory on the board.
Development tool software also provides high-level (C/C++) source code debug environment.

The target development environment and procedure for best success is to place software to be
tested into RAM memory. Execute software to be tested under dBUG monitor or development
tool control, after software is tested and operational, port and program application into FLASH
memory to execute new application when power is applied.

Reference Documentation

Reference documents are provided on the support CD in Acrobat Reader® format.
CML5485UM.pdf – This user manual.

MCF5485UM.pdf – MCF5485 Device User Manual
CFPRM.pdf – Coldfire Programmers Reference Manual with instruction set
CML5485_SCH_C.pdf – CML5485 board schematics

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CML-5485 USER MANUAL V1.0 06/22/05

CML-5485 Startup

Follow these steps to connect and power on the board for the default dBUG monitor operation.

1) Carefully unpack the CML-5485 and observe ESD preventive measures while handling the

CML-5485 development board.

2) Load the ColdFire support CD into the PC and install the AxIDE terminal software from the

utilities directory, OR configure HyperTerminal for a direct connection to the PC COM port
to be applied for serial communication with the CML-5485 board. Set the baud rate to

19.2K baud, 8 data bits, 1 stop bit, and no parity. Software XON / XOFF flow control
should be enabled for flash memory support operations. Use the AxIDE ‘√’ tool bar button
to configure the COM port on the PC.

3) Connect the CML-5485 board COM1 serial port connector to the host PC COM port with

the provided 9 pin serial cable.

4) Apply power to the development board by installing the wall plug power supply between a

wall outlet and the PWR Jack on the board. The board voltage indicators should turn on at
this time. The RESET indicator will flash during power on or Reset switch press.

5) Observe the AxIDE or HyperTerminal window display for the dBUG monitor prompt.

Prompt should be similar to the following:

Hard Reset
DRAM Size: 64M

Copyright 1995-2003 Freescale, Inc. All Rights Reserved.
ColdFire MCF5485 Firmware v2e.1a.xx (Build XXX on XXX XX 20XXxx:xx:xx)

Enter 'help' for help.

dBUG>

6) The board is ready to use now. See the dBUG monitor section of the user manual for

additional monitor information. If BDM / JTAG development port interfaced tools are to be
applied, see the BDM PORT section of this manual for more details on installation.

CML-5485 Hardware Configuration and Options

The CML-5485 board provides a basic development or application platform for the MCF5485
microcontroller. Following are descriptions of the main components and options provided on
the board.

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CML-5485 USER MANUAL V1.0 06/22/05

POWER SUPPLY

Input power is applied by external connection to the PWR power jack. The input supply is
provided to the 3.3V primary supply regulator VR1 and the PCI +5V regulator VR5.

VR2 provides 2.5V peripheral and DDRAM supply from the 3.3V supply. VR3 provides the

1.5V core supply from the 3.3V supply. VR4 is the DDRAM termination supply. With +8 to

+20VDC applied at the PWR jack, the POWER Indicator should be ON. External fuse of 1A
and optional ON / OFF switch should be applied in system applications to the PWR jack input
supply.

RESET and RESET_SW

External reset is provided by the RESET switch, LV1 low voltage detector, or user applied
connection to the RESET* signal on the BUS_PORT. These external Reset sources activate a
150ms minimum pulse duration to the MCF5485 RSTI* input. If the main 3.3V supply is below
operating level, the LV1 voltage detector will cause the MCF5485 to stay in the RESET
condition.

The BDM port provides a direct connection to the MCF5485 RSTI* for Reset application by
development tools.

Application of RESET will cause the dBUG monitor or user application to initialize the
MCF5485. Previous DDRAM memory content and operating state of the MCF5485 will be lost.

INDICATORS

Indication is provided for power supply status, CPU Reset status, and Ethernet status. The
indications may be applied to determine proper operation of the development board.

Indicator Summary

INDICATOR COLOR OPERATION DEFAULT CONDITION

POWER Green +3.3V power present ON
RESET RED CPU is in RESET state OFF
LNK Green Ethernet channel has Link ON with Network connected
100 Green Ethernet channel is operating

100 base

DUP Green Ethernet channel is operating

full duplex

ON if 100 base network,
OFF if 10 base network
ON if full duplex network

ABORT Switch

The ABORT switch provides for manual application of the IRQ7 interrupt signal. This
operation will allow the dBUG monitor to stop execution of a user program and maintain the
CPU operating state for user examination. After application of the ABORT switch, dBUG will
prompt the current program instruction pending. Display is similar to a breakpoint operation.

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CML-5485 USER MANUAL V1.0 06/22/05

SYSTEM CLOCK

The system clocks are provided by U2 with 25MHz reference oscillator Y2. U2 provides
separate 50MHz primary clocks to the MCF5485, PCI Bus and connector J1, and the
BUS_PORT if R63 is installed. A 25Mhz clock from U2 is also provided to the Ethernet PHY
device U12. The MCF5485 local bus operates at the 50Mhz primary clock frequency. Internal
PLL clock generation of the MCF5485 provides 100MHz DDRAM clock and 200MHz core
clock. The MCF5485 USB reference clock of 12MHz is provided by crystal oscillator Y1.

MEMORY

Memory is provided in the MCF5485 device and externally on the development board. The
MCF5485 provides 64K bytes of SRAM memory internally. Board memory consists of 64M
Bytes of DDRAM on the SDRAM bus and 8M bytes of Flash memory on the FLEX Bus. The
debug monitor occupies the first or lower 256K bytes of the board Flash memory. User should
refer to the dBUG memory map for default memory allocation and physical locations.

The BUS and ADDRESS Ports maybe applied for Flex Bus expansion off board.
Note: The MCF5485 DDRAM controller must be configured prior to application of the memory

space when BDM or JTAG tools are applied.

COMMUNICATION PERIPHERALS

The CML-5485 provides 7 conditioned communication ports, 2 x 10/100TX Ethernet, 2 x
RS232 Serial COM, 2 x CAN, and a USB port. User should refer to the respective manual
chapter for details of operation and connection of each port.

CML-5485 PORTS AND CONNECTORS

PWR - Power Jack

PWR provides the default power input to the board. The power jack accepts a standard 2.0 ~

2.1mm center barrel plug connector (positive voltage center) to provide the +V supply of +8 to

+20 VDC (+12VDC typical).

+Volts, 2mm center

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CML-5485 USER MANUAL V1.0 06/22/05

COM1 and COM2 Ports

The COM1 and 2 ports provide standard 9 pin serial connection with RS232 type interface to
the MCF5485 UART0 and UART1 peripherals respectfully. The COM1 port is applied by the
dBUG monitor at 19.2K baud default. Both ports will connect to a standard PC COM port with
a straight through type 9 pin serial cable. Following is the DB9S connection reference.

COM1 or COM2

1

1

TXD

RXD

GND

4

2 6
3 7
4 8
5 9

The 1, 4, 6 and 9 pins provide RS232 status signals. These DB9 connector locations are
provided access pads behind the connector.

COM PORT OPTIONS

X
6
7 CTS
8 RTS
9

The COM-1or 2 port is a DB9 socket connector with RS232
signal levels.

RXD maybe isolated from port by option, see chart below.
CTS / RTS are enabled by options, see chart below.
1,4,6 connected for status null to host

The following table provides COM options and default connections to the MCF5485
Programmable Serial Controllers (PSC).

Port Signal Option Default MCF5485 Signal

COM1 RXD RXD0 Closed PSC0RXD
COM1 RTS RTS0 Open PSC0RTS
COM1 CTS CTS0 Open PSC0CTS
COM2 RXD RXD1 Closed PSC1RXD
COM2 RTS RTS1 Open PSC1RTS
COM2 CTS CTS1 Open PSC1CTS

Notes:

1) All options are SMT 0805 component size pads.

2) Default closed options must be opened by cutting trace between option pads.

3) To close an option a SMT 0805 resistor of 0 ohms maybe applied.

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CML-5485 USER MANUAL V1.0 06/22/05

CAN Port

The CAN port provides two physical interface layers for the two channels of MCF5485
FlexCAN Controller Area Network version 2.0B peripheral. The FlexCAN transmit and receive
signals are connected to a 3.3V CAN transceivers capable of 1M baud communication
(SN65HVD230). Transceiver differential CAN network signals are provided a 62 ohm
termination by components RC1 and RC2, and applied to the CAN port connector.

Each CAN transceiver has CAN signal drive control via the RS0 / 1 test pad on the
development board. The RS signal is provided a 1K Ohm pull-down resistor for the maximum
signal rate setting. User may refer to the SN65HVD230 data sheet and apply additional signal
control at the RS test pad.

The CAN Port connector is a 5 position screw terminal block that will accept discreet wiring for
CAN Bus connections.

CAN Port Term Block

1 2 3 4 5

CAN PORT Connection and Options Table

CAN Port Port Signal MCF5485 Signals OPTION Default

1 CAN_HI_0 CANTX0 CT1 Closed
2 CAN_LO_0 CANRX0 CT2 Closed
3 Ground
4 CAN_HI_1 CANTX1 CT3 Closed
5 CAN_LO_1 CANRX1 CT4 Closed

Notes:

1) All options are SMT 0805 component size pads.

2) Default closed options must be opened by cutting trace between option pads.

3) To close an option a SMT 0805 resistor of 0 ohms maybe applied.

J4 and J5 ETHERNET Ports

These ports provide the 10/100TX Ethernet physical interface connections to the MCF5485
FEC0 and 1 respectfully. Port configuration applies a dual PHY device, the Intel LXT973
10/100TX physical layer transceiver (PHY) for a complete IEEE802.3 interface. Features of
the port include Auto MDX cable or connection configuration type detection, 3 status indicators
per port, and integrated magnetics RJ45 connectors.

Refer to the LXT973 data sheet for register and operation details.

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CML-5485 USER MANUAL V1.0 06/22/05

Ethernet Status Indicators

LNK
100

DUP

Green Ethernet has Link ON with Network connected
Green Ethernet is operating 100 base ON if 100 base network, OFF if 10 base

network

Green Ethernet is operating full duplex ON if full duplex network

Note: Ethernet port must be initialized and operating for status indications.
Refer to the CML5485_SCH_C.pdf drawing for details on hardware connections to this port.

MCU_PORT

The MCU PORT provides access to the MCF5485 I/O ports. Ports applied on the board are
noted.

DACK0*

DREQ0*
(Note 1) CANRX1
(Note 1) CANRX0

TIN2
TIN1
TIN0

PSC3RTS*

PSC3RXD
PSC2RXD

(Note 2) PSC1RTS

(Note 2) PSC1RXD
(Note 3) PSC0RTS*
(Note 3) PSC0RXD

DSPISOUT

DSPISCK

DSPICS3
DSPICS0

SCL
PCIBG1*
PCIBG3*
PCIBR1*
PCIBR3*

IRQ6*

GND

Notes:

1) These signals have peripheral connection on the CML-5485 board CAN Port.

2) These signals have peripheral connection on the CML-5485 board COM2 Port.

3) These signals have peripheral connection on the CML-5485 board COM1 Port.

4) This signal has peripheral connection on the CML-5485 board J1 PCI Port.

1 2
3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

DACK1*
DREQ1*
CANTX1 (Note 1)
CANTX0 (Note 1)
TOUT2
TOUT1
TOUT0
PSC3CTS*
PSC3TXD
PSC2TXD
PSC1CTS* (Note 2)
PSC1TXD (Note 2)
PSC0CTS* (Note 3)
PSC0TXD (Note 3)
DSPISIN
DSPICS5
DSPICS2
SDA
PCIBG0*
PCIBG2*

PCIBR0* (Note 4)

PCIBR2*
IRQ7*
IRQ5*
+3.3V

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CML-5485 USER MANUAL V1.0 06/22/05

BUS_PORT

The BUS PORT provides access to the MCF5485 FLEX Bus data and control signals. Most
signals on the BUS PORT have a peripheral connection on the CML-5485 board. The FBCS0*
chip select is dedicated to the on board flash memory. The board must boot from the on board
flash.

AD30
AD28
AD26
AD24
AD22
AD20
AD18
AD16
AD14
AD12

A10
AD8
AD6
AD4
AD2
AD0

RSTO*

(Note 1) CLKOUT

FBCS2*
FBCS4*

BWE0*
BWE2*

R/W*

TA*

+3.3V

Notes:

1) The CLKOUT signal must be enabled by installing option resistor R63. The value of R63 should be selected
to reduce connection reflections of the 50MHz signal.

2) The default bus size of FBCS0* is 16 bits data on AD16 – AD31.

3) The FLEX BUS operates in Multiplexed address and data mode by default. The address port provides de­multiplexed address signals.

1 2
3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

AD31
AD29
AD27
AD25
AD23
AD21
AD19
AD17
AD15
AD13
AD11
AD9
AD7
AD5
AD3
AD1
RESET* IN
FBCS1*
FBCS3*
FBCS5*
BWE1*
BWE3*
TS*
OE*
GND

12