Avnet Ultra96-V2 Hardware User's Manual

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Ultra96-V2 Hardware User’s Guide

Revision 1

Version 1.0

Copyright © 2019 Avnet, Inc. AVNET, “Reach Further,” and the AV logo are registered

trademarks of Avnet, Inc. All other brands are the property of their respective owners.

LIT# Ultra96-V2-HW-User-Guide-rev-1-0-V1

Contents

1 Document Control ................................................................................................. 3

2 Version History ...................................................................................................... 3

3 Introduction ........................................................................................................... 3

3.1 Glossary ................................................................................................................................... 5

3.2 Reference Documents ............................................................................................................. 5

4 Ultra96-V2 Architecture and Features ................................................................... 6

4.1 List of Features ........................................................................................................................ 6

4.2 Ultra96-V2 Block Diagram ....................................................................................................... 7

5 Functional Description ........................................................................................... 8

5.1 Zynq UltraScale+ MPSoC ........................................................................................................ 8

5.1.1 SBVA484 Package ........................................................................................................... 9

5.1.2 PL I/Os (Banks 26, 65, 66) ............................................................................................. 10

5.1.3 PS MIOs (Banks 500, 501, 502) .................................................................................... 13

5.1.4 PS Bank 503 .................................................................................................................. 17

5.1.5 PS Bank 504 .................................................................................................................. 18

5.1.6 PS Bank 505 .................................................................................................................. 20

5.2 LPDDR4 Memory ................................................................................................................... 21

5.3 microSD Card ......................................................................................................................... 21

5.4 USB ........................................................................................................................................ 22

5.4.1 USB5744 Implementation Details .................................................................................. 22

5.5 Wi-Fi / Bluetooth..................................................................................................................... 23

5.5.1 Wi-FI ............................................................................................................................... 23

5.5.2 Bluetooth ........................................................................................................................ 23

5.5.3 Bluetooth Audio .............................................................................................................. 23

5.6 Mini DisplayPort ..................................................................................................................... 23

5.7 UART ..................................................................................................................................... 23

5.8 I2C .......................................................................................................................................... 24

5.9 User LEDs .............................................................................................................................. 24

5.10 MPSoC Thermal Bracket with Fan ......................................................................................... 24

5.11 Expansion Connectors ........................................................................................................... 24

5.11.1 Low Speed Expansion Connector (J7) .......................................................................... 24

5.11.2 High Speed Expansion Connector ................................................................................. 26

6 Configuration and Debug .................................................................................... 27

6.1 Boot Mode .............................................................................................................................. 27

6.2 JTAG Configuration and Debug ............................................................................................. 27

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7 Power .................................................................................................................. 28

Version

Date

Comment

1.0

23 May 2019

Initial Release

7.1 External Power Connection ................................................................................................... 28

7.2 Power Estimation Using XPE ................................................................................................. 28

7.3 Power Regulators .................................................................................................................. 29

7.4 Power Sequence .................................................................................................................... 30

8 Clocks ................................................................................................................. 32

9 Reset ................................................................................................................... 32

10 Specifications and Ratings .................................................................................. 32

11 Getting Help and Support .................................................................................... 32

1 Document Control

Document Version: 1.0

Document Date: 23 May 2019

2 Version History

3 Introduction

The main purposes of the Ultra96-V2 Kit are:

• Provide a Xilinx entry in the 96Boards community

• Combine ARM processing with programmable logic in a convenient and expandable board

• Showcase a wide range of potential peripherals and acceleration engines in the programmable logic

that is not available from other 96Boards offerings

• Be a low-cost starter kit for Zynq UltraScale+ MPSoC developers

• Showcase hardware acceleration for software bottlenecks

• Allow expansion to a variety of sensors and peripherals through the 96Boards mezzanine

connectors

• Target a number of applications for development, including:

o Artificial Intelligence

o Machine Learning

o IoT/Cloud connectivity for add-on sensors

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o Embedded Computing

o Robotics

o Wireless design and demonstrations using Wi-Fi and Bluetooth

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3.1 Glossary

Term

Definition

PS

Zynq UltraScale+ MPSoC Processing System

PL

Zynq UltraScale+ MPSoC Programmable Logic

MIO

PS Multiplexed Input Output Pins

POR

Power On Reset

APU

Application Processing Unit

RPU

Real-time Processing Unit

GPU

Graphics Processing Unit

SYSMON

System Monitor

HD

High Density PL I/O Pins

HP

High Performance PL I/O Pins

PMBus

Power Management Bus

3.2 Reference Documents

[1] Zynq UltraScale+ MPSoC Overview

[2] Zynq UltraScale+ MPSoC DC and AC Switching Characteristics

[3] Zynq UltraScale+ MPSoC Technical Reference Manual

[4] Zynq UltraScale+ MPSoC Packaging and Pinout Product Specification

[5] Zynq UltraScale+ MPSoC PCB Design Guide

[6] UltraScale Architecture SelectIO Resources

[7] SBVA484 Package File

[8] Xilinx Vivado Design Suite

[9] Xilinx Software Development Kit

[10] 96Boards Specification

[11] WiLink8 2.4GHz WiFi + Bluetooth Module

[12] USB3320 Hi-Speed USB 2.0 ULPI Transceiver

[13] USB5744 Smart Hub

[14] Micron MT53B512M32D2NP-062 WT:C LPDDR4 SDRAM datasheet

[15] Delkin Devices Utility Industrial MLC microSD

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4 Ultra96-V2 Architecture and Features

This section summarizes the features of the development board, followed by functional descriptions of each
circuit.

4.1 List of Features

The Ultra96-V2 Developer Kit supports the following features:

• Zynq UltraScale+ MPSoC ZU3EG SBVA484

• Storage

o Micron 2 GB (512M x32) LPDDR4 Memory

o MicroSD Socket

 Ships with Delkin Utility MLC Industrial 16GB card

• Wi-Fi / Bluetooth

• DisplayPort

• 1x USB 3.0 Type Micro-B upstream port

• 2x USB 3.0 Type A downstream ports

• 40-pin Low-speed expansion header

• 60-pin High speed expansion header

• Mounted on thermal bracket with fan

Note that there is no on-board, wired Ethernet interface. All communications must be done via USB,
Wi-Fi, JTAG, or expansion interface.

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4.2 Ultra96-V2 Block Diagram

Figure 1 – Ultra96-V2 Block Diagram

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5 Functional Description

The following sections provide brief descriptions of each feature provided on the Ultra96-V2 board.

5.1 Zynq UltraScale+ MPSoC

The Zynq UltraScale+ MPSoC ZU3EG device (in the SBVA484 package) contains:

• Processor System (PS):
o Application Processing Unit

Quad-core ARM Cortex-A53 MPCore with CoreSight; NEON & Single/Double
Precision Floating Point; 32KB/32KB L1 Cache, 1MB L2 Cache

o Real-Time Processing Unit

Dual-core ARM Cortex-R5 with CoreSight; Single/Double Precision Floating
Point; 32KB/32KB L1 Cache, and TCM

o Embedded and External Memory

256KB On-Chip Memory w/ECC; External DDR4; DDR3; DDR3L; LPDDR4;
LPDDR3; External Quad-SPI; NAND; eMMC

o General Connectivity

214 PS I/O; UART; CAN; USB 2.0; I2C; SPI; 32b GPIO; Real Time Clock;
WatchDog Timers; Triple Timer Counters

o High-Speed Connectivity

4 PS-GTR; PCIe Gen1/2; Serial ATA 3.1; DisplayPort 1.2a; USB 3.0; SGMII

o Graphic Processing Unit

ARM Mali™-400 MP2; 64KB L2 Cache

• Programmable Logic (PL)

o System Logic Cells 154,350
o CLB Flip-Flops 141,120
o CLB LUTs 70,560
o Distributed RAM (Mb) 1.8
o Block RAM Blocks 216
o Block RAM (Mb) 7.6
o UltraRAM Blocks 0
o UltraRAM (Mb) 0
o DSP Slices 360
o CMTs 3
o System Monitor 2

• I/O

o Max PS MIO 78

MIO = multiplexed I/O (up to three banks of 26 I/Os) with support for I/O
voltage of 1.8V or 3.3V

o Max. PS Transceiver I/O 4 transmit and 4 receive pairs

o Max. PL HP I/O 156

HP = High-performance I/O with support for I/O voltage from 1.0V to

1.8V

o Max. PL HD I/O 96

HD = High-density I/O with support for I/O voltage from 1.2V to 3.3V

o Max. PL Transceiver I/O 4 transmit and 4 receive pairs

5.1.1 SBVA484 Package

Figure 2 – SBVA484 Package Diagram

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5.1.2 PL I/Os (Banks 26, 65, 66)

MPSoC Pin Number

Bank

MPSoC Site Name

Function

A9

RADIO_LED0

B9

RADIO_LED1

B5

BT_HCI_CTS

B7

BT_HCI_RTS

E8

CSI0_MCLK

D8

CSI1_MCLK

D7

HD_GPIO_0

F8

HD_GPIO_1

E5

HD_GPIO_10

D6

HD_GPIO_11

D5

HD_GPIO_12

C7

HD_GPIO_13

B6

HD_GPIO_14

C5

HD_GPIO_15

F7

HD_GPIO_2

G7

HD_GPIO_3

F6

HD_GPIO_4

G5

HD_GPIO_5

A6

HD_GPIO_6

A7

HD_GPIO_7

G6

HD_GPIO_8

E6

HD_GPIO_9

C8

N/C

A8

N/C

Zynq UltraScale+ MPSoC Promammable Logic (PL) provides two types of I/O banks: High­density (HD) banks and high-performance (HP) banks. HD banks support a limited number of
single-ended I/O standards with speeds up to 250Mbps and VCCO voltages up to 3.30V. HP
banks support a large variety of high-speed I/O standards, including differential I/O, and support
VCCO voltages up to 1.80V.

ZU3EG provides one HD bank (Bank 26) with 24 pins, one HP bank (Bank 65) with 52 pins,
and another HP bank (Bank 66) with 6 pins.

The PL I/Os on Ultra96-V2 are tied to the Low-Speed 96Boards Mezzanine, the High-Speed
96Boards Mezzanine, Bluetooth, and the fan.

Table 1 – PL IO Bank 26

26

Bluetooth

HS Expansion

LS Expansion

N/C

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