Avnet Spartan-3E User Manual

Xilinx® Spartan™-3E Evaluation Kit

User Guide

Table of Contents

1.0 Introduction...............................................................................................................................................................................4

1.1 Description............................................................................................................................................................................4

1.2 Features ...............................................................................................................................................................................4

1.3 Demo Applications................................................................................................................................................................5

1.4 Ordering Information.............................................................................................................................................................6

2.0 Hardware ..................................................................................................................................................................................7

2.1 Spartan-3E FPGA.................................................................................................................................................................7

2.2 Configuration........................................................................................................................................................................8

2.2.1 Boundary Scan............................................................................................................................................................8

2.2.2 Configuring FPGA with SPI FLASH (default)...............................................................................................................9

2.2.3 Configuring FPGA over USB .......................................................................................................................................9

2.3 Creating a .HEX file..............................................................................................................................................................9

2.4 Programming SPI FLASH...................................................................................................................................................10

2.5 Avnet USB Utility................................................................................................................................................................11

2.6 Jumper Settings..................................................................................................................................................................13

2.7 Clocks.................................................................................................................................................................................15

2.8 On-board Display (2 Character Alphanumeric LED)...........................................................................................................15

2.9 DIP & Push-button Switches...............................................................................................................................................16

2.10 LEDs ..............................................................................................................................................................................17

2.11 Memory..........................................................................................................................................................................17

2.11.1 SPI Flash...................................................................................................................................................................17

2.12 Communication (RS-232, USB 2.0) ...............................................................................................................................18

2.12.1 RS-232.......................................................................................................................................................................18

2.12.2 USB 2.0 .....................................................................................................................................................................18

2.13 I/O Connectors...............................................................................................................................................................21

2.13.1 Header “J1”................................................................................................................................................................21

2.14 Power.............................................................................................................................................................................22

2.14.1 External AC/DC Adapter “J5”.....................................................................................................................................22

2.14.2 USB Power................................................................................................................................................................22

2.14.3 TI TPS75003..............................................................................................................................................................22

3.0 Software/BSP..........................................................................................................................................................................22

3.1 What is included.................................................................................................................................................................22

3.1.1 Segment Test Project ................................................................................................................................................22

4.0 List of Partners........................................................................................................................................................................23

Figures

Figure 1 – Spartan-3E Evaluation Board Assembly Drawing .....................................................................................................................5

Figure 2 - Spartan-3E Evaluation Board Picture.........................................................................................................................................6

Figure 3 - Spartan-3E Evaluation Kit Block Diagram..................................................................................................................................7

Figure 4 - Boundary Scan Mode Selection via JP6....................................................................................................................................8

Figure 5 - Configuration Connections – Par3 .............................................................................................................................................9

Figure 6 - Configuration Connections – Par IV...........................................................................................................................................9

Figure 7 - Select Target Board.................................................................................................................................................................12

Figure 8 - USB Utility GUI.........................................................................................................................................................................13

Figure 9 - Default Jumper Placement.......................................................................................................................................................15

Figure 10 - Barrel Power Connector "J5"..................................................................................................................................................22

Copyright © 2005 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are property of their respective owners. Avnet Electronics Marketing 2 of 23 Rev 1.0 06/14/2006

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Tables

Table 1 - Ordering Information ...................................................................................................................................................................6

Table 2 - Spartan-3E Attributes by Density ................................................................................................................................................7

Table 3 - FPGA Configuration from PROM/JTAG … Jumper Setting.........................................................................................................8

Table 4 - JTAG Headers (Par-3 & Par-4) Pin-Out......................................................................................................................................8

Table 5 - J6 Header (SPI) Pin-out ............................................................................................................................................................11

Table 6 - Available GCLK Sources...........................................................................................................................................................15

Table 7 - Ethernet PHY Modes.................................................................................................................................................................16

Table 8 - DIP switch FPGA Pin-out..........................................................................................................................................................16

Table 9 - Push button FPGA Pin-out........................................................................................................................................................16

Table 10 - LED FPGA Pin-out..................................................................................................................................................................17

Table 11 - SPI FPGA Pin-out ...................................................................................................................................................................17

Table 12 - RS-232 FPGA Pin-out.............................................................................................................................................................18

Table 13 - RS-232 Connector Pin-out ......................................................................................................................................................18

Table 14 - USB Interface FPGA Pin-out...................................................................................................................................................20

Table 15 - Header "J1" Pin-out.................................................................................................................................................................21

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1.0 Introduction

The purpose of this manual is to describe the functionality and contents of the Spartan-3E Evaluation Kit from Avnet Electronics Marketing. This document includes instructions for operati ng the board, descriptions of the hard ware features and explanations of the example projects.

1.1 Description

The Spartan-3E Evaluation Kit provides a platform for engineers designing with the Xilinx Spartan-3E FPGA. The board provides the necessary hardware to not only evaluate the features of the Spartan-3E but also to implement user applications with a basic set of peripherals. Example projects are provided to help the user understa nd the design tool flow and leverage from known functional designs.

1.2 Features

FPGA

— Xilinx XC3S100E-TQ144 Spartan-3E FPGA

Board I/O Connectors

— 50-pin header for user I/O — 8 discrete LEDs — 2 push-buttons — 4-position DIP-switch — Dual character alpha numeric display

Memory

— ST Microelectronics SPI serial FLASH

Communication

— USB 2.0 — RS-232 serial port

Power

— USB or 5V wall-mount (not included) — Texas Instruments TPS75003 triple supply

Configuration

— SPI serial FLASH to FPGA — USB download utility — Support for Xilinx Parallel Cable IV — Fly-wire support for and Xilinx or compatible cable

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JP3

+5V

JP7

Par-IV Prog

JR1

GND TMS TCK TDO TDI

Cypress

Programming

Dip

Switches

TP2 TP3 TP1

3.3V 2.5V

Fly-Wire

U11

Texas Instruments

TPS75003

JP1 JP4

U10

100

SPI

Flash

MHz

1.2V

Xilinx

XC3S100E

FPGA

SW1

DB9

RS232

SW2

electronics marketing

DESIGN SERVICES

USB 2.0

USB

JP2

JP8 JP9

SW3

FPGA Reconfig

General Purpose I/O Header

JP6

LEDs

JP5

Figure 1 – Spartan-3E Evaluation Board Assembly Drawing

1.3 Demo Applications

The Spartan-3E Evaluation Kit from Avnet Electronics Marketing comes with example proj ects designed in Xilinx ISE. The example projects help the user get started by leveraging a lready tested an d functional de signs. The e xample projects that will be discussed in detail later in this document are listed below.

*Note: There may be additional demos which were developed after the printing of this document. For additional demo applications, please contact your local Avnet FAE.

Segment Test Project

— Display count value on segment display — Provide test message over RS-232 — Source Code Included

Released Literature # ADS-005604

Figure 2 - Spartan-3E Evaluation Board Picture

1.4 Ordering Information

The following table lists the evaluation kit part numbers and available software options. For more information, visit the Internet link at

Part Number Hardware

ADS-XLX-SP3E-EVL100 Xilinx Spartan-3E Evaluation Kit with an XC3S100E ADS-BASEX-BUNDLE ISE BaseX (only available with purchase of the above part number)

http://www.em.avnet.com/ads.

Table 1 - Ordering Information

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2.0 Hardware

This section of the manual describes the hardware of the Spartan-3E Evaluatio n Board. T he hardware was design ed with the Spart an3E FPGA as the focal point. The block diagram is shown in

Figure 8.

Figure 3 - Spartan-3E Evaluation Kit Block Diagram

2.1 Spartan-3E FPGA

The Spartan-3E Evaluation Board was designed to support the Spartan-3E FPGA in the 144-pin package (TQ144). This package supports two densities 3S100E and 3S250E tho ugh initially only the 3S100E will be offered in a product. Table 2 describes the attributes of the Spartan-3E device based on density.

Spartan-

3E System Logic BlockRAM

Part Gates Cells (bits) BRAM Multipliers DCMs User I/O (144

XC3S100E 100K 2,160 72K 4 4 2 108 XC3S250E 250K 5,508 216K 12 12 4 108

Dedicated

Max

package)

Table 2 - Spartan-3E Attributes by Density

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Avnet Spartan-3E User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual