Avago Technologies LSI53C1000R User Manual

TECHNICAL

MANUAL

LSI53C1000R PCI to Ultra160 SCSI Controller

August 2003

Version 2.2

DB14-000152-04

This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an ofﬁcer of LSI Logic Corporation.

LSI Logic products are not intended for use in life-support appliances, devices, or systems. Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic ofﬁcer is prohibited.

Document number DB14-000152-04, Version 2.2 (August 2003). This document describes the LSI Logic LSI53C1000R PCI to Ultra160 SCSI Controller and will remain the ofﬁcial reference source for all revisions/releases of this product until rescinded by an update.

LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.

Ultra/Ultra2/Ultra3/Ultra160 SCSI are terms used by the SCSI Trade Association (STA) to describe various SCSI speciﬁcations. Refer to the

subsection entitled “Related Publications,” for additional information on

LSI Logic, the LSI Logic logo design, LVDLink, SCRIPTS, SDMS, SURElink, and TolerANT are registered trademarks or trademarks of LSI Logic Corporation. All other brand and product names may be trademarks of their respective companies.

To receive product literature, visit us at http://www.lsilogic.com. For a current list of our distributors, sales ofﬁces, and design resource

centers, view our web page located at http://www.lsilogic.com/contacts/index.html

Audience

Organization

Preface

This book is the primary reference and technical manual for the LSI Logic LSI53C1000R PCI to Ultra160 SCSI Controller. It contains a complete functional description for the product and includes complete physical and electrical speciﬁcations.

This document was prepared for system designers and programmers who are using this device to design an Ultra160 SCSI port for PCI-based personal computers, workstations, servers, or embedded applications.

This document has the following chapters and appendixes:

• Chapter 1, Introduction, provides general information about the

LSI53C1000R.

• Chapter 2, Functional Description, describes the main functional

areas of the chip in greater detail, including the interfaces to the SCSI bus and external memory.

• Chapter 3, Signal Descriptions, contains the pin diagram and signal

descriptions.

• Chapter 4, Registers, describes each bit in the operating registers,

and is organized by register address.

• Chapter 5, SCSI SCRIPTS Instruction Set, deﬁnes all of the

SCSI SCRIPTS instructions that are supported by the LSI53C1000R.

• Chapter 6, Speciﬁcations, contains the electrical characteristics and

AC timing diagrams.

• Appendix A, Register Summary, is a register summary.

Preface iii

• Appendix B, External Memory Interface Diagram Examples,

Related Publications

For background please contact:

ANSI

www.ansi.org 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2)

Global Engineering Documents

www.global.ihs.com 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U.S.) FAX (303) 397-2740 Ask for document number X3.131-1994 (SCSI-2) or X3.253

(SCSI-3 Parallel Interface)

contains several example interface drawings for connecting the LSI53C1000R to external ROMs.

ENDL Publications

www.r ahul.net/endl/ 14426 Black Walnut Court Saratoga, CA 95070 (408) 867-6642 Document names: SCSI Bench Reference, SCSI Encyclopedia, SCSI Tutor

Prentice Hall

113 Sylvan Avenue Englewood Cliffs, NJ 07632 (800) 947-7700 Ask for document number ISBN 0-13-796855-8, SCSI: Understanding

the Small Computer System Interface

iv Preface

LSI Logic World Wide Web Home Page

www.lsil.com SCSI SCRIPTS™ Processors Programming Guide, Document No. DB15-000159-01

PCI Special Interest Group

www.pcisig.org 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344

Conventions Used in This Manual

The word assert means to drive a signal true or active. The word deassert means to drive a signal false or inactive.

Hexadecimal numbers are indicated by the preﬁx “0x”—for example, 0x32CF. Binary numbers are indicated by the preﬁx “0b”—for example, 0b0011.0010.1100.1111.

Revision Record

Revision Date Remarks

1.0 6/2000 Preliminary version

2.0 11/2000 Final version

2.1 5/2001 Changes to Chapter 3 and Chapter 6 concerning pinouts

2.2 6/2003 Added instructions for setting the GPIO registers. Changed Vih (max) to

11.0 V in Table 6.10. In Table 3.1, changed GPIO[4:0] pins to “Pulled down internally.”

Preface v

vi Preface

Contents

Chapter 1 Introduction

1.1 General Description 1-1

1.2 Beneﬁts of Ultra160 SCSI 1-4

1.3 Beneﬁts of SURElink (Ultra160 SCSI Domain Validation) Technology 1-5

1.4 Beneﬁts of LVDlink Technology 1-5

1.5 Beneﬁts of TolerANT®Technology 1-6

1.6 Summary of LSI53C1000R Beneﬁts 1-7

1.6.1 SCSI Performance 1-7

1.6.2 PCI Performance 1-8

1.6.3 Integration 1-9

1.6.4 Ease of Use 1-9

1.6.5 Flexibility 1-10

1.6.6 Reliability 1-11

1.6.7 Testability 1-11

Chapter 2 Functional Description

2.1 PCI Functional Description 2-3

2.1.1 PCI Addressing 2-3

2.1.2 PCI Bus Commands and Functions Supported 2-4

2.1.3 PCI Cache Mode 2-11

2.2 SCSI Functional Description 2-18

2.2.1 SCRIPTS Processor 2-19

2.2.2 Internal SCRIPTS RAM 2-20

2.2.3 64-Bit Addressing in SCRIPTS 2-21

2.2.4 Hardware Control of SCSI Activity LED 2-21

2.2.5 Designing an Ultra160 SCSI System 2-22

2.2.6 Prefetching SCRIPTS Instructions 2-31

2.2.7 Opcode Fetch Burst Capability 2-32

Contents vii

2.2.8 Load and Store Instructions 2-33

2.2.9 JTAG Boundary Scan Testing 2-33

2.2.10 Parity/CRC/AIP Options 2-34

2.2.11 DMA FIFO 2-36

2.2.12 SCSI Data Paths 2-37

2.2.13 SCSI Bus Interface 2-39

2.2.14 Select/Reselect during Selection/Reselection 2-41

2.2.15 Synchronous Operation 2-41

2.2.16 Interrupt Handling 2-45

2.2.17 Interrupt Routing 2-53

2.2.18 Chained Block Moves 2-55

2.3 Parallel ROM Interface 2-58

2.4 Serial EEPROM Interface 2-60

2.4.1 Default Download Mode 2-60

2.4.2 No Download Mode 2-61

2.5 Power Management 2-61

2.5.1 Power State D0 2-62

2.5.2 Power State D1 2-62

2.5.3 Power State D2 2-63

2.5.4 Power State D3 2-63

Chapter 3 Signal Descriptions

3.1 Signal Organization 3-1

3.2 Internal Pull-ups and Pull-downs 3-4

3.3 PCI Bus Interface Signals 3-5

3.3.1 System Signals 3-5

3.3.2 Address and Data Signals 3-6

3.3.3 Interface Control Signals 3-7

3.3.4 Arbitration Signals 3-8

3.3.5 Error Reporting Signals 3-9

3.3.6 Interrupt Signals 3-9

3.4 SCSI Bus Interface Signals 3-10

3.5 General Purpose I/O (GPIO) Signals 3-13

3.6 Flash ROM and Memory Interface Signals 3-14

3.7 Test Interface Signals 3-15

3.8 Power and Ground Signals 3-16

3.9 MAD Bus Programming 3-17

viii Contents

Chapter 4 Registers

4.1 PCI Conﬁguration Registers 4-1

4.2 SCSI Registers 4-21

4.3 SCSI Shadow Registers 4-125

Chapter 5 SCSI SCRIPTS Instruction Set

5.1 SCSI SCRIPTS 5-1

5.2 Block Move Instructions 5-4

5.2.1 First Dword 5-4

5.2.2 Second Dword 5-13

5.2.3 Third Dword 5-14

5.3 I/O Instructions 5-14

5.3.1 First Dword 5-14

5.3.2 Second Dword 5-22

5.4 Read/Write Instructions 5-23

5.4.1 First Dword 5-23

5.4.2 Second Dword 5-24

5.4.3 Read-Modify-Write Cycles 5-24

5.4.4 Move to/from SFBR Cycles 5-25

5.5 Transfer Control Instructions 5-27

5.5.1 First Dword 5-27

5.5.2 Second Dword 5-33

5.5.3 Third Dword 5-33

5.6 Memory Move Instructions 5-34

5.6.1 Read/Write System Memory from a SCRIPT 5-35

5.6.2 Second Dword 5-36

5.6.3 Third Dword 5-37

5.7 Load and Store Instructions 5-37

5.7.1 First Dword 5-39

5.7.2 Second Dword 5-40

Chapter 6 Speciﬁcations

6.1 DC Characteristics 6-1

6.2 TolerANT Technology Electrical Characteristics 6-7

6.3 AC Characteristics 6-11

6.4 PCI and External Memory Interface Timing Diagrams 6-14

Contents ix

6.4.1 Target Timing 6-15

6.4.2 Initiator Timing 6-24

6.4.3 External Memory Timing 6-41

6.5 SCSI Timing Diagrams 6-62

6.6 Package Drawings 6-71

Appendix A Register Summary

Appendix B External Memory Interface Diagram Examples

Index

Customer Feedback

x Contents

Figures

1.1 Typical LSI53C1000R Board Application 1-2

1.2 Typical LSI53C1000R System Application 1-3

2.1 LSI53C1000R Block Diagram 2-2

2.2 DMA FIFO Sections 2-36

2.3 LSI53C1000R Host Interface SCSI Data Paths 2-37

2.4 Regulated Termination for Ultra160 SCSI 2-40

2.5 Determining the Synchronous Transfer Rate 2-45

2.6 Interrupt Routing Hardware Using the LSI53C1000R 2-54

2.7 Block Move and Chained Block Move Instructions 2-55

3.1 LSI53C1000R Signal Grouping 3-3

4.1 Single Transition Transfer Waveforms 4-104

4.2 DT Transfer Waveforms (XCLKS Examples) 4-105

4.3 DT Transfer Waveforms (XCLKH Examples) 4-106

5.1 SCRIPTS Overview 5-4

5.2 Block Move Instruction – First Dword 5-5

5.3 Block Move Instruction – Second Dword 5-13

5.4 Block Move Instruction – Third Dword 5-14

5.5 First 32-Bit Word of the I/O Instruction 5-14

5.6 Second 32-Bit Word of the I/O Instruction 5-22

5.7 Read/Write Instruction – First Dword 5-23

5.8 Read/Write Instruction – Second Dword 5-24

5.9 Transfer Control Instructions – First Dword 5-27

5.10 Transfer Control Instructions – Second Dword 5-33

5.11 Transfer Control Instructions – Third Dword 5-33

5.12 Memory Move Instructions – First Dword 5-35

5.13 Memory Move Instructions – Second Dword 5-36

5.14 Memory Move Instructions – Third Dword 5-37

5.15 Load and Store Instruction – First Dword 5-39

5.16 Load and Store Instructions – Second Dword 5-40

6.1 LVD Driver 6-3

6.2 LVD Receiver 6-4

6.3 Rise and Fall Time Test Condition 6-8

6.4 SCSI Input Filtering 6-8

6.5 Hysteresis of SCSI Receivers 6-9

6.6 Input Current as a Function of Input Voltage 6-9

6.7 Output Current as a Function of Output Voltage 6-10

6.8 External Clock 6-11

6.9 Reset Input 6-12

6.10 Interrupt Output 6-13

6.11 PCI Conﬁguration Register Read 6-16

6.12 PCI Conﬁguration Register Write 6-17

6.13 Operating Registers/SCRIPTS RAM Read, 32 Bits 6-18

6.14 Operating Register/SCRIPTS RAM Read, 64 Bits 6-20

6.15 Operating Register/SCRIPTS RAM Read, 32 Bits 6-21

6.16 Operating Register/SCRIPTS RAM Write, 64 Bits 6-23

6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-25

6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-27

6.19 Back to Back Read, 32-Bit Address and Data 6-29

6.20 Back to Back Write, 32-Bit Address and Data 6-31

6.21 Burst Read, 32-Bit Address and Data 6-33

6.22 Burst Read, 64-Bit Address and Data 6-35

6.23 Burst Write, 32-Bit Address and Data 6-37

6.24 Burst Write, 64-Bit Address and Data 6-39

6.25 External Memory Read 6-42

6.25 External Memory Read (Cont.) 6-43

6.26 External Memory Write 6-46

6.26 External Memory Write (Cont.) 6-47

6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Read Cycle 6-49

6.27 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Read Cycle (Cont.) 6-49

6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Write Cycle 6-51

6.28 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Write Cycle (Cont.) 6-51

6.29 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte

Access Read Cycle 6-52

6.29 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte

Access Read Cycle (Cont.) 6-53

6.30 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte

Access Write Cycle 6-54

6.30 Normal/Fast Memory (≥ 128 Kbytes) Multiple Byte

Access Write Cycle (Cont.) 6-55

6.31 Slow Memory (≥ 128 Kbytes) Read Cycle 6-57

xii

6.31 Slow Memory (≥ 128 Kbytes) Read Cycle (Cont.) 6-57

6.32 Slow Memory (≥ 128 Kbytes) Write Cycle 6-59

6.32 Slow Memory (≥ 128 Kbytes) Write Cycle (Cont.) 6-59

6.33 ≤ 64 Kbytes ROM Read Cycle 6-60

6.34 ≤ 64 Kbytes ROM Write Cycle 6-61

6.35 Initiator Asynchronous Send 6-62

6.36 Initiator Asynchronous Receive 6-63

6.37 Target Asynchronous Send 6-63

6.38 Target Asynchronous Receive 6-64

6.39 Initiator and Target ST Synchronous Transfer 6-66

6.40 Initiator and Target DT Synchronous Transfer 6-69

6.41 LSI53C1000R 456 BGA Chip – Top View 6-72

6.41 LSI53C1000R 456 BGA Chip – Top View (Cont.) 6-73

6.42 LSI53C1000R 456 BGA Mechanical Drawing 6-78

B.1 16 Kbyte Interface with 200 ns Memory B-1 B.2 64 Kbyte Interface with 150 ns Memory B-2 B.3 128, 256, 512 Kbyte or 1 Mbyte Interface

with 150 ns Memory B-3

B.4 512 Kbyte Interface with 150 ns Memory B-4

xiii

xiv

Tables

2.1 PCI Bus Commands and Encoding Types 2-5

2.2 PCI Cache Mode Alignment 2-11

2.3 New Phases on SCSI Bus 2-23

2.4 Bits Used for Parity/CRC/AIP Control and Generation 2-34

2.5 SCSI Parity Errors and Interrupts 2-36

2.6 SCF Divisor Values 2-42

2.7 Parallel ROM Support 2-59

2.8 Default Download Mode Serial EEPROM Data Format 2-61

2.9 Power States 2-62

3.1 LSI53C1000R Internal Pull-ups and Pull-downs 3-4

3.2 System Signals 3-5

3.3 Address and Data Signals 3-6

3.4 Interface Control Signals 3-7

3.5 Arbitration Signals 3-8

3.6 Error Reporting Signals 3-9

3.7 Interrupt Signals 3-9

3.8 SCSI Bus Interface Signals 3-10

3.9 SCSI Signals 3-10

3.10 SCSI Control Signals 3-12

3.11 GPIO Signals 3-13

3.12 Flash ROM and Memory Interface Signals 3-14

3.13 Test Interface Signals 3-15

3.14 Power and Ground Signals 3-16

3.15 MAD[3:1] Pin Decoding 3-18

4.1 PCI Conﬁguration Register Map 4-2

4.2 SCSI Register Map 4-22

4.3 Maximum Synchronous Offset 4-34

4.4 DT Transfer Rates 4-107

4.5 Single Transition Transfer Rates 4-110

5.1 Read/Write Instructions 5-25

6.1 Absolute Maximum Stress Ratings 6-2

6.2 Operating Conditions 6-2

6.3 LVD Driver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,

SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-3

6.4 LVD Receiver SCSI Signals – SD[15:0], SDP[1:0], SREQ/,

SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-3

6.5 DIFFSENS SCSI Signals 6-4

6.6 Input Capacitance 6-4

6.7 8 mA Bidirectional Signals – GPIO0_FETCH/,

GPIO1_MASTER/, GPIO2, GPIO3, GPIO4 6-5

6.8 4 mA Bidirectional Signals – MAD[7:0] 6-5

6.9 4 mA Output Signals – MAS[1:0]/, MCE/,

MOE/_TESTOUT, MWE/, TDO 6-5

6.10 8 mA PCI Bidirectional Signals – AD[63:0], C_BE[7:0]/,

FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR, PAR64, REQ64/, ACK64/ 6-6

6.11 Input Signals – CLK, GNT/, IDSEL, RST/, SCLK, TCK, TDI,

TEST_HSC, TEST_RST/, TMS 6-6

6.12 8 mA Output Signals – INTA/, INTB/, ALT_INTA/,

ALT_INTB/, REQ/, SERR/ 6-6

6.13 TolerANT Technology Electrical Characteristics

for SE SCSI Signals 6-7

6.14 External Clock 6-11

6.15 Reset Input 6-12

6.16 Interrupt Output 6-13

6.17 PCI Conﬁguration Register Read 6-16

6.18 PCI Conﬁguration Register Write 6-17

6.19 Operating Register/SCRIPTS RAM Read, 32 Bits 6-18

6.20 Operating Register/SCRIPTS RAM Read, 64 Bits 6-19

6.21 Operating Register/SCRIPTS RAM Read, 32 Bits 6-21

6.22 Operating Register/SCRIPTS RAM Write, 64 Bits 6-22

6.23 Nonburst Opcode Fetch, 32-Bit Address and Data 6-24

6.24 Burst Opcode Fetch, 32-Bit Address and Data 6-26

6.25 Back to Back Read, 32-Bit Address and Data 6-28

6.26 Back to Back Write, 32-Bit Address and Data 6-30

6.27 Burst Read, 32-Bit Address and Data 6-32

6.28 Burst Read, 64-Bit Address and Data 6-34

6.29 Burst Write, 32-Bit Address and Data 6-36

6.30 Burst Write, 64-Bit Address and Data 6-38

6.31 External Memory Read 6-41

6.32 External Memory Write 6-45

6.33 Normal/Fast Memory (≥ 128 Kbytes) Single Byte

Access Read Cycle 6-48

xvi

6.34 Normal/Fast Memory (≥ 128 Kbytes) Single Byte Access

Write Cycle 6-50

6.35 Slow Memory (≥ 128 Kbytes) Read Cycle 6-56

6.36 Slow Memory (≥ 128 Kbytes) Write Cycle 6-58

6.37 ≤ 64 Kbytes ROM Read Cycle 6-60

6.38 ≤ 64 Kbytes ROM Write Cycle 6-61

6.39 Initiator Asynchronous Send 6-62

6.40 Initiator Asynchronous Receive 6-63

6.41 Target Asynchronous Send 6-63

6.42 Target Asynchronous Receive 6-64

6.43 SCSI-1 Transfers (SE 5.0 Mbytes) 6-64

6.44 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or

20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-65

6.45 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or

40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-65

6.46 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or

80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-66

6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or

20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-67

6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or

40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-67

6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or

80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6-68

6.50 Ultra160 SCSI Transfers 160 Mbyte (16-Bit Transfers)

Quadrupled 40 MHz Clock 6-69

6.51 Alphanumeric List by Signal Name 6-74

6.52 Alphanumeric List by BGA Position 6-76

A.1 LSI53C1000R PCI Register Map A-1 A.2 LSI53C1000R SCSI Register Map A-3

xvii

xviii

Chapter 1 Introduction

This chapter provides a general overview on the LSI53C1000R PCI to Ultra160 SCSI Controller. This chapter contains the following sections:

• Section 1.1, “General Description”

• Section 1.2, “Beneﬁts of Ultra160 SCSI”

• Section 1.3, “Benefits of SURElink (Ultra160 SCSI Domain Validation)

Technology”

• Section 1.4, “Beneﬁts of LVDlink Technology”

• Section 1.5, “Beneﬁts of TolerANT® Technology”

• Section 1.6, “Summary of LSI53C1000R Beneﬁts”

1.1 General Description

The LSI53C1000R brings Ultra160 SCSI performance to host adapter, workstation, and server designs, making it easy to add a high-performance SCSI bus to any PCI system.

The LSI53C1000R supports a 64-bit or 32-bit, 66 or 33 MHz PCI bus. The Ultra160 SCSI features implemented in the LSI53C1000R are: double transition (DT) clocking, cyclic redundancy check (CRC), and domain validation. These features comply with the Ultra160 SCSI industry initiative.

DT clocking permits the LSI53C1000R to transfer data up to 160 Mbytes/s. CRC improves the integrity of the SCSI data transmission through enhanced detection of communication errors. Asynchronous Information Protection (AIP) augments CRC to protect all nondata phases, providing complete end-to-end protection of the SCSI I/O. SURElink™ domain validation technology detects the SCSI bus

LSI53C1000R PCI to Ultra160 SCSI Controller Technical Manual 1-1

conﬁguration and automatically tests and adjusts the SCSI transfer rate to optimize interoperability. Three levels of Domain Validation are provided, assuring robust system operation.

The LSI53C1000R has a local memory bus. This allows local storage of the device’s BIOS ROM in ﬂash memory or standard EPROMs. The LSI53C1000R supports programming of local ﬂash memory for BIOS updates. The chip is packaged in a 456 Ball Grid Array (BGA). Figure 1.1 shows a typical LSI53C1000R board application connected to external ROM or ﬂash memory.

Figure 1.1 Typical LSI53C1000R Board Application

68-Pin

SCSI

Connector

and

Terminator

Memory Control

Block

Flash ROM

Serial EEPROM

SCSI Data,

Parity, and

Control Signals

LSI53C1000R

64-Bit/66MHz

PCI to

Single Channel

Ultra160 SCSI

Controller

PCI Interface

PCI Address, Data, Parity

and Control Signals

Memory

Address/Data

Bus

GPIO/[1:0]

LVDlink™ technology is the LSI Logic implementation of Low Voltage Differential (LVD). LVDlink transceivers allow the LSI53C1000R to perform either Single-Ended (SE) or LVD transfers. The LSI53C1000R integrates a high-performance SCSI core, a 64-bit/66 MHz PCI bus master DMA core, and the SCSI SCRIPTS™ processor to meet the ﬂexibility requirements of Ultra160 SCSI standards. It implements multithreaded I/O algorithms with minimum processor intervention,

1-2 Introduction

solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. Figure 1.2 illustrates a typical LSI53C1000R system application.

Figure 1.2 Typical LSI53C1000R System Application

PCI Bus

Interface

Controller

Processor Bus

Central

Processing

Unit

(CPU)

PCI Bus

Typical PCI Computer

System Architecture

LSI53C1000R PCI

to Ultra160 SCSI

Controller

One PCI Bus Load

PCI Graphic Accelerator

PCI Fast Ethernet

Memory

Controller

Memory

SCSI Bus

Fixed Disk, Optical Disk,

Printer, Tape, and Other

SCSI Peripherals

The LSI53C1000R is pin compatible with the LSI53C1020 PCI to Ultra320 SCSI Controller. Proper board design, using LSI Logic

Design Considerations for the LSI53C1010R and LSI53C1030, SEN S11019, allows seamless, low risk upgrade from the Ultra160

LSI53C1000R to the Ultra320 LSI53C1020.

General Description 1-3

1.2 Beneﬁts of Ultra160 SCSI

Ultra160 SCSI delivers data up to two times faster than Ultra2 SCSI. Ultra160 SCSI is a subset of Ultra3 SCSI, which is an extension of the SPI-3 draft standard. When enabled, Ultra160 SCSI performs 80 megatransfers/s, resulting in approximately double the synchronous data transfer rates of Ultra2 SCSI. The LSI53C1000R performs 16-bit, Ultra160 SCSI synchronous data transfers as fast as 160 Mbytes/s. This advantage is most noticeable in heavily loaded systems, or large block size applications such as video on-demand and image processing.

The Ultra160 data transfer speed is accomplished using DT clocking. DT clocking refers to transferring data on both polarity edges of the request or acknowledge signals. Data is clocked on both rising and falling edges of the request and acknowledge signals. Double-edge clocking doubles data transfer speeds without increasing the clock rate.

Ultra160 SCSI also includes CRC, which offers higher levels of data reliability by ensuring complete integrity of transferred data. CRC is a 32-bit scheme, referred to as CRC-32. CRC is guaranteed to detect all single bit errors, any two bits in error, or any combination of errors within a single 32-bit range.

AIP is also supported by the LSI53C1000R, protecting all nondata phases, including command, status, and messages. CRC, along with AIP, provides end-to-end protection of the SCSI I/O.

SURElink domain validation provides 3 levels of integrity checking: Basic (level 1), Enhanced (level 2), and Margined (level 3). Further information on SURElink technology is available in Section 1.3, “Beneﬁts

of SURElink (Ultra160 SCSI Domain Validation) Technology.”

An advantage of Ultra160 SCSI is that it significantly improves SCSI bandwidth while preserving existing hardware and software investments. The primary software changes required are to enable the chip to perform synchronous negotiations for Ultra160 SCSI rates and to enable the clock quadrupler. Ultra160 SCSI uses the same connectors as Ultra SCSI and Ultra2 SCSI. Chapter 2, "Functional Description" contains more information on migrating an Ultra SCSI or Ultra2 SCSI design to an Ultra160 SCSI design.

1-4 Introduction

1.3 Beneﬁts of SURElink (Ultra160 SCSI Domain Validation) Technology

SURElink technology represents the very latest SCSI interconnect management solution. It ensures robust and low risk Ultra160 SCSI implementations by extending the Domain Validation guidelines documented in the ANSI T10 SPI-3 specifications. Domain Validation verifies that the system is capable of transferring data at Ultra160 speeds, allowing it to renegotiate to lower speed and bus width if necessary. SURElink technology is the software control for the manageability enhancements in the LSI53C1000R PCI to Ultra160 SCSI Controller. Fully integrated in the SDMS™ (Storage Device Management System) software solution, SURElink technology provides Domain V alidation at boot time as well as throughout system operation. SURElink technology extends to the Desktop Management Interface (DMI)-based System Management components of the SDMS software solution, providing the network administrator remote management capability.

SURElink domain validation provides three levels of integrity checking: Basic (level1), Enhanced (level2), and Margined (level3). The basic check consists of an inquiry command to detect gross problems. The enhanced check sends a known data pattern using the Read and Write Buffer commands to detect additional problems. Margined check verifies that the physical parameters have some degree of margin. By varying L VD drive strength and REQ/ACK timing characteristics, level 3 verifies that no errors occur on the transfers. These altered signals are only used during the diagnostic check and not during normal system operation. If errors occur with any of these checks, the system can drop back to a lower transmission speed, on a per-target basis, to ensure robust system operation.

1.4 Beneﬁts of LVDlink Technology

The LSI53C1000R supports LVD through LVDlink technology. This signaling technology increases the reliability of SCSI data transfers over longer distances than are supported by SE SCSI. The low current output of LVD allows the I/O transceivers to be integrated directly onto the chip. LVD provides the reliability of High Voltage Differential (HVD) SCSI without the added cost of external differential transceivers. Ultra160 SCSI with LVD

Beneﬁts of SURElink (Ultra160 SCSI Domain Validation) Technology 1-5

allows a longer SCSI cable and more devices on the bus, with the same cables defined in the SCSI-3 Parallel Interface standard for Ultra SCSI. LVD provides a long-term migration path to even faster SCSI transfer rates without compromising signal integrity, cable length, or connectivity.

For backward compatibility to existing SE devices, the LSI53C1000R features universal LVDlink transceivers that support LVD SCSI and SE SCSI. This allows use of the LSI53C1000R in both legacy and Ultra160 SCSI applications.

1.5 Beneﬁts of TolerANT®Technology

The LSI53C1000R features TolerANT technology, which includes active negation on the SCSI drivers and input signal ﬁltering on the SCSI receivers. Active negation causes the SCSI Request, Acknowledge, Data, and Parity signals to be actively driven HIGH rather than passively pulled up by terminators.

TolerANT receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. TolerANT receivers ﬁlter the SCSI bus signals to eliminate unwanted transitions, without the long signal delay associated with RC-type input ﬁlters. This improved driver and receiver technology helps eliminate double clocking of data, which is the single biggest reliability issue with SCSI operations. TolerANT input signal ﬁltering is a built-in feature of the LSI53C1000R and all LSI Logic Fast, Ultra, Ultra2, and Ultra160 SCSI devices.

The beneﬁts of TolerANT technology include increased noise immunity when the signal transitions to HIGH, better performance due to balanced duty cycles, and improved fast SCSI transfer rates. In addition, TolerANT SCSI devices do not cause glitches on the SCSI bus at power-up or power-down. This protects other devices on the bus from data corruption. When used with the LVDlink transceivers, TolerANT technology provides excellent signal quality and data reliability in real world cabling environments. TolerANTtechnology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute.

1-6 Introduction

1.6 Summary of LSI53C1000R Beneﬁts

This section provides a summary of the LSI53C1000R features and beneﬁts. It contains information on SCSI Performance, PCI Performance, Integration, Ease of Use, Flexibility, Reliability, and Testability.

1.6.1 SCSI Performance

The LSI53C1000R:

• Performs wide, Ultra160 SCSI synchronous data transfers as fast as

160 Mbytes/s using DT clocking.

• Supports CRC checking and generation in DT phases.

• Protects nondata phases with AIP.

• Supports Domain Validation:

– Basic (Level 1) – Enhanced (Level 2) – Margined (Level 3)

• Includes integrated LVDlink universal transceivers:

– Supports SE and LVD signals. – Allows greater device connectivity and longer cable length. – LVDlink transceivers save the cost of external differential

transceivers.

– Supports a long-term performance migration path.

• Bursts of up to 512 bytes across the PCI bus with an independent

896–920 byte FIFO.

• Handles phase mismatches in SCRIPTS without interrupting the

system processor.

• Includes an on-chip SCSI clock quadrupler that allows the chip to

achieve Ultra160 SCSI transfer rates with an input frequency of 40 MHz.

• Includes 8 Kbytes of internal RAM for SCRIPTS instruction storage.

• Supports 31 levels of SCSI synchronous offset in the

Single Transition (ST) mode and 62 levels in the DT mode.

Summary of LSI53C1000R Beneﬁts 1-7

• Supports variable block size and scatter/gather data transfers.

• Performs sustained Memory-to-Memory DMA transfers to

approximately 100 Mbytes/s.

• Minimizes the SCSI I/O start latency.

• Performs complex bus sequences without interrupts, including

restoring data pointers.

• Reduces Interrupt Service Routine (ISR) overhead through a unique

interrupt status reporting method.

• Includes SCSI Interrupt Steering Logic (SISL) for RAID Ready SCSI

on mainboard applications with a separate interrupt for routing to a RAID adapter.

• Supports Load/Store SCRIPTS instructions to increase the

performance of data transfers to and from the chip registers without using PCI cycles.

• Includes SCRIPTS support of 64-bit addressing.

• Supports target disconnect and later reconnect with no interrupt to

the system processor.

• Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast

I/O context switching.

• Supports expanded Register Move instructions to support additional

arithmetic capability.

1.6.2 PCI Performance

The LSI53C1000R:

• Complies with PCI 2.2 speciﬁcation.

• Supports a 64-bit/66 MHz PCI interface for 528 Mbytes/s bandwidth

that: – Can function in a 32-bit or 64-bit PCI slot – Operates at 33 or 66 MHz – Supports dual address cycle (DAC) generation for all SCRIPTS

• Bursts 4/8, 8/16, 16/32, 32/64, or 64/128 Qword/Dword transfers

across the PCI bus.

• Supports 32-bit or 64-bit word data bursts with variable burst lengths.

1-8 Introduction

1.6.3 Integration

• Prefetches up to 8 Dwords of SCRIPTS instructions.

• Bursts SCRIPTS opcode fetches across the PCI bus.

• Performs zero wait-state bus master data bursts up to 528 Mbytes/s

(@ 66 MHz).

• Supports PCI Cache Line Size (CLS) register.

• Supports PCI Write and Invalidate, Read Line, and Read Multiple

commands.

• Complies with PCI Bus Power Management Speciﬁcation Rev 1.1.

• Complies with PC99.

The following features ease integration of the LSI53C1000R into a system.

• Ultra160 SCSI PCI Controller.

• Integrated LVD transceivers.

• Full 32-bit or 64-bit PCI DMA bus master.

• Memory-to-Memory Move instructions allow use as a third-party PCI

bus DMA controller.

• Integrated SCRIPTS processor.

• Pin to pin compatible with the LSI53C1020 and subsequent chips.

1.6.4 Ease of Use

The following features of the LSI53C1000R make the device user friendly.

• The LSI53C1000R is pin compatible with the LSI53C1020.

• Up to 1 Mbyte of add-in memory support for BIOS and SCRIPTS

• Reduced SCSI development effort.

• Compiler-compatible with existing LSI53C7XX and LSI53C8XX

• Direct connection to PCI and SCSI SE and LVD.

• Development tools and sample SCSI SCRIPTS available.

Summary of LSI53C1000R Beneﬁts 1-9

storage.

family SCRIPTS.

1.6.5 Flexibility

• Maskable and pollable interrupts.

• Wide SCSI, A or P cable, and up to 15 devices are supported.

• Three programmable SCSI timers: Select/Reselect,

Handshake-to-Handshake, and General Purpose.

• Software for PC-based operating system support.

• Support for relative jumps.

• SCSI Selected As ID bits for responding with multiple IDs.

The following features increase the ﬂexibility of the LSI53C1000R:

• Universal LVD transceivers are backward compatible with SE devices.

• High level programming interface (SCSI SCRIPTS).

• Programs local and bus ﬂash memory.

• Tailored SCSI sequences execute from main system RAM or internal

SCRIPTS RAM.

• Flexible programming interface to tune I/O performance or to adapt

to unique SCSI devices.

• Support for changes in the logical I/O interface deﬁnition.

• Low level access to all registers and all SCSI bus signals.

• Fetch, Master, and Memory Access control pins.

• Separate SCSI and system clocks.

• SCSI clock quadrupler bits enable Ultra160 SCSI transfer rates with

a 40 MHz SCSI clock input.

• Selectable INT pin disable bit.

• Compatible with 3.3 V and 5 V PCI.

• Easy migration to LSI53C1020 and subsequent chips.

1-10 Introduction

1.6.6 Reliability

The following features enhance the reliability of the LSI53C1000R:

• CRC and AIP provide end-to-end SCSI I/O protection.

• 2 kV ESD protection on SCSI signals.

• Protection against bus reﬂections due to impedance mismatches.

• Controlled bus assertion times (reduces RFI, improves reliability, and

eases FCC certiﬁcation).

• Latch-up protection greater than 150 mA.

• Voltage feed-through protection (minimum leakage current through

SCSI pads).

• A high proportion of pins are power and ground.

• Power and ground isolation of I/O pads and internal chip logic.

• TolerANT technology provides:

– Active negation of SCSI Data, Parity, Request, and Acknowledge

signals for improved fast SCSI transfer rates.

– Input signal ﬁltering on SCSI receivers improves data integrity,

even in noisy cabling environments.

1.6.7 Testability

The following features enhance the testability of the LSI53C1000R:

• All SCSI signals accessible through programmed I/O.

• SCSI bus signal continuity checking.

• Support for single-step mode operation.

• JTAG boundary scan.

Summary of LSI53C1000R Beneﬁts 1-11

1-12 Introduction

+ 358 hidden pages

Avago Technologies LSI53C1000R User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 General Description

1.6.1 SCSI Performance

1.6.2 PCI Performance

1.6.3 Integration

1.6.4 Ease of Use

1.6.5 Flexibility

1.6.6 Reliability

1.6.7 Testability