Avago Technologies ACPL-P347-000E User Manual

ACPL-P349, ACPL-W349

Isolated IGBT or SiC/GaN MOSFET Gate Driver Evaluation Board

User Manual

Quick-Start

This manual outlines the features of the ACPL-P349/W349 Evaluation Board and the conguration required for evaluat­ing Isolated IGBT or SiC/GaN MOSFET Gate Drivers. Visual inspection is required to ensure that the evaluation board is
received in good condition.

Default connections of the evaluation board are described below (refer to Figure 1):

1. Q1 and Q2 are not mounted. Either an IGBT or SiC/GaN MOSFET can be mounted at either Q1 (for TO-220 package)
or Q2 (for TO-247 package) or connected to the driver board through short wire connections from the holes provided
at Q1 or Q2;

2. D4 and R7 are not mounted (on solder side). A 15V zener footprint at D4 is provided to allow for a single DC power
supply of 15V~30V to be applied across Vcc2 and Vee if needed. A virtual ground Ve (at source pin of Q1 or Q2) can
then be generated and it acts as the reference point at the source pin of each SiC/GaN MOSFET (or emitter pin of each
IGBT). Vcc2 will then stay at 15V above the virtual ground Ve. R7 is needed to generate the bias current across D4;

3. S2 & S3 jumpers are shorted by default to connect Ve to Vee, assuming that a negative supply is not needed.
Note: If negative supply is needed, S2 & S3 jumpers need to be removed;

4. Bootstrap Diode D3b and Resistor R6 are connected by default. These 2 components are provided to help generate
Vcc2b supply through bootstrapping assuming that Vcc2a supply is available.

Note: Bootstrapping supply works only when Q1 or Q2 are mounted in a half bridge conguration and turned on and o
through proper PWM driving signals;

5. S1 is shorted by default to ground the IN- (or LED-, the cathode of LED) pin when Vcc1 is supplied. This short can be
removed if IN- cannot be grounded;

6. Upper and lower arms of the inverter will have common Vcc1 (& Gnd1), a provision is made to allow Vcc1 to be
connected by solder between upper and lower inverter PCB portions (and Gnd1 on the solder side);

7. Provisions are also made to allow Vcc2 (& Vee) to be generated from Vcc1 through a DC/DC converter at IC2. When
this DC/DC converter is used, S2, S3 (& R6) should be disconnected;

Vcc1b

Vcc1a

Vcc1a & Vcc1b(shorted)

Gnda & Gndb on solder side(also shorted)

S1(shorted) S2(shorted) S3 on solder side(also shorted)

Figure 1. ACPL-P349/W349 Evaluation board showing default connections

Note: All part references are designated with sux ‘a’ and ‘b’ to indicate lower and upper inverter arms respectively. If part references are made without
suxes, then they are valid for both upper and lower inverter arms (except R6, which is shared).

R6 mounted(soldered)

Once inspection is performed, the evaluation board can be used to test either one of the top and bottom half bridge
inverter arms in simulation mode without the need for a IGBT or SiC/GaN MOSFET. To perform testing simply follow the
ve steps as outlined below (See Figure 2).

Testing both Arms of The Half Bridge Inverter Driver (without IGBT or SiC/GaN MOSFET)

1. Solder a 10nF capacitor across Gate and Emitter/Collector terminals of Q1 or Q2 (to simulate actual gate capacitance
of IGBT or SiC/GaN MOSFET)

2. Connect a +5V DC supply (DC supply 1) across +5V and GND terminals of CON1

3. Connect another DC supply (DC supply 2 with voltage range from 15V~30V) across Vcc2 (pin-7 of IC2) and Vee (pin-5
of IC2) terminals of IC2a respectively. This can be non-isolated for testing purposes

4. Connect drive signals;

a) A 10kHz 5V DC pulse (at slightly <50% duty) from a dual output signal generator across IN1+ & IN1- pins of CON1a

to simulate microcontroller output to drive lower arm of the half bridge Inverter

b) Another 10kHz 5V DC pulse (at 180° out of phase to 4a) from the dual output signal generator across IN2+ & IN2-

pins of CON1b to simulate microcontroller output to drive upper arm of the half bridge Inverter

5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points;

a. LED signal at IN1+ pin with reference to GND
b. LED signal at IN2+ pin with reference to GND

Note: Vcc2b supply of voltage close to Vcc2a should then be successfully generated through the built-in bootstrap components D3b and R6.

c. Vga representing the output voltage of ACPL-P349/W349 (IC1a) at Gate pin of Q1a (or Q2a) with reference to Vea
d. Vgb (through an isolated probe) representing the output voltage of ACPL-P349/W349 (IC1b) at Gate pin of Q1b (or

Q2b) with reference to Veb

In2 -

In2+

4b

5b

Signal Input

-

In1

In1+

4a

5a

Signal Input

DC Supply1

2

+5V

Gnd

Figure 2. Simulation Test Setup of Evaluation Board

+-

Vcc2b

3

15~30V

DC Supply2

5d

10nF

1

Veb

5c

10nF

1

Vea

+-

2

Schematics

Evaluation Board Schematics are shown in Figure 3.

LEDb +

LEDb -

Vcc1b

Gndb

LEDa +

LEDa -

Vcc1a

Gnda

CON1b

CON1a

S1b

S1a

R1b

220R

R2b

150R

R1a

220R

R2a

150R

NM
R3b

NM
R3a

IC1b

1

3

1

2

1

3

1

2

ACPL-W349

IC2b

NM

IC1a

ACPL-W349

IC2a

R05P15D/R8

6

0.1µF

5

4

7

6

5

6

0.1µF

5

4

7

6

5

C1b

VEEb

TP2b

TP3b

TP4b

C1a

VEEa

TP2a

TP3a

TP4a

Vcc2b

Vcc2a

TP1a

TP1b

R5b
NM

Vcc2b

C2b

10µF Ta

C3b

10µF Ta

R5a
NM

Vcc2a

C2a
10µF Ta

C3a
10µF Ta

VEEb

VEEa

R4b

4R7 1W

R4a

4R7 1W

S3a

S3b

R7b

NM

SS32

D1b

S2b

BYM26F

R7a

NM

SS32

D1a

S2a

BYM26F

D3b

D3a

D4b

NM

D2b

SMBJ11CA

D4a

NM

D2a

SMBJ11CA

G

R6

4R7 1W

G

D

S

VEb

D

S

VEa

NM

TO220/TO247

Q1b/Q2b

NM

TO220/TO247

Q1a/Q2a

Figure 3. ACPL-P349/W349 Evaluation Board Schematics

3