Avago Technologies ACPL-P345-000E User Manual

ACPL-P346/W346

Isolated Power MOSFET Gate Driver Evaluation Board

User's Manual

Quick Start

Visual inspection is needed to ensure that the evaluation board is received in good condition.

All part references are designated with sux ‘a’ and ‘b’ to indicate the lower and the upper inverter arms, respectively. If
part references are made without suxes, then they are valid for both upper and lower inverter arms (except R6, which
is shared).

Figure 1 shows the default connections of the evaluation board:

1. Q1 and Q2 are not mounted. Actual Power MOSFET can be mounted at either Q1 (for TO-220 package) or Q2 (for TO­247 package) or connected to the driver board through short wire connections from the holes provided at Q1 or Q2.

2. D4 and R7 are not mounted (on solder side). A 12 V Zener diode footprint at D4 is provided to allow for a single DC
power supply of 15 V ~25 V to be applied across V
Q2) can then be generated and it acts as the reference point at the source pin of each power MOSFET. V
stay at 12 V above the virtual ground VE. R7 is needed to generate the bias current across D4.

3. S2 and S3 jumpers are shorted by default to connect VE to VEE, assuming that a negative supply is not needed. Note:
If a negative supply is needed, then S2 and S3 jumpers must be removed.

4. Bootstrap diode D3b and resistor R6 are connected by default. These two components are provided to help generate
V

supply through bootstrapping assuming that V

CC2b

only when Q1 or Q2 are mounted in a half-bridge conguration and turned on and o through proper PWM driving
signals.

5. S1 is shorted by default to ground the IN- (or LED-, the cathode of LED) pin when V
removed if IN- cannot be grounded.

6. Upper and lower arms of the inverter will have common V
connected by solder between upper and lower inverter PCB portions (and GND1 on the solder side).

7. Provisions are also made to allow V

(and VEE) to be generated from V

CC2

this DC/DC converter is used, S2, S3 (and R6) should be disconnected.

and VEE if needed. A virtual ground VE (at Source pin of Q1 or

CC2

will then

CC2

supply is available. Note: Bootstrapping supply works

CC2a

is supplied. This short can be

CC1

(and GND1), a provision is made to allow V

CC1

through a DC/DC converter at IC2. When

CC1

CC1

to be

V

CC1b

V

CC1a

VCC1a and VCC1b (shorted)

GNDa and GNDb on solder side (also shorted)

S1 (shorted)

Figure 1. Actual ACPL-P346/W346 evaluation board showing default connections

S2 (shorted)

R6 mounted (shorted)

S3 on solder side (also shorted)

Once inspection is done, the evaluation board can be powered up in ve simple steps. Figure 2 shows you how to test
the top or the bottom half-bridge inverter arms in simulation mode without the need for an actual power MOSFET.

Testing both arms of the half-bridge inverter driver (without a power MOSFET)

1. Solder a 10 nF capacitor across the gate and emitter terminals of Q1 or Q2. This is to simulate actual gate capacitance
of a power MOSFET.

2. Connect a +5 V DC supply (DC supply 1) across the +5V and GND terminals of CON1.

3. Connect another DC supply (DC Supply 2 with voltage range from 12 V ~ 20 V) across V
5 of IC2) terminals of IC2a, respectively. This can be non-isolated for testing purposes.

4. Connect drive signals:

a. A 10 kHz 5 V DC pulse (at slightly < 50% duty) from a dual-output signal generator across IN1+ and IN1- pins of

CON1a to simulate microcontroller output to drive the lower arm of the half-bridge Inverter.

b. Another 10 kHz 5V DC pulse (at 180° out of phase to the signal in 4a) from the dual-output signal generator across

IN2+ and IN2- pins of CON1b to simulate microcontroller output to drive the upper arm of the half-bridge inverter.

5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points:

a. LED signal at the IN1+ pin with reference to (w.r.t.) GND.

b. LED signal at the IN2+ pin w.r.t. GND.

Note: The V

components D3b and R6.

supply of voltage close to V

CC2b

should then be successfully generated through the built-in bootstrap

CC2a

c. VGa representing the output voltage of ACPL-P346/W346 (IC1a) at the gate pin of Q1a (or Q2a) w.r.t. VEa.

d. VGb (through an isolated probe) representing the output voltage of ACPL-P346/W346 (IC1b) at the gate pin of Q1b

(or Q2b) w.r.t. VEB.

(pin 7 of IC2) and VEE (pin

CC2

In2-

In2+

4b

5b

Signal Input

+-

V

CC2b

3

12~20 V

DC Supply 2

+-

4a

5a

In1-

In1+

Signal Input

DC Supply 1

2

+5V

Gnd

Figure 2. Simple Simulation Test Setup of Evaluation Board

10nF

10nF

5d

1

V

Eb

5c

1

V

Ea

2

Schematics

Figure 3 shows the schematics of the evaluation board:

IC1b

ACPL-P346

IC2b

LEDb+

LEDb-

V

CC1b

CON1b

S1b

R1b

249R

R2b

130R

NM
R3b

1

3

1

NM

GNDb

LEDa+

LEDa-

V

CC1a

GNDa

CON1a

S1a

R1a

249R

R2a

130R

NM
R3a

2

IC1a

1

3

1

2

ACPL-P346

IC2a

R05P212D/R8

6

C1b

0.1µF

5

4

V

7

6

5

6

C1a

0.1 µF

5

4

V

TP2a

7

TP3a

6

TP4a

5

EEb

TP2b

TP3b

TP4b

EEa

V

CC2b

D4b

R7b

NM

R4b

TP1b

4R7 1W

R5b
NM

V

CC2b

C2b

10 µF T

C3b

10 µF T

V

EEb

V

CC2a

TP1a

R5a
NM

V

CC2a

C2a
10µF T

C3a
10µF T

V

EEa

SS32

D1b

BYM26F

S3b

a

a

R7a

NM

R4a

4R7 1W

SS32

D1a

S2a

BYM26F

S3a

a

a

S2b

SMBJ11CA

D3b

SMBJ11CA

D3a

NM

D4a

NM

D2b

D2a

G

R6

4R7 1W

G

D

S

V

Eb

D

S

V

Ea

NM

TO220/TO247

Q1b/Q2b

NM

TO220/TO247

Q1a/Q2a

Figure 3. Schematics of ACPL-P346/W346 evaluation board

3