ACPL-H342/K342 Gate Drive Evaluation Board
2.5 Amp Gate Drive Optocoupler with Active Miller Clamp,
Rail-to-Rail Output and UVLO in Stretched SO8
User’s Guide
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Product Description
The ACPL-H342/K342 is a 2.5A output current gate drive
optocoupler with features like active Miller clamp, rail-torail output and anti-cross conduction timing that helps to
simplify IGBT gate drive design without compromising on
eciency and reliability.
ACPL-H342/K342 is ideally suited for driving IGBTs and
power MOSFETs used in motor control and renewable
energy inverter applications. The voltage and current
supplied by these optocouplers make them suitable for
direct driving of IGBTs with ratings up to 1200 V and 150 A.
ACPL-K342 has an insulation voltage of V
It is also immune to common-mode voltage transients as
high as 1.5 kV and as fast as 40 kV/Ps.
IORM
= 1140 V
PEAK
Applications
x Isolated IGBT/MOSFET Gate Drive
x AC and Brushless DC Motor Drives
x Industrial Inverters
x Renewable Energy Inverters
x Uninterruptible Power Supplies (UPS)
About Evaluation Board
The ACPL-H342/K342 evaluation board allows a powerinverter designer to easily test the Miller clamp and
rail-to-rail capability of the ACPL-H342/K342 gate drive
optocoupler. The evaluation board includes two separate
gate drive channels (one optocoupler per channel) making
it a half-bridge topology for driving directly the gates of
high-side and low-side IGBTs of a power inverter (such as
single-phase motor inverter or one phase of a 3-phase
motor inverter).
Features of the evaluation board as listed:
.
x
Half-Bridge topology
x Footprints for bootstrap power supply conguration
x Works for IGBT TO-220 / TO-247 type
x Able to evaluate active Miller clamp and rail-to-rail
performance
x Footprints for
connections to motor
x Example of good bypass capacitors
The schematic diagram of the evaluation board can be
found in Figure 1 and 2. The top view of evaluation board
is in
Figure 3.
PCB mounting terminal blocks for wire
layout
TP_ANODE_T
11
R1
170 :
1
2
2
3
4
1
R2
170 :
U1
Anode
NC
Cathode
NC
ACPL-H342/K342
Vcc
Vout
Vclamp
VEE
Dbs
1 2
NM
8
12
12
EC1
NM
12
Cbs
NM
1 PF
C1
50 V
7
6
5
R3
1 21
NM
R4
1 2
NM
Rbs
1 2
NM
D1
2
SS32
ZD1
ZD2
1
22
2P_HEADER
1
2
J5
3P_TO220
1
2
3
J1
NM
G1
C1
E1
1
3P_TO247
J2
1
2
3
NM
1
1
1
2
3
VCC_T
TP_CLAMP_T
TP_OUT_T
3P_HEADER
J3
TP_G1
TP_C1
NM
TP_E1
12
TP_CATHODE_T
Figure 1. Schematic Diagram for ACPL-H342/K342 Evaluation Board – Top
TP_ANODE_B
112
R5
170 :
1
Anode
2
NC
3
Cathode
4 5
NC VEE
1
R6
170 :
12
TP_CATHODE_B
Figure 2. Schematic Diagram for ACPL-H342/K342 Evaluation Board – Bottom
U2
Vclamp
ACPL-H342/K342
Vcc
Vout
8
12
C2
7
6
50 V
EC2
NM
12
1 PF
1 21
1 2
R7
NM
R8
NM
D2
SS32
ZD3
ZD4
1
2P_HEADER
1
2
J4
2P_HEADER
1
2
J10
1
22
1
3P_TO220
1
2
3
NM
2P_HEADER
1
2
J9
J6
G2
C2
E2
2
3P_TO247
J7
1
2
3
NM
1
1
1
1
1
1
1
TP_E1_T
TP_VEE_T
VCC_B
TP_CLAMP_B
TP_OUT_B
3P_HEADER
J8
1
2
3
NM
TP_E2_B
TP_VEE_B
TP_G2
TP_C2
TP_E2
CAUTION: When operating the board connected to a half-bridge dual IGBT (with the dual IGBT connected to high-voltage
rails) never short the output ground planes and scope ground together!! Also when probing points on the upper gate-drive
channel use a scope with adequate voltage rating!
2
Split Resistors
Input LED Driver
ACPL-H342/K342
Top Gate Driver
Isolation
Barrier
Bypass Cap
C1 and C2
Bootstrap Capacitor,
Resistor and Diode
IGBT TO-220/247
type package
PCB Mounting
Terminal Blocks
J3 and J8
Gate Resistors
R3, R4, R7 and R8
ACPL-H342/K342
Bottom Gate Driver
Figure 3. Top Layer View
Active Miller Clamp
Jumpers J5 and J10
Negative Power Supply
Jumpers J4 and J9
Test Connection and Operation
The denotations or symbols used below refer to High Side, the top gate driver (U1) operation. If operating in a halfbridge topology, please refer to the bottom gate driver’s (U2) denotations or symbols in schematic diagram, Figure 2.
ACPL-H342/K342 Input Side:
1. LED input current: ACPL-H342/K342 has a LED input gate control. Split resistors network R1 and R2, each with a value of
170 : are used to achieve high CMR response. Connecting “TP_ANODE_T” and “TP_CATHODE_T” to a 5 V input pulse
signal will drive a recommended LED current of 10 mA.
ACPLH342/K342 Output Side:
1. Output positive power supply: Connect the +15 V of an isolated DC power supply to “VCC_T” and the common to “TP_
E1_T” test points. “TP_E1_T” is connected to the IGBT emitter.
2.
Output negative power supply (optional): If only single positive output power supply is required, short the open
connection J4. For negative output power supply, connect the -15 V of the isolated DC power supply to “TP_VEE_T”
and the common to “TP_E1_T” test points. Remove any short circuit connection on J4 and replace J4 with appropriate
bypass capacitors.
3.
Output positive bootstrap power supply (optional for Top, High side only): For single positive output power supply, short
the open connection J4. Connect the +15 V power supply of the Bottom side, “VCC_B” to the Top side “VCC_T”. To
complete the bootstrap power supply, solder appropriate bootstrap resistor “Rbs”, diode “Dbs” and Capacitor “Cbs”.
4.
Gate resistors: Solder appropriate R3 for IGBT gate discharging and R4 for IGBT gate charging.
Active Miller Clamp: If Miller clamp feature is required. Short the open connection J5. If Miller clamp feature is not
5.
required, remove any short circuit connection on J5. It is also recommended to connect the oating Miller clamp pin
to VEE by shorting “TP_CLAMP_T” to “ TP_VEE_T” when not in used.
6.
Output: Monitor the output or the gate of IGBT by connecting an oscilloscope between “TP_OUT_T” to “TP_E1_T”.
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Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved.
AV02-2653EN - September 24, 2010
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