Avago Technologies ACPL-339J-000E User Manual
ACPL-339J
Isolated Gate Driver Evaluation Board
User’s Manual
Quick-Start
Visual inspection is needed to ensure that the evaluation board is received in good condition. The default connections
of the evaluation board are as follows:
1. A 15 V Zener diode at D1 is provided to allow for a single DC power supply of 21.6 V ~ 30 V to be applied across V
and Vee. A virtual ground Ve (at COM pin of CON2) will be generated, and it acts as the reference point at the emitter
of each IGBT. V
D1.
2. Actual IGBT can be mounted at either Q5 (for TO-220 package) or Q6 (for TO-247 package) or connected to the driver
board through short wire connections from the holes provided at Q5 or Q6.
3. S2 jumper is shorted by default to allow for the driver board to be tested without actual IGBT connection at Q5 or Q6.
Note: Once IGBT is connected at either the Q5 or Q6 location, this S2 jumper must be removed to allow for IGBT Desat
protection to be activated.
4. J1 is shorted by default, assuming that a Desat detection voltage of 8 V is needed. To reduce the Desat detection
voltage by another 1 V, this jumper can be replaced by another piece of D3 diode (BYM26E). To further reduce the
Desat detection voltage, higher VF voltage diodes can be selected to replace both D3 and J1, plus the use of higher
resistance for R4.
5. S1 is shorted by default to ground the IN1– signal. This short can be removed if IN1– cannot be grounded.
Once inspection is done, the evaluation board can be powered up in ve simple steps (see Figure 1), to test either one of
the top and bottom half bridge inverter arms in simulation mode without the need of actual IGBT (or Power MOSFET).
will then stay at 15 V above the virtual ground Ve. R11 is needed to provide the bias current across
cc2
cc2
Testing Either Arm of The Half Bridge Inverter Driver (without IGBT)
1. Solder a 10 nF capacitor across gate and emitter terminals of Q5 (to simulate actual gate capacitance of IGBT/power
MOSFET).
2. Connect a +5 V DC supply (DC supply 1) across +5 V and GND terminals of CON1.
3. Connect another DC supply (DC Supply 2 with voltage range from 21.6 V ~ 30 V) across V
-15 V) terminals of CON2. This can be non-isolated for testing purpose.
4. Supply a 10 kHz 5 V DC pulse (at 50% duty) from a signal generator across IN1+ & IN1– pins of CON1 to simulate
microcontroller output to drive either arm of the half bridge Inverter.
5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points:
a. LED signal at IN1+ pin with reference to (w.r.t.) GND.
b. Fault output for any fault signal appearing at FAULT pin w.r.t. GND.
c. V
d. V
e. V
f. V
g. VgIGBT for the gate driving voltage of Q5/Q6 Gate w.r.t. Ve.
Note: A DESAT fault can be simulated by removing the S2 Jumper.
for the negative output voltage of ACPL-339J at U1 pin 11 w.r.t. Ve (COM pin).
outn
for the positive output voltage of ACPL-339J at U1 pin 12 w.r.t. Ve.
outp
for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. Ve.
gmos
for the DESAT voltage of Q5/Q6 Collector w.r.t. Ve.
desat
(+15V) and Vee (-6.6 V ~
cc2
GND
+5V
DC Supply 1
2
5a
IN1+
Signa l Input
IN1–
4
5b
Figure 1. Simple Simulation Test Setup of Evaluation Board
Schematics
5f
5g
10 nF
5d
5c
1
5e
3
21.6 V ~ 30 V
DC Supply 2
Figure 2 shows the schematics of the Evaluation Board.
CON1
+5V
IN1+
IN1-
FAULT
GND
Figure 2. Schematics of ACPL-339J Evaluation Board
GND
Vcc1
1
NC
2
C1
220p
270
R1
R2
270
C2
S1
220p
C3
Vcc1
330n
10k
R3
CATHODE
3
ANODE
4
CATHODE
5
V
GND1
6
V
CC1
7
FAULT
8
C4
V
1n
GND1
IC1
ACPL-339J
DESAT
V
GMOS
V
V
V
OUTN
V
V
CC2
OUTP
LED
V
16
E
15
14
13
12
11
10
9
EE
Vcc2
VEE
CON2
15V
BZG03C15TR3
1µ
C5
Tant
+
20V
1µ Tant
20V
+
C7
+
10µ
Tant
C6
35V
D2
DFLS220L
C8
100p
15 (½W)
15 (½W)
R4
100
Si7465DP
R5
R6
Si7848BDP
BYM26E
J1
D3
470
R9
Q1
R7//R7a
10R (½W)
10R (½W)
10R (½W)
10R (½W)
R8 //R8a
Q2
S2
R10
330
Q3
Caution: Please
remove S2
jumpers if
IGBT/Power
Mosfet is
connected to
Q5 (or Q6)
Si2318
1k (½W)
R11
D1
VE
VCC2
21.6V~30V
VEE
G
NM
IGBT (or
VE
Power Mosfet)
(TO-220 & TO-247)
VEE
VE
C
Q5
C
Q6
G
NM
E
E
2
Practical Connections of the Evaluation Board Using IGBT/Power MOSFET for Actual Inverter Test
1. Solder actual IGBTs/Power MOSFETs at Q5 (or Q6) for the top and bottom arms of the Half Bridge Inverter Isolated
Drivers.
2. Connect a +5 V DC isolated supply 1 across +5 V and GND terminals of CON1 for both arms of the Isolated Drivers.
3. Connect another isolated DC supply 2 (voltage range from 21.6 V ~ 30 V) across V
arm.
4. Connect another isolated DC supply 3 (voltage range from 21.6 V ~ 30 V) across V
bottom arm.
5. Connect the signal output (meant to drive the top arm of half-bridge Inverter) from the microcontroller to Signal
Input 1 across pin IN1+ and IN1– of CON1 w.r.t. GND of Top Inverter Arm Isolated Driver.
6. Connect the signal output (meant to drive the bottom arm of half-bridge Inverter) from the microcontroller to Signal
Input 2 across pin IN1+ and IN1– of CON1 w.r.t. GND of Bottom Inverter Arm Isolated Driver.
7. Use a multi-channel Digital Oscilloscope to capture the waveforms at these points:
a. LED signal at IN1+ pin with reference to (w.r.t.) GND for Top Arm
b. LED signal at IN1+ pin w.r.t. GND for Bottom Arm
c. Fault output for any fault signal appearing at FAULT1 w.r.t. GND
d. Fault output for any fault signal appearing at FAULT2 w.r.t. GND
e. V
for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. Ve of Top Inverter Arm (dierential probe
gmos
needed)
f. V
for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. Ve of Bottom Inverter Arm (dierential probe
gmos
needed)
g. V
h. V
i. V
j. V
for the DESAT voltage of Q5 (or Q6) w.r.t. Ve of Top Inverter Arm (dierential probe needed)
desat
for the DESAT voltage of Q5 (or Q6) w.r.t. Ve of Bottom Inverter Arm (dierential probe needed)
desat
for the gate driving voltage of Q5/Q6 w.r.t. Ve of Top Inverter Arm (dierential probe needed)
gIGBT
for the gate driving voltage of Q5/Q6 w.r.t. Ve of Bottom Inverter Arm (dierential probe needed)
gIGBT
8. Connect the high voltage cable from Top Arm IGBT Emitter pin to the Bottom Arm IGBT Collector pin and then to the
Inverter load.
9. Connect the high voltage cables from Top Arm IGBT Collector to HVDC+ and from Bottom Arm IGBT Emitter to HVDC–
respectively as shown.
Note:
To protect the Inverter and its driver circuitries, it is recommended that you enable the current limiting function of the HV supply supplying the
High Voltage DC Bus during this test.
and Vee terminals of CON2 for top
cc2
and Vee terminals of CON2 for
cc2
3
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