Avago Technologies ACPL-339J-000E User Manual

ACPL-339J

Isolated Gate Driver Evaluation Board

User’s Manual

Quick-Start

Visual inspection is needed to ensure that the evaluation board is received in good condition. The default connections
of the evaluation board are as follows:

1. A 15 V Zener diode at D1 is provided to allow for a single DC power supply of 21.6 V ~ 30 V to be applied across V
and Vee. A virtual ground Ve (at COM pin of CON2) will be generated, and it acts as the reference point at the emitter
of each IGBT. V
D1.

2. Actual IGBT can be mounted at either Q5 (for TO-220 package) or Q6 (for TO-247 package) or connected to the driver
board through short wire connections from the holes provided at Q5 or Q6.

3. S2 jumper is shorted by default to allow for the driver board to be tested without actual IGBT connection at Q5 or Q6.
Note: Once IGBT is connected at either the Q5 or Q6 location, this S2 jumper must be removed to allow for IGBT Desat
protection to be activated.

4. J1 is shorted by default, assuming that a Desat detection voltage of 8 V is needed. To reduce the Desat detection
voltage by another 1 V, this jumper can be replaced by another piece of D3 diode (BYM26E). To further reduce the
Desat detection voltage, higher VF voltage diodes can be selected to replace both D3 and J1, plus the use of higher
resistance for R4.

5. S1 is shorted by default to ground the IN1– signal. This short can be removed if IN1– cannot be grounded.

Once inspection is done, the evaluation board can be powered up in ve simple steps (see Figure 1), to test either one of
the top and bottom half bridge inverter arms in simulation mode without the need of actual IGBT (or Power MOSFET).

will then stay at 15 V above the virtual ground Ve. R11 is needed to provide the bias current across

cc2

cc2

Testing Either Arm of The Half Bridge Inverter Driver (without IGBT)

1. Solder a 10 nF capacitor across gate and emitter terminals of Q5 (to simulate actual gate capacitance of IGBT/power
MOSFET).

2. Connect a +5 V DC supply (DC supply 1) across +5 V and GND terminals of CON1.

3. Connect another DC supply (DC Supply 2 with voltage range from 21.6 V ~ 30 V) across V

-15 V) terminals of CON2. This can be non-isolated for testing purpose.

4. Supply a 10 kHz 5 V DC pulse (at 50% duty) from a signal generator across IN1+ & IN1– pins of CON1 to simulate
microcontroller output to drive either arm of the half bridge Inverter.

5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points:

a. LED signal at IN1+ pin with reference to (w.r.t.) GND.

b. Fault output for any fault signal appearing at FAULT pin w.r.t. GND.

c. V

d. V

e. V

f. V

g. VgIGBT for the gate driving voltage of Q5/Q6 Gate w.r.t. Ve.

Note: A DESAT fault can be simulated by removing the S2 Jumper.

for the negative output voltage of ACPL-339J at U1 pin 11 w.r.t. Ve (COM pin).

outn

for the positive output voltage of ACPL-339J at U1 pin 12 w.r.t. Ve.

outp

for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. Ve.

gmos

for the DESAT voltage of Q5/Q6 Collector w.r.t. Ve.

desat

(+15V) and Vee (-6.6 V ~

cc2

GND

+5V

DC Supply 1

2

5a

IN1+

Signa l Input

IN1–

4

5b

Figure 1. Simple Simulation Test Setup of Evaluation Board

Schematics

5f

5g

10 nF

5d

5c

1

5e

3

21.6 V ~ 30 V
DC Supply 2

Figure 2 shows the schematics of the Evaluation Board.

CON1

+5V

IN1+

IN1-

FAULT

GND

Figure 2. Schematics of ACPL-339J Evaluation Board

GND

Vcc1

1

NC

2

C1

220p

270

R1
R2

270

C2

S1

220p

C3

Vcc1

330n

10k

R3

CATHODE

3

ANODE

4

CATHODE

5

V

GND1

6

V

CC1

7

FAULT

8

C4

V

1n

GND1

IC1

ACPL-339J

DESAT

V

GMOS

V

V

V

OUTN

V

V

CC2

OUTP

LED

V

16

E

15

14

13

12

11

10

9

EE

Vcc2

VEE

CON2

15V

BZG03C15TR3

1µ

C5

Tant

+

20V

1µ Tant
20V

+

C7

+

10µ
Tant

C6

35V

D2

DFLS220L

C8

100p

15 (½W)

15 (½W)

R4

100

Si7465DP

R5

R6

Si7848BDP

BYM26E

J1

D3

470
R9

Q1

R7//R7a

10R (½W)

10R (½W)

10R (½W)

10R (½W)

R8 //R8a

Q2

S2

R10

330

Q3

Caution: Please
remove S2
jumpers if
IGBT/Power
Mosfet is
connected to
Q5 (or Q6)

Si2318

1k (½W)

R11

D1

VE

VCC2

21.6V~30V

VEE

G

NM

IGBT (or

VE

Power Mosfet)
(TO-220 & TO-247)

VEE

VE

C

Q5

C

Q6

G

NM

E

E

2

Practical Connections of the Evaluation Board Using IGBT/Power MOSFET for Actual Inverter Test

1. Solder actual IGBTs/Power MOSFETs at Q5 (or Q6) for the top and bottom arms of the Half Bridge Inverter Isolated
Drivers.

2. Connect a +5 V DC isolated supply 1 across +5 V and GND terminals of CON1 for both arms of the Isolated Drivers.

3. Connect another isolated DC supply 2 (voltage range from 21.6 V ~ 30 V) across V
arm.

4. Connect another isolated DC supply 3 (voltage range from 21.6 V ~ 30 V) across V
bottom arm.

5. Connect the signal output (meant to drive the top arm of half-bridge Inverter) from the microcontroller to Signal
Input 1 across pin IN1+ and IN1– of CON1 w.r.t. GND of Top Inverter Arm Isolated Driver.

6. Connect the signal output (meant to drive the bottom arm of half-bridge Inverter) from the microcontroller to Signal
Input 2 across pin IN1+ and IN1– of CON1 w.r.t. GND of Bottom Inverter Arm Isolated Driver.

7. Use a multi-channel Digital Oscilloscope to capture the waveforms at these points:

a. LED signal at IN1+ pin with reference to (w.r.t.) GND for Top Arm

b. LED signal at IN1+ pin w.r.t. GND for Bottom Arm

c. Fault output for any fault signal appearing at FAULT1 w.r.t. GND

d. Fault output for any fault signal appearing at FAULT2 w.r.t. GND

e. V

for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. Ve of Top Inverter Arm (dierential probe

gmos

needed)

f. V

for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. Ve of Bottom Inverter Arm (dierential probe

gmos

needed)

g. V

h. V

i. V

j. V

for the DESAT voltage of Q5 (or Q6) w.r.t. Ve of Top Inverter Arm (dierential probe needed)

desat

for the DESAT voltage of Q5 (or Q6) w.r.t. Ve of Bottom Inverter Arm (dierential probe needed)

desat

for the gate driving voltage of Q5/Q6 w.r.t. Ve of Top Inverter Arm (dierential probe needed)

gIGBT

for the gate driving voltage of Q5/Q6 w.r.t. Ve of Bottom Inverter Arm (dierential probe needed)

gIGBT

8. Connect the high voltage cable from Top Arm IGBT Emitter pin to the Bottom Arm IGBT Collector pin and then to the
Inverter load.

9. Connect the high voltage cables from Top Arm IGBT Collector to HVDC+ and from Bottom Arm IGBT Emitter to HVDC–
respectively as shown.

Note:
To protect the Inverter and its driver circuitries, it is recommended that you enable the current limiting function of the HV supply supplying the

High Voltage DC Bus during this test.

and Vee terminals of CON2 for top

cc2

and Vee terminals of CON2 for

cc2

3

5

7c

FAULT1

Microcontroller

IN1+

IN1–

Signal Input 1

GND

DC Supply 1

2

+5V

Top Inverter Arm Isolated Driver

Bottom Inverter Arm Isolated Driver

3

21.6 V ~ 30 V

V

e

DC Supply 2

1

IGBT mounted at

Q5 (or Q6)

HVDC+

9

Note: S2 jumper must
be removed before
this connection

Top Arm of Half-Bridge
Inverter Circuit

8

To Load

IN1+

6

Signal Input2

IN1–

FAULT2

7d

Figure 3. Connection of Evaluation Board in Actual Applications

V

e

4 DC Supply 3

21.6 V ~ 30 V

1

IGBT mounted at

Q5 (or Q6)

Bottom Arm of
Half- Bridge Inverter Circuit

Note: S2 jumper must
be removed before
this connection

9

HVDC–

4

Application Circuit Description

The ACPL-339J is an advanced isolated gate driver that provides 1.0 A output current, suitable for IGBT and power
MOSFET. It is also designed to drive dierent sizes of MOSFET buer stage that will make the class of IGBT scalable. ACPL­339J provides a single isolation solution suitable for both low and high power ratings of motor control and inverter
applications. The input LED is optically coupled to an integrated circuit with two power output stages under non­overlapping timing protection to prevent cross conduction at external MOSFET buers at Q1 and Q2.

Each of the ACPL-339J evaluation boards (see Figure 4) accommodates an ACPL-339J IC. Two boards are needed to drive
top and bottom arms of the Half-bridge Inverter. It allows the designer to easily test the performance of gate driver in
an actual application under real-life operating conditions. Figure 2 shows the typical de-saturation protected gate drive
circuit that is implemented on the evaluation board. Operation of the evaluation board merely requires the inclusion of
a common 5V DC isolated supply on the input side and two isolated DC supplies (range from 21.6 V ~ 30 V): one for top
arm and one for the bottom arm across V
while the balance of the supplied voltage (21.6 V ~ 30 V minus 15 V) will be built across the 1 kΩ resistor (R11) to set the
negative Vee voltage, all with reference to Ve at each arm.

Note:
As can be seen on the board, the isolation circuitry (at the far left) is easily contained within a small area while maintaining adequate spacing for

good voltage isolation and easy assembly.

and Vee. The V

cc2

voltage will then be xed at +15 V by a Zener diode at D1,

cc2

Figure 4. Top and Bottom Views of ACPL-339J Evaluation Board

5

a) Operations of various outputs

The outputs (V
current), UVLO and DESAT conditions. Once the UVLOP+ and UVLON– signals are not active (V
> V

UVLON+

), V
of the ACPL-339J will be the primary source of IGBT/Power MOSFET protection. DESAT will remain functional until V
VE is decreased below V
of the ACPL-339J work alternatively to ensure constant IGBT/MOSFET protection.

, V

OUTP

is allowed to go low and V

OUTP

, V

OUTN

GMOS

or VE - VEE is decreased below V

UVLOP-

and FAULT) of each ACPL-339J are governed by the combination of IF (the LED

- VE > V

CC2

is allowed to go high. Thereafter, the DESAT (pin 15) detection feature

OUTN

. Therefore, the DESAT detection and UVLO features

UVLON-

UVLOP+

, VE - VEE

CC2

-

Table 1 shows the possible output combinations for Fault, V

outp

, V

outn

and V

under the inuence of dierent UVLO

gmos

and DESAT operating conditions, whether they are active or not.

Table 1

I

F

X Active Not Active High High Low V

ON Not Active Active (with DESAT fault) High High Low V

ON Not Active Active (no DESAT fault) Low Low High V

OFF Not Active Not Active Low High Low V

Note:
Normal operating condition is highlighted in blue in the table; X denotes Don’t Care; Logic output of V

UVLOP and UVLON DESAT Function Pin 7 (FAULT) Output V

UVLON is active. This will ensure that MN3 is turned on to shut down the IGBT/SiC FET when insucient power supply VE-VEE is applied.

OUTP

GMOS

V

OUTN

will be changed from VEE to VE when

V

GMOS

E

E

EE

EE

b) Soft-shutdowns from DESAT and UVLO faults

The DESAT pin of each device monitors its IGBT Vce voltage. The internal DESAT fault detection circuitry must remain
disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT
threshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the
DESAT voltage threshold, and the external DESAT blanking capacitor (C8, at 100 pF). The nominal blanking time is
calculated in terms of external capacitance (C
as T

BLANK

= C

BLANK

× V

DESAT

/ I

. The nominal blanking time with the recommended 100 pF capacitor is 100 pF * 8 V /

CHG

250 µA = 3.2 µsec. This nominal blanking time also represents the longest time it will take for each ACPL-339J to respond
to a DESAT fault condition. After T
Q2 MOSFETs and V

switches from Low to High, turning on an external Q3 pull-down MOSFET, to ‘softly’ turn o the

GMOS

time, both V

BLANK

IGBT. Also activated is an internal feedback channel that brings the isolated FAULT output from Low to High to notify the
microcontroller of the fault condition.

), FAULT threshold voltage (V

BLANK

and V

OUTP

OUTN

), and DESAT charge current (I

DESAT

CHG

outputs will turn o the respective external Q1 and

)

Once fault is detected, the output will be muted for T

time. All input LED signals will be ignored during the mute

MUTE

period to allow the driver to completely do a soft shutdown of the IGBT. The fault is auto-reset upon the 1 ms (typical)
mute time (T

) timeout or upon the change in IN1 status from High to Low transition, whichever is later. In this way

MUTE

there is a minimum timeout, yet there is still exibility of lengthening the timeout.

When a DESAT fault is detected, its device’s V

output switches from Low to High, turning on the external Q3 MOSFET

GMOS

pull-down device. Q3 slowly discharges the IGBT gate voltage at a decay rate corresponding to the RC constant of RS
and CIN (the IGBT input capacitance). Based on a RS of 330 Ω (as in R10) and CIN of 10 nF(from the external connected
capacitor at Q5 or Q6), the entire soft shut down will decay in 4.8 * 330 Ω * 10 nF = 15.8 µs. Soft shutdown prevents fast
changes of the collector current that could cause damaging voltage spikes due to lead and wire inductance. Similarly,
when under voltage operation occurs during normal operation, its device’s V

output switches from Low to High,

GMOS

turning on the external Q3 MOSFET pull-down device. Q3 slowly discharges the IGBT gate voltage at a decay rate
corresponding to the RC constant of RS and CIN (the IGBT input capacitance). The entire soft shutdown will decay in 15.8
µs to prevent fast changes in the collector current.

6

Using the Board

It is easy to prepare the evaluation board for use. Only minor preparations (just by soldering cables for DC supplies,
proper cables for HVDC+/HVDC– high voltage bus, and load connections) are required. The evaluation board has a
default setup (as shown in Table 2) when it is shipped to the customer. The customer is free to select dierent settings
for J1, S1 and S2 for his dierent needs.

Table 2

Recommended PWM frequency V

Default Setup

J1 is provided to let customer to adjust the DESAT fault detection voltage to 7 V by replacing it with another BYM26E.
S1 jumper is shorted to ground the IN1-. This can be open if dierential signal is used across IN1+ & IN1– to drive the LED.
S2 jumper can be shorted when IGBT/Power MOSFET are not connected to Q5 (or Q6) to stop the DESAT fault from occurring. It
has to be open, however, when IGBT/Power MOSFET are connected to activate the DESAT fault protection.

1 kHz to 50 kHz (0 ~ 5 V) +5Vdc 21.6 V ~ 30 V Shorted Shorted Shorted

cc1

V

w.r.t. Vee J1 S1 S2

cc2

Output Measurement

Figure 5 and Figure 6 show a sample of Input LED and various output waveforms that have been captured. The soft
shutdown waveform are shown clearly in V

LED ON

I

F

V

DESAT

V

GMOS

V

G(IGBT)

8 V

Soft
Shutdown

gIGBT

waveform.

LED OFF

V

OUTN

V

OUTP

Ext PMOS ON

FAULT

Figure 5. Input LED (tON < t

Ext NMOS OFF

Ext PMOS OFF

) and various output voltage waveforms

MUTE

Ext NMOS ON

7

V

V

V

I

V

OUTN

F

DESAT

GMOS

G(IGBT)

LED ON

8 V

LED OFF

Soft
Shutdown

Ext NMOS ON

Ext NMOS OFF

V

OUTP

Ext PMOS ON

FAULT

Figure 6. Input LED (tON > t

Figure 5 and Figure 6 also show that, once DESAT fault is detected, the output (V

Ext PMOS OFF

) and various output voltage waveforms

MUTE

) will be muted for T

gIGBT

MUTE

time
where input LED signals will be ignored during the mute period to allow for the driver to completely perform a soft
shutdown of the IGBT. The fault is auto-reset upon the 1 ms (typical) mute time (T

) timeout or upon LED Input ‘High’

MUTE

to ‘Low’ transition, whichever is later. In this way there is a minimum timeout, yet there is still exibility of lengthening
the timeout, as in Figure 6.

Performing OR on the Fault Circuits

During normal operation of the circuit under ‘no fault’ condition, LED2 of U1 (IC1) are activated and normally ‘On’,
to pull their respective pin 7 ‘Low’. To improve on the operating eciencies, and at the same time to allow for easy
bootstrapping, the LEDs are made to operate at 50% duty cycle at a frequency of 5 MHz through internal oscillator
circuits. This, however, causes the open collector Fault output at pin 7 of U1 to toggle at undesirable ‘High’ and ‘Low’
levels if only pull-up resistors are connected. To lter away the unwanted oscillating outputs and to keep it at a Low
level, an RC network each is connected (see Figure 7) for both ICs (IC1 and IC2) in the Top and Bottom Arms of the Half­Bridge Inverter Drivers. Corner frequencies of both networks are set at around 15 ~ 16 kHz to have eective ltering.

During an actual fault condition, however, pin 7 will be pulled ‘High’. Due to this positive (or ‘High’) logic, the Fault pins
cannot be tied together to achieve a common Fault level if one and only one of the Inverter Arms experiences a fault.
Tying the Fault pins together causes the voltage level of both Fault pins to stay Low when only one of the ICs experiences
a fault—this is undesirable.

To overcome such a problem and to allow the circuit to correctly report a common Fault level to the microcontroller, a
circuit that performs the OR function consists of an NPN transistor and a base resistor can each be connected to the Fault
pin of their respective IC. As shown in Figure 7, the collector outputs can then be tied (perform an OR) together before a
pull-up resistor and the point on which the OR is performed represents a common Fault signal, albeit in a reversed logic.

8

+5V

FAULT

47k

2N3904

47k

47k

R

10k

1 nF

R

10k

+5V

C

+5V

V

CC1

FAULT

GND1

V

CC1

FAULT

5,8

IC1

6

7

LED2

SHIELD

ACPL-339J

IC2

6

7

LED2

2N3904

C

1 nF

5,8

SHIELD

GND1

ACPL-339J

Figure 7. Performing an OR on the Fault Outputs Of IC1 (Top Arm) and IC2 (Bottom Arm)

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Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved.
AV02-3957EN - July 24, 2014