Avago Technologies ACPL-336J-000E User Manual

ACPL-337J

Isolated IGBT Gate Driver Evaluation board

User's Manual

Quick-Start

Visual inspection is needed to ensure that the evaluation board is received in good condition.

Default connections of the evaluation board are as shown (see Figure 1):

1. Q1 (Bipolar Buer Driver), Q2 (Miller Clamp Bipolar) and Q3 (IGBT) are not mounted. An actual IGBT should be
mounted at Q3 (for TO-247 package), or connected to the driver board through short wire connections from the
holes provided at Q3.

2. CON3 is provided to allow for positive supply (V
is connected to emitter pin of the IGBT).

3. J1 jumper is shorted by default to connect the output to the Gate pin of the IGBT, through gate resistors R6 (10 Ω) &
R7 (0 Ω);

4. R9, R10 and Q1 (provisions for buer driver) are not mounted by default. These components will be needed if more
than 4 A of gate drive current is required (J1 must be removed while R7 must then be shorted to accommodate this).

5. Similarly, Q2 is not mounted by default. This component should be mounted, however, if Miller Clamp current of
more than 2 A is required;

6. CON2 and J2 are shorted by default to allow for a single input PWM signal at Vin+ (pin 2 of CON1) to drive the LED of
ACPL-337J. If a separate LED drive signal (across R3 and R4) is required, then CON2 (and J2 if R4 cannot be grounded
to Gnd) must be opened.

7. CON1 is provided to allow for the power supply (+5V) to be connected across V
direct driving of LED, plus /UVLO and /Fault feedback.

) and negative supply (V

CC2

) with respect to VE (marked as E, which

EE2

and Gnd, TTL signal drive at Vin+,

CC1

Component Side Solder Side

Gnd

Vin+

Vcc1

/UVLO

/Fault

LED+
LED−

J2 shorted

Figure 1. Actual ACPL-337J evaluation board showing default connections

Once inspection is done, the evaluation board can be powered up in seven simple steps, as shown in Figure 2, in simula­tion mode, without the need of actual IGBT.

CON2 shorted

J1 shorted

Testing IGBT Gate Driver (in Simulation Mode)

1. Solder a 10 nF capacitor across the Gate and Emitter terminals of Q3 (to simulate actual gate capacitance of an IGBT).

2. Solder a jumper wire across the Collector and Emitter terminals of Q3 (to simulate a turn-on saturated Collector
voltage of IGBT).

3. Connect a +5V DC supply (DC supply 1) across V

4. Connect another DC supply (DC Supply 2 of +15 V typical or +30 V maximum) across V
terminals of CON3. Connect a third DC supply (DC Supply 3 of -5V typical or -15 V maximum) across V
and VE (E pin) terminals of CON3. Maximum voltage across V
can be non-isolated.

5. Connect a 10 kHz 5 V DC pulse (at about 50% duty) from a dual-output signal generator across IN+ and Gnd pins of
CON1 to simulate microcontroller output to drive the IGBT.

6. Use a multichannel digital oscilloscope to capture the waveforms at the following points:

a. Input PWM signal at IN+ pin (CON1) with reference to (w.r.t.) Gnd.
b. LED signal at LED+ pin w.r.t. Gnd (or LED-). Note: this is a generated LED drive signal from the device ACPL-337J.
c. VG representing the gate drive voltage of ACPL-337J (U1) at G (gate) pin of Q3 w.r.t. E (emitter) pin.
d. Desat signal at pin 14 of U1, which represents the Desat voltage of IGBT’s C (collector) pin during turn-on.
e. Conrm that LED+ signal is almost identical to IN+ signal, and then switch this channel to monitor the simulated

Miller Clamp voltage of IGBT at pin 10 of U1.

7. Provision is done on the board to allow for the LED to be driven directly by 5 V PWM (10 kHz) signals instead of the IN+
signal by disconnecting the shunt post at CON2. Once the shunt post at CON2 is removed, the external PWM signals
(at 10 kHz 5VPP) can be connected directly to LED+ and LED- pins at CON1.

Note:
Before you proceed to the next tests, make sure you remove the jumper wire that was connected in Step 2.

and GND terminals of CON1.

CC1

and V

CC2

EE2

(V

CC2

pin) and VE (E pin)

CC2

(V

EE2

EE2

pin)

is 30 V. For testing, these power supplies

DC Supply 2 DC Supply 3

5

in+

Signal

Input

Gnd

+5V

Gnd

DC Supply 1

3

Vin+

6a

Vcc1

/UVLO

/Fault

LED+

6b

LED -

+15V

6d

6e

0V

–5V

4

6c

1

10 nF

2

Jumper
Short

Figure 2. Simple Simulation Test Setup of Evaluation board

2

Schematics

Figure 3 shows the schematics of the evaluation board.

CON1

V

1

2

3

4

5

6

7

8

EE1

V

IN+

V

CC1

V

LEDDRV

UVLO

FAULT

ANODE

CATHODE

DESAT

V

V

CLAMP

Gnd

1 µF

+

C3

A

T

R2

R1

C1 C2

J2

10k

330p F

Gnd

R3

R4

CON2

150

150

10k

330p F

Figure 3. Schematics of the ACPL-337J evaluation board

V

16

EE2

V

15

LED

14

V

13

E

12

V

CC2

11

OUT

10

9

V

EE2

SBD

BAT42 W

1 µF

A

T

C7 +

1 µF

C4 +

A

T

R6 R7

C5 +

1 µF
T

A

CON3

V

CC2

C6
100pF

V

E

2W

10

PBSS 4041SPN

nm : Not Moun ted

V

R5

Q1a

Q1b

E

J1

R10

V

1k

V

CC2

7,8

PBSS 4041SPN

nm

2

1

R9

nmnm

3

nm

4

5,6

EE2

R8

2ST N2540

CON4

G E

nm

C

1 kV

D1

BYV26E

Q3
(TO2 47)

2W

G

0R

47

Q2

nm

3

1

nm

4,2

V

EE2

C

E

V

E

3