HSMP-382x, 482x
Surface Mount RF PIN Switch and Limiter Diodes
Data Sheet
Description/Applications
The HSMP-382x series is optimized for switching applications where ultra-low resistance is required. The
HSMP-482x diode is ideal for limiting and low inductance switching applications up to 1.5 GHz.
A SPICE model is not available for PIN diodes as
SPICE does not provide for a key PIN diode characteristic, carrier lifetime.
Package Lead Code Identification, SOT-323
(Top View)
DUAL ANODE
HSMP-482B
Package Lead Code Identification, SOT-23
(Top View)
SINGLE
SERIES
Features
• Diodes Optimized for:
Low Current Switching
Low Distortion Attenuating
• Power Limiting /Circuit Protection
• Surface Mount SOT-23 and SOT-323 Packages
Single and Dual Versions
Tape and Reel Options Available
• Low Failure in Time (FIT) Rate
• Lead-free Option Available
Note:
1. For more information see the Surface Mount PIN Reliability
Data Sheet.
[1]
#0
COMMON
ANODE
#3
DUAL ANODE
HSMP-4820
#2
COMMON
CATHODE
#4
2
Absolute Maximum Ratings
[1]
TC = +25°C
Symbol Parameter Unit SOT-23 SOT-323
I
Forward Current (1 µs Pulse) Amp 1 1
f
P
Peak Inverse Voltage V 50 50
IV
T
Junction Temperature °C 150 150
j
T
Storage Temperature °C -65 to 150 -65 to 150
stg
θ
Thermal Resistance
jc
[2]
°C/W 500 150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the
device.
2. TC = +25°C, where TC is defined to be the temperature at the package pins where contact is made
to the circuit board.
Electrical Specifications TC = 25°C
Package Minimum Maximum Maximum
Part Number Marking Lead Breakdown Series Resistance Total Capacitance
HSMP- Code Code Configuration Voltage V
3820 F0 0 Single 50 0.6 0.8
3822 F2 2 Series
3823 F3 3 Common Anode
3824 F4 4 Common Cathode
Test Conditions V
(V) RS (Ω)C
BR
= V
R
Measure
≤ 10 µA
I
R
BR
f = 100 MHz f = 1 MHz
IF = 10 mA V
(pF)
T
= 20 V
R
High Frequency (Low Inductance, 500 MHz – 3 GHz) PIN Diodes
Part Package Breakdown Series Total Total Total
Number Marking Lead Voltage Resistance Capacitance Capacitance Inductance
HSMP- Code Code Configuration VBR (V) RS (Ω)C
4820 FA A Dual Anode 50 0.6 0.75 1.0 1.0
482B FA A Dual Anode
Test Conditions VR = V
Minimum Maximum Typical Maximum Typical
(pF) CT (pF) LT (nH)
T
BR
Measure VR = 20 V VR = 0 V 3 GHz
IF = 10 mA f = 1 MHz f = 1 MHz f = 500 MHz–
IR ≤ 10 µA
Typical Parameters at TC = 25°C
Part Number Series Resistance Carrier Lifetime Reverse Recovery Time Total Capacitance
HSMP- R
382x 1.5 70 7 0.60 @ 20 V
Test Conditions f = 100 MHz I
(Ω) τ (ns) Trr (ns) CT (pF)
S
= 10 mA VR = 10 V
I
= 10 mA IF = 20 mA
F
F
90% Recovery
Typical Parameters at TC = 25°C (unless otherwise noted), Single Diode
3
100
10
1
0.1
– FORWARD CURRENT (mA)
F
I
0.01
125°C
0 0.2 0.4 0.6 0.8 1.0 1.2
VF – FORWARD VOLTAGE (mA)
25°C
–50°C
Figure 1. Forward Current vs.
Forward Voltage.
1.4
1.2
1.0
CAPACITANCE (pF)
0.8
0.6
0 1020304050
– REVERSE VOLTAGE (V)
V
R
Figure 4. Capacitance vs. Reverse
Voltage.
100
= 2V
V
R
V
= 5V
R
10
– REVERSE RECOVERY TIME (ns)
rr
T
1
10 20 30
FORWARD CURRENT (mA)
V
= 10V
R
Figure 2. Reverse Recovery Time vs.
Forward Current for Various Reverse
Voltages.
120
Diode Mounted as a
Series Attenuator in a
115
50 Ohm Microstrip and
Tested at 123 MHz
110
105
100
95
90
INPUT INTERCEPT POINT (dBm)
85
11030
IF – FORWARD BIAS CURRENT (mA)
Figure 5. 2nd Harmonic Input
Intercept Point vs. Forward Bias
Current.
100
10
1
RF RESISTANCE (OHMS)
0.1
0.01 0.1 1 10 100
IF – FORWARD BIAS CURRENT (mA)
Figure 3. RF Resistance at 25°C vs.
Forward Bias Current.
30
25
20
15
10
CW POWER OUT (dBm)
5
Measured with external
bias return
0
0
5
CW POWER IN (dBm)
1.5 GHz
1.0 GHz
20 25 30 3515
4010
Figure 6. Large Signal Transfer Curve
of the HSMP-482x Limiter.
Typical Applications for Multiple Diode Products
RF COMMON
RF 1
BIAS 1
Figure 7. Simple SPDT Switch, Using Only Positive
Current.
RF 2
BIAS 2
RF COMMON
RF 1
RF 2
BIAS BIAS
Figure 8. High Isolation SPDT Switch, Dual Bias.
Typical Applications for Multiple Diode Products, continued
4
RF COMMON
BIAS
RF 1 RF 2
Figure 9. Switch Using Both Positive and Negative
Bias Current.
BIAS
RF 1
RF COMMON
RF 2
BIAS
Figure 10. Very High Isolation SPDT Switch,
Dual Bias.
Figure 11. High Isolation SPST Switch (Repeat Cells
as Required.
Figure 12. Power Limiter Using HSMP-3822 Diode
Pair. See Application Note 1050 for details.
5
Typical Applications for HSMP482x Low Inductance Series
Microstrip Series Connection for
HSMP-482x Series
In order to take full advantage of
the low inductance of the
HSMP-482x series when using
them in series applications, both
lead 1 and lead 2 should be
connected together, as shown in
Figure 14.
3
12
HSMP-482x
Figure 13. Internal Connections.
HSMP-482x Series
In Figure 15, the center conductor
of the microstrip line is interrupted and leads 1 and 2 of the
HSMP-482x diode are placed
across the resulting gap. This
forces the 0.5 nH lead inductance
of leads 1 and 2 to appear as part
of a low pass filter, reducing the
shunt parasitic inductance and
increasing the maximum available
attenuation. The 0.3 nH of shunt
inductance external to the diode
is created by the via holes, and is
a good estimate for 0.032" thick
material.
50 OHM MICROSTRIP LINES
Co-Planar Waveguide Shunt
Connection for HSMP-482x Series
Co-Planar waveguide, with
ground on the top side of the
printed circuit board, is shown in
Figure 17. Since it eliminates the
need for via holes to ground, it
offers lower shunt parasitic
inductance and higher maximum
attenuation when compared to a
microstrip circuit. See AN1050 for
details.
Co-Planar Waveguide
Groundplane
Center Conductor
Groundplane
Figure 17. Circuit Layout.
Figure 14. Circuit Layout.
Microstrip Shunt Connections for
PAD CONNECTED TO
GROUND BY TWO
VIA HOLES
Figure 15. Circuit Layout,
HSMP-482x Limiter.
1.5 nH 1.5 nH
0.8 pF
0.3 nH
0.3 nH
Figure 16. Equivalent Circuit.
0.8 pF
0.75 nH
Figure 18. Equivalent Circuit.
6
Assembly Information
SOT-323 PCB Footprint
A recommended PCB pad layout
for the miniature SOT-323 (SC-70)
package is shown in Figure 19
(dimensions are in inches). This
layout provides ample allowance
for package placement by automated assembly equipment
without adding parasitics that
could impair the performance.
0.026
0.079
0.039
0.022
Dimensions in inches
Figure 19. Recommended PCB Pad
Layout for Avago’s SC70 3L/SOT-323
Products.
SOT-23 PCB Footprint
0.039
0.039
1
1
SMT Assembly
Reliable assembly of surface
mount components is a complex
process that involves many
material, process, and equipment
factors, including: method of
heating (e.g., IR or vapor phase
reflow, wave soldering, etc.)
circuit board material, conductor
thickness and pattern, type of
solder alloy, and the thermal
conductivity and thermal mass of
components. Components with a
low mass, such as the SOT-323/-23
package, will reach solder reflow
temperatures faster than those
with a greater mass.
Avago’s diodes have been qualified to the time-temperature
profile shown in Figure 21. This
profile is representative of an IR
reflow type of surface mount
assembly process.
After ramping up from room
temperature, the circuit board
with components attached to it
(held in place with solder paste)
passes through one or more
preheat zones. The preheat zones
increase the temperature of the
board and components to prevent
thermal shock and begin evaporating solvents from the solder paste.
The reflow zone briefly elevates
the temperature sufficiently to
produce a reflow of the solder.
The rates of change of temperature for the ramp-up and cooldown zones are chosen to be low
enough to not cause deformation
of the board or damage to components due to thermal shock. The
maximum temperature in the
reflow zone (T
) should not
MAX
exceed 235°C.
These parameters are typical for a
surface mount assembly process
for Avago diodes. As a general
guideline, the circuit board and
components should be exposed
only to the minimum temperatures and times necessary to
achieve a uniform reflow of
solder.
0.079
2.0
0.035
0.9
0.031
0.8
Dimensions in
Figure 20. Recommended PCB Pad
Layout for Avago’s SOT-23 Products.
inches
mm
250
200
150
100
TEMPERATURE (°C)
50
0
0
Figure 21. Surface Mount Assembly Profile.
60
Preheat
Zone
120 180 240 300
TIME (seconds)
Reflow
Zone
Cool Down
Zone
T
MAX
Package Dimensions
g
Outline SOT-323 (SC-70)
7
Outline 23 (SOT-23)
E
A1
Notes:
XXX-package marking
Drawin
e1
XXX
e
B
D
s are not to scale
E1
L
C
DIMENSIONS (mm)
MIN.
SYMBOL
A
A
A1
B
C
D
E1
e
e1
E
L
0.80
0.00
0.15
0.10
1.80
1.10
0.65 typical
1.30 typical
1.80
0.425 typical
MAX.
1.00
0.10
0.40
0.20
2.25
1.40
2.40
e2
E
A1
Notes:
XXX-package marking
Drawings are not to scale
Package Characteristics
Lead Material ................................... Copper (SOT-323); Alloy 42 (SOT-23)
Lead Finish ................................... Tin-Lead 85-15% (Non lead-free option)
or Tin 100% (Lead-free option)
Maximum Soldering Temperature .............................. 260°C for 5 seconds
Minimum Lead Strength .......................................................... 2 pounds pull
Typical Package Inductance .................................................................. 2 nH
Typical Package Capacitance .............................. 0.08 pF (opposite leads)
XXX
e
e1
E1
L
B
D
SYMBOL
A
A
A1
B
C
D
E1
e
e1
e2
E
L
C
DIMENSIONS (mm)
MIN.
MAX.
0.79
1.20
0.000
0.100
0.37
0.54
0.086
0.152
2.73
3.13
1.15
1.50
0.89
1.02
1.78
2.04
0.45
0.60
2.10
2.70
0.45
0.69
Ordering Information
Specify part number followed by option. For example:
HSMP - 382x - XXX
Bulk or Tape and Reel Option
Part Number; x = Lead Code
Surface Mount PIN
Option Descriptions
-BLK = Bulk, 100 pcs. per antistatic bag
-TR1 = Tape and Reel, 3000 devices per 7" reel
-TR2 = Tape and Reel, 10,000 devices per 13" reel
Tape and Reeling conforms to Electronic Industries RS-481, “Taping of
Surface Mounted Components for Automated Placement.”
For lead-free option, the part number will have the character "G" at the
end, eg. -TR2G for a 10K pc lead-free reel.
W
Device Orientation
For Outlines SOT-23/323
REEL
TOP VIEW
4 mm
8
END VIE
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
Tape Dimensions and Product Orientation
For Outline SOT-23
P
P
0
t1
D
D
1
8 mm
ABC ABC ABC ABC
Note: "AB" represents package marking code.
"C" represents date code.
P
2
E
F
W
CAVITY
PERFORATION
CARRIER TAPE
DISTANCE
BETWEEN
CENTERLINE
Ko
9° MAX
A
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
DIAMETER
PITCH
POSITION
WIDTH
THICKNESS
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
A
0
B
0
K
0
P
D
1
D
P
0
E
Wt18.00 + 0.30 – 0.10
F
P
2
8° MAX
3.15 ± 0.10
2.77 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.05
1.50 + 0.10
4.00 ± 0.10
1.75 ± 0.10
0.229 ± 0.013
3.50 ± 0.05
2.00 ± 0.05
B
0
0.124 ± 0.004
0.109 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 ± 0.002
0.059 + 0.004
0.157 ± 0.004
0.069 ± 0.004
0.315 + 0.012 – 0.004
0.009 ± 0.0005
0.138 ± 0.002
0.079 ± 0.002
13.5° MAX
Tape Dimensions and Product Orientation
For Outline SOT-323
P
P
0
C
t
(CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS)
1
D
P
2
E
F
W
D
1
CAVITY
PERFORATION
CARRIER TAPE
COVER TAPE
DISTANCE
ANGLE
An
A
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
DIAMETER
PITCH
POSITION
WIDTH
THICKNESS
WIDTH
TAPE THICKNESS
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
FOR SOT-323 (SC70-3 LEAD) An 8°C MAX
FOR SOT-363 (SC70-6 LEAD) 10°C MAX
A
2.40 ± 0.10
0
2.40 ± 0.10
B
0
1.20 ± 0.10
K
0
4.00 ± 0.10
P
1.00 + 0.25
D
1
D
1.55 ± 0.05
P
4.00 ± 0.10
0
1.75 ± 0.10
E
W
8.00 ± 0.30
t
0.254 ± 0.02
1
C
5.4 ± 0.10
T
0.062 ± 0.001
t
3.50 ± 0.05
F
2.00 ± 0.05
P
2
0.094 ± 0.004
0.094 ± 0.004
0.047 ± 0.004
0.157 ± 0.004
0.039 + 0.010
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
0.315 ± 0.012
0.0100 ± 0.0008
0.205 ± 0.004
0.0025 ± 0.00004
0.138 ± 0.002
0.079 ± 0.002
K
0
An
B
0
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited
in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved.
Obsoletes 5989-2498EN
5989-4026EN August 14, 2006
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