AVAGO APDS-9300 Service Manual

APDS-9300

Miniature Ambient Light Photo Sensor
with Digital (I2C) Output

Data Sheet

Description

The APDS-9300 is a low-voltage Digital Ambient Light
Photo Sensor that converts light intensity to digital signal
output capable of direct I2C interface. Each device consists
of one broadband photodiode (visible plus infrared) and
one infrared photodiode. Two integrating ADCs convert
the photodiode currents to a digital output that represents
the irradiance measured on each channel. This digital out­put can be input to a microprocessor where illuminance
(ambient light level) in lux is derived using an empirical
formula to approximate the human-eye response.

Application Support Information

The Application Engineering Group is available to assist
you with the application design associated with APDS­9300 ambient light photo sensor module. You can contact
them through your local sales representatives for addi­tional details.

Features

• Approximate the human-eye response

• Precise Illuminance measurement under diverse

lighting conditions

• Programmable Interrupt Function with User-Dened
Upper and Lower Threshold Settings

• 16-Bit Digital Output with I2C Fast-Mode at 400 kHz

• Programmable Analog Gain and Integration Time

• Miniature ChipLED Package

Height - 0.55mm

Length - 2.60mm

Width - 2.20mm

• 50/60-Hz Lighting Ripple Rejection

• Low 2.5-V Input Voltage and 1.8-V Digital Output

• Low Active Power (0.6 mW Typical) with Power Down

Mode

• RoHS Compliant

Applications

• Detection of ambient light to control display
backlighting

o Mobile devices – Cell phones, PDAs, PMP

o Computing devices – Notebooks, Tablet PC, Key

board

o Consumer devices – LCD Monitor, Flat-panel TVs,

Video Cameras, Digital Still Camera

• Automatic Residential and Commercial Lighting
Management

• Automotive instrumentation clusters.

• Electronic Signs and Signals

Ordering Information

I2C

Interrupt

ADC Register

Command

Register

Address Select

Ch0 (Visible + IR)

Ch1 (IR)

SCL
SDA

ADDR SEL

VDD= 2.4 V
to 3.0 V

INT

ADC

ADC

GND

Part Number Packaging Type Package Quantity

APDS-9300-020 Tape and Reel 6-pins Chipled package 2500

Functional Block Diagram

I/O Pins Conguration Table

Pin Symbol Description

1 V

2 GND Ground

3 ADDR SEL Address Select

4 SCL Serial Clock

5 SDA Serial Data

6 INT Interrupt

DD

2

Voltage Supply

Absolute Maximum Ratings

Parameter Symbol Min Max Unit

Supply voltage V

Digital output voltage range V

Digital output current I

Storage temperature range T

ESD tolerance human body model - 2000 V

DD

O

O

stg

- 3.8 V

-0.5 3.8 V

-1 20 mA

-40 85 ºC

Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit Conditions

Supply Voltage V

Operating Temperature T

SCL, SDA input low voltage V

SCL, SDA input high voltage V

DD

a

IL

IH

2.4 2.5 3.0 V

-30 - 85 ºC

-0.5 - 0.58 V

1.13 - 3.6 V 2.4 ≤ VDD ≤ 2.6

1.25 - 3.6 V 2.4 ≤ VDD ≤ 3.0

Electrical Characteristics

Parameter Symbol Min Typ Max Unit Conditions

Supply current I

INT, SDA output low voltage V

Leakage current I

DD

OL

LEAK

-

-

0
0

0.24

3.2

-

-

0.6
15

0.4

0.6

mA
μA

V
V

-5 - 5 μA

Active
Power down

3 mA sink current
6 mA sink current

3

Operating Characteristics, High Gain (16X), VDD = 2.5 V, Ta = 25 ºC, (unless otherwise noted) (see Notes 2, 3, 4, 5)

Parameter Symbol Channel Min Typ Max Unit Conditions

Oscillator frequency fosc 690 735 780 kHz

Dark ADC count value Ch0 0 4 counts Ee = 0, Tint = 402 ms

Ch1 0 4

Full scale ADC count value
(Note 6)

ADC count value Ch0 750 1000 1250 counts λp = 640 nm, Tint = 101 ms

ADC count value ratio: Ch1/
Ch0

Irradiance responsivity Re Ch0 27.5 counts/

Illuminance responsivity Rv Ch0 36 counts/

ADC count value ratio: Ch1/
Ch0

Illuminance responsivity,
low gain mode (Note 7)

(Sensor Lux) /(actual Lux),
high gain mode (Note 8)

Rv Ch0 2.3 counts/

Ch0 65535 counts Tint > 178 ms

Ch1 65535

Ch0 37177 Tint = 101 ms

Ch1 37177

Ch0 5047 Tint = 13.7 ms

Ch1 5047

Ch1 200 Ee = 36.3 µW/cm2

Ch0 700 1000 1300 λp = 940 nm, Tint = 101 ms

Ch1 820 Ee = 119 µW/cm2

0.15 0.2 0.25 λp = 640 nm, Tint = 101 ms

0.69 0.82 0.95 λp = 940 nm, Tint = 101 ms

λp = 640 nm, Tint = 101 ms

Ch1 5.5

Ch0 8.4 λp = 940 nm, Tint = 101 ms

Ch1 6.9

Ch1 4 Tint = 402 ms

Ch0 144 Incandescent light source:

Ch1 72 Tint = 402 ms

0.11 Fluorescent light source:

0.5 Incandescent light source:

Ch1 0.25 Tint = 402 ms

Ch0 9 Incandescent light source:

Ch1 4.5 Tint = 402 ms

0.65 1 1.35 Fluorescent light source:

0.60 1 1.40 Incandescent light source:

(µW/cm2)

Fluorescent light source:

lux

Tint = 402 ms

Tint = 402 ms

Fluorescent light source:

lux

Tint = 402 ms

Tint = 402 ms

4

Notes:

2. Optical measurements are made using small–angle incident radiation from light–emitting diode optical sources. Visible 640 nm LEDs and infrared
940 nm LEDs are used for nal product testing for compatibility with high–volume production.

3. The 640 nm irradiance Ee is supplied by an AlInGaP light–emitting diode with the following characteristics: peak wavelength lp = 640 nm and
spectral halfwidth Dl½ = 17 nm.

4. The 940 nm irradiance Ee is supplied by a GaAs light–emitting diode with the following characteristics: peak wavelength lp = 940 nm and spectral
halfwidth Dl½ = 40 nm.

5. Integration time Tint, is dependent on internal oscillator frequency (fosc) and on the integration eld value in the timing register as described in
the Register Set section. For nominal fosc = 735 kHz, nominal Tint = (number of clock cycles)/fosc.

Field value 00: Tint = (11 • 918)/fosc = 13.7 ms
Field value 01: Tint = (81 • 918)/fosc = 101 ms
Field value 10: Tint = (322 • 918)/fosc = 402 ms
Scaling between integration times vary proportionally as follows:
11/322 = 0.034 (eld value 00), 81/322 = 0.252 (eld value 01), and 322/322 = 1 (eld value 10).

6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also by a 2–count
oset.

Full scale ADC count value = ((number of clock cycles)/2 - 2)
Field value 00: Full scale ADC count value = ((11 • 918)/2 - 2) = 5047
Field value 01: Full scale ADC count value = ((81 • 918)/2 - 2) = 37177
Field value 10: Full scale ADC count value = 65535, which is limited by 16 bit register. This full scale ADC count value is reached for 131074

clock cycles, which occurs for Tint = 178 ms for nominal fosc = 735 kHz.

7. Low gain mode has 16x lower gain than high gain mode: (1/16 = 0.0625).

8. For sensor Lux calculation, please refer to the empirical formula in Application Note. It is based on measured Ch0 and Ch1 ADC count values for the
light source specied. Actual Lux is obtained with a commercial luxmeter. The range of the (sensor Lux) / (actual Lux) ratio is estimated based on
the variation of the 640 nm and 940 nm optical parameters. Devices are not 100% tested with uorescent or incandescent light sources.

CH1/CH0 Sensor Lux Formula

0 ≤ CH1/CH0 ≤ 0.52 Sensor Lux = (0.0315 x CH0) – (0.0593 x CH0 x ((CH1/CH0)

0.52 ≤ CH1/CH0 ≤ 0.65 Sensor Lux = (0.0229 x CH0) – (0.0291 x CH1)

0.65 ≤ CH1/CH0 ≤ 0.80 Sensor Lux = (0.0157 x CH0) – (0.0180 x CH1)

0.80 ≤ CH1/CH0 ≤ 1.30 Sensor Lux = (0.00338 x CH0) – (0.00260 x CH1)

CH1/CH0 ≥ 1.30 Sensor Lux = 0

1.4

))

AC Electrical Characteristics (VDD = 3 V, Ta = 25 ºC)

Parameter † Min. Typ. Max. Unit

t

(CONV)

f

(SCL)

t

(BUF)

t

(HDSTA)

t

(SUSTA)

t

(SUSTO)

t

(HDDAT)

t

(SUDAT)

t

(LOW)

t

(HIGH)

t

F

t

R

C

j

† Specied by design and characterization; not production tested.

Conversion time 12 100 400 ms

Clock frequency - - 400 kHz

Bus free time between start and stop condition 1.3 - - μs

Hold time after (repeated) start condition. After this

0.6 - - μs

period, the rst clock is generated.

Repeated start condition setup time 0.6 - - μs

Stop condition setup time 0.6 - - μs

Data hold time 0 - 0.9 μs

Data setup time 100 - - ns

SCL clock low period 1.3 - - μs

SCL clock high period 0.6 - - μs

Clock/data fall time - - 300 ns

Clock/data rise time - - 300 ns

Input pin capacitance - - 10 pF

5

Parameter Measurement Information

A0A1A2A3A4A5A 6D1D2D3D4D5D6D7D0

R/W

Start by
Master

ACK by
APDS-9300

Stop by
Master

ACK by
APDS-9300

SDA

Frame 1 I2C Slave Address Byte

Frame 2 Command Byte

SCL

1 9 1 9

SDA

SCL

StopStart

SCL

ACK

t

(LOWMEXT)

t

(LOWMEXT)

t

(LOWSEXT)

SCL

ACK

t

(LOWMEXT)

SDA

SCL

Start

Condition

Stop

Condition

P

t

(SUSTO)

t

(SUDAT)

t

(HDDAT)

t

(BUF)

V

IH

V

IL

t

(R)

t

(LOW)

t

(HIGH)

t

(F)

t

(HDSTA)

V

IH

V

IL

P S

S

t

(SUSTA)

A0A1A2A3A4A5A6D1D2D3D4D5D6D7D 0

R/W

Start by
Master

ACK by

APDS-9300

Stop by
Master

NACK by

Master

SDA

Frame 1 I2C Slave Address Byte

Frame 2 Data Byte From APDS-9300

SCL

1 9 1

9

Figure 1. Timing Diagrams

Figure 2. Example Timing Diagram for I2C Send Byte Format

Figure 3. Example Timing Diagram for I2C Receive Byte Format

6

Typical Characteristics

SPECTRAL RESPONSIVITY

0

400

0.2

0.4

0.6

0.8

1

500 600 700 800 900 1000 1100

NORMALIZED RESPONSIVITY

300

CHANNEL 1

PHOTODIODE

CHANNEL 0
PHOTODIODE

- WAVELENGTH - nm

470 pF

ANGULAR DISPLACEMENT - °

NORMALIZED RESPONSIVITY

0

0.2

0.4

0.6

0.8

1.0

-90 -60 -30 0 30 60

90

OPTICAL AXIS

Figure 4. Normalized Responsivity vs. Spectral Responsivity Figure 5. Normalized Responsivity vs. Angular Displacement * CL Package

Principles of Operation

Analog–to–Digital Converter

The APDS-9300 contains two integrating analog–to–digi­tal converters (ADC) that integrate the currents from the
channel 0 and channel 1 photodiodes. Integration of both
channels occurs simultaneously, and upon completion of
the conversion cycle the conversion result is transferred to
the channel 0 and channel 1 data registers, respectively.
The transfers are double buered to ensure that invalid
data is not read during the transfer. After the transfer, the
device automatically begins the next integration cycle.

Digital Interface

Interface and control of the APDS-9300 is accomplished
through a two–wire serial interface to a set of registers
that provide access to device control functions and out­put data. The serial interface is compatible to I2C bus Fast–
Mode. The APDS-9300 oers three slave addresses that
are selectable via an external pin (ADDR SEL). The slave
address options are shown in Table 1.

Table 1. Slave Address Selection

ADDR SEL Terminal Level Slave Address

GND 0101001

Float 0111001

V

DD

NOTE:
The Slave Addresses are 7 bits and please note the I2C protocols. A read/
write bit should be appended to the slave address by the master device
to properly communicate with the APDS-9300 device.

1001001

7