AUSTN AS4SD4M16DG-8-IT, AS4SD4M16DG-10-XT Datasheet
Austin Semiconductor, Inc.
CLOCK
SDRAM
AS4SD4M16
4 Meg x 16 SDRAM
Synchronous DRAM Memory
FEATURES
• Extended Testing Over -55°C to +125° C and
Industrial T emp -40°C to 85° C
• WRITE Recovery ( t
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge and Auto Refresh Modes
• Self Refresh Mode (Industrial, -40°C to 85° C only)
• 4,096-cycle refresh
• L VTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Longer lead TSOP for improved reliability
(OCPL*)
• Short Flow / Long Flow T est Screening Options
OPTIONS MARKING
• Configurations
4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16
• Plastic Package - OCPL*
54-pin TSOP (400 mil) D G No. 901
WR
/ t
) tWR = 2 CLK
DPL
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
• Timing (Cycle Time)
8ns; tAC = 6.5ns @ CL = 3 ( tRP - 24ns) -8
10ns; tAC = 9ns @ CL = 2 -10
• Operating Temperature Ranges
-Military (-55°C to +125° C) XT
-Industrial T emp (-40°C to 85° C) IT
KEY TIMING PARAMETERS
SPEED
GRADE FREQUENCY CL = 2** CL = 3** TIME TIME
-8 125 MHz – 6.5ns 2ns 1ns
-10 100 MHz – 7ns 3ns 1ns
-8 83 MHz 9ns – 2ns 1ns
-10 66 MHz 9ns – 3ns 1ns
*Off-center parting line
**CL = CAS (READ) latency
AS4SD4M16
Rev. 1.5 10/01
ACCESS TIME
SETUP HOLD
Note: “\” indicates an active low.
4 Meg x 16
Configuration 1 Meg x 16 x 4 banks
Refresh Count 4K
Row Addressing 4K (A0-A11)
Bank Addressing 4 (BA0, BA1)
Column Addressing 256 (A0-A7)
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GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally
configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock
signal, CLK). Each of the x16’s 6,777,216-bit banks is or ganized
as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A11 select the row). The address bits
registered coincident with the READ or WRITE command are
used to select the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is initi-
SDRAM
AS4SD4M16
ated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one
bank while accessing one of the other three banks will hide the
precharge cycles and provide seamless, high-speed, randomaccess operation.
The 64Mb SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All inputs and
outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating
performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation,
the ability to interleave between internal banks in order to hide
precharge time and the capability to randomly change column
addresses on each clock cycle during a burst access.
AS4SD4M16
Rev. 1.5 10/01
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TABLE OF CONTENTS
Functional Block Diagram - 4 Meg x 16 ........................................ 4
Pin Descriptions ............................................................................. 5
Functional Description ................................................................. 6
Initialization ............................................................................. 6
Register Definition ................................................................. 6
Mode Register ................................................................ 6
Burst Length ................................................................... 6
Burst Type ....................................................................... 7
CAS Latency ................................................................... 8
Operating Mode ............................................................. 8
Write Burst Mode .......................................................... 8
Commands ....................................................................................... 9
Truth Table 1 (Commands and DQM Operation) ......................... 9
Command Inhibit .................................................................... 10
No Operation (NOP) .................................................................10
Load Mode Register ............................................................. 10
Active ....................................................................................... 10
Read .......................................................................................... 10
Write ......................................................................................... 10
Precharge ................................................................................. 10
Auto Precharge ...................................................................... 10
Burst Terminate ...................................................................... 1 1
Auto Refresh .......................................................................... 11
Self Refresh ............................................................................. 11
Operation ..................................................................................... 12
Bank/Row Activation ............................................................ 12
Reads ........................................................................................ 13
Writes ....................................................................................... 19
Precharge................................................................................... 21
Power-Down...............................................................................21
SDRAM
AS4SD4M16
Clock Suspend......................................................................... 22
Burst Read/Single Write ...........................................................22
Concurrent Auto Precharge ................................................. 23
Truth T able 2 (CKE) ......................................................................2 5
Truth Table 3 (Current State, Same Bank) ................................. 26
Truth Table 4 (Current State, Different Bank) ........................... 28
Absolute Maximum Ratings ........................................................ 30
DC Electrical Characteristics and Operating Conditions......... 30
ICC Specifications and Conditions .............................................. 30
Capacitance ..................................................................................... 31
AC Electrical Characteristics (Timing T able) ............................31
Timing W aveforms
Initialize and Load Mode Register ..................................... 34
Power-Down Mode ................................................................ 35
Clock Suspend Mode ........................................................... 36
Auto Refresh Mode .............................................................. 37
Self Refresh Mode ................................................................. 38
Reads
Read - Without Auto Precharge ................................. 39
Read - With Auto Precharge ....................................... 40
Alternating Bank Read Accesses .............................. 41
Read - Full-Page Burst ......................................................... 42
Read - DQM Operation ................................................ 43
Writes
Write - W ithout Auto Precharge ................................ 44
Write - W ith Auto Precharge ...................................... 45
Alternating Bank Write Accesses .............................. 46
Write - Full-Page Burst ................................................. 47
Write - DQM Operation ............................................... 48
AS4SD4M16
Rev. 1.5 10/01
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3
CKE
CLK
CS\
WE\
CAS\
RAS\
A0,
A10,
BA
MODE REGISTER
ADDRESS
14
REGISTER
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIA GRAM
4 Meg x 16 SDRAM
CONTROL
LOGIC
DECODE
COMMAND
REFRESH
12
12
2
ROW
ADDRESS
MUX
2
CONTROL
COLUMNADDRESS
COUNTER/
COUNTER
1
12
8
12
BANK
LOGIC
LATCH
BANK0
ROW-
ADDRESS
LATCH &
DECODER
8
(4,096 X 256 X 16)
4096
SENSE AMPLIFIERS
DQM MASK LOGIC
READ DATA LATCH
BANK2
BANK1
BANK 0
MEMORY
ARRAY
4096
I/O GATING
WRITE DRIVERS
256
(X16)
COLUMN
DECODER
BANK3
AS4SD4M16
2 2
DATA
OUTPUT
16
REGISTER
DATA
16
INPUT
REGISTER
SDRAM
DQML, DQMH
DQ0-DQ15
16
AS4SD4M16
Rev. 1.5 10/01
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PIN DESCRIPTION
SDRAM
AS4SD4M16
TSOP
PIN NUMBERS
SYMBOL TYPE
38 CLK Input
37 CKE Input
19 CS\ Input
16, 17 WE\, CAS\ Input
18 RAS\
15, 39 DQML, Input
DQMH
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE
in either bank) or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down and self
refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
Chip Select: CS\ enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS\ is registered
HIGH. CS\ provides for external bank selection on systems with multiple
banks. CS\ is considered part of the command code.
Command Inputs: RAS\, CAS\, and WE\ (along with CS\) define the
command being entered.
Input/Output Mask: DQM is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQM is
sampled HIGH during a WRITE cycle. The output buffers are placed in a
High-Z state (two-clock latency) when DQM is sampled HIGH during a READ
cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15.
DQML and DQMH are considered same state when referenced as DQM.
20, 21 BA0, BA1 Input
23-26, 29-34, A0-A11 Input
22, 35
2, 4, 5, 7, 8 DQ0- DQ15 Input/
10, 11, 13, 42 Output
44, 45, 47, 48
50, 51, 53
36, 40 NC —
3, 9, 43, 49 VDDQ Supply
6, 12, 46, 52 VSSQ Supply
1, 14, 27 VDD Supply
28, 41, 54 VSS Supply
AS4SD4M16
Rev. 1.5 10/01
Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
Address Inputs: A0-A11 are sampled during the ACTIVE command (row
address A0-A11) and READ/WRITE command (column address A0-A7, with
A10 defining AUTO PRECHARGE) to select one location out of the memory
array in the respective bank. A10 is sampled during a PRECHARGE
command to determine if all banks are to be precharged (A10 HIGH) or bank
selected by BA0,BA1 (LOW). The address inputs also provide the op-code
during a LOAD MODE REGISTER command.
Data I/O: Data bus.
No Connect: These pins should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: +3.3V ±0.3V.
Ground.
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SDRAM
AS4SD4M16
FUNCTIONAL DESCRIPTION
In general, the 64Mb SDRAM is quad-bank DRAM (1
Meg x 16 x 4 banks) which operate at 3.3V and include a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x16’s
16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0 and
BA1 select the bank, A0-A11 select the row). The address bits
( x16: A0-A7) registered coincident with the READ or WRITE
command are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
Initalization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than those
specified may result in undefined operation. Once power is
applied to V
stable, the SDRAM requires a 100µs delay prior to applying an
executable command. Starting at some point during this 100µs
period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied.
one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks
must be precharged, thereby placing the device in the all banks
idle state.
must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown
state, it should be loaded prior to applying any operational
command.
DD and VDDQ (simultaneously) and the clock is
Once the 100µs delay has been satisfied with at least
Once in the idle state, two AUTO REFRESH cycles
REGISTER DEFINITION
Mode Register
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in Figure 1.
The Mode Register is programmed via the LOAD MODE
REGISTER command and will retain the stored information until
it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved), M4M6 specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and M11
are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable, as shown
in Figure 1. The burst length determines the maximum number
of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations are
available for both the sequential and the interleaved burst types,
and a full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is reached.
The block is uniquely selected by A1-A7 (x16) when the burst
length is set to two; A2-A7 (x16) when the burst length is set to
four; and by A3-A7 (x16) when the burst length is set to eight.
The remaining (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
AS4SD4M16
Rev. 1.5 10/01
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Austin Semiconductor, Inc.
A0
A0
A0
Table 1
Burst
SDRAM
AS4SD4M16
BURST TYPE
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting column
address, as shown in Table 1.
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
11 10 9 8 7 6 5 4 3 2 1 0
Reserved* WB Op Mode CAS Latency BT Burst Length
* Should program M11,
M10=0,0 to ensure
compatibility with future
devices.
M3
0
1
M9
0
1
M8 M7
00
--
M6 - M0
Defined
-
Write Burst Mode
Programmed Burst Length
Single Location Access
Operating Mode
Standard Operation
All other states reserved
M2 M1 M0
000 1 1
001 2 2
010 4 4
011 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
Burst Type
Sequential
Interleave
M6 M5 M4
000
001
010
011
100
101
110
111
Mode Register(Mx)
Burst Length
M3=0 M3=1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
FIGURE 1
MODE REGISTER DEFINITION
Length
2
4
8
Full Page
(y)
NOTE:
BURST DEFINITION
Starting Column
Address
A1
0 0 0,1,2,3 0,1,2,3
0 1 1,2,3,0 1,0,3,2
1 0 2,3,0,1 2,3,0,1
1 1 3,0,1,2 3,2,1,0
A2 A1
0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
0 0 1 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6
0 1 0 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5
0 1 1 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4
1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
1 0 1 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2
1 1 0 6,7,0,1,2,3,4,5, 6,7,4,5,2,3,0,1
1 1 1 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
n = A0 - A9
location 0 - y
Order of Access Within a Burst
Type = Sequential Type = Interleaved
0 0 - 1 0 - 1
1 1-0 1-0
Cn, Cn+1, Cn+2,
Cn+3, Cn+4…
…Cn-1,
Cn…
Not Supported
1 . For full-page accesses: y = 256 (x16).
2 . For a burst length of two, A1-A7 (x16)
select the block-of-two burst; A0 selects
the starting column within the block.
3 . For a burst length of four, A2-A7 (x16)
select the block-of-four burst; A0-A1
select the starting column within the
block.
4 . For a burst length of eight, A3-A7 (x16)
select the clock-of-eight burst; A0-A2
select the starting column within the
block.
5 . For a full-page burst, the full row is
selected and A0-A7 (x16) select the
starting column.
6. Whenever a boundary of the block is
reached within a given sequence above,
the following access wraps within the
block.
7 . For a burst length of one, A0-A7 (x16)
select the unique column to be accessed,
and Mode Register bit M3 is ignored.
AS4SD4M16
Rev. 1.5 10/01
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7
Austin Semiconductor, Inc.
-10
3
3
3
123
123
123
123
3
3
3
3
3
3
123
123
123
SDRAM
AS4SD4M16
CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock edge
n+m. The DQs will start driving as a result of the clock edge one
cycle earlier (n + m - 1), and provided that the relevant access
times are met, the data will be valid by clock edge n + m. For
example, assuming that the clock cycle time is such that all
relevant access times are met, if a READ command is registered
at T0 and the latency is programmed to two clocks, the DQs will
start driving after T1 and the data will be valid by T2, as shown
in Figure 2. T able 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
T3T2T1T0
CLK
2
COMMAMD
DQ
2
NOP
t
LZ
t
AC
NOPREAD
t
OH
2
2
D
OUT
2
Reserved states should not be used as unknown op-
eration or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting
M7and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both READ and WRITE
bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but write
accesses are single-location (nonburst) accesses.
Table 2
CAS LATENCY
ALLOWABLE OPERATING FREQUENCY
(MHz)
SPEED
CAS LATENCY = 2 CAS LATENCY = 3
-8 ≤ 83
≤ 66
≤ 125
≤ 100
CLK
COMMAMD
DQ
AS4SD4M16
Rev. 1.5 10/01
CAS Latency = 2
READ
NOP
CAS Latency = 3
Figure 2
CAS LATENCY
NOP
T3T2T1T0
T4
NOP
t
LZ
t
AC
t
OH
2
2
D
2
OUT
UNDEFINED
2
DON’T CARE
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8
SDRAM
WE\
AS4SD4M16
Austin Semiconductor, Inc.
COMMANDS
Truth Table 1 provides a quick reference of available commands.
This is followed by a written description of each command.
Two additional Truth Tables appear following the Operation
section; these tables provide current state/next state information.
TRUTH TABLE 1- Commands and DMQ Operation
(Note: 1)
NAME (FUNCTION) CS\ RAS\ CAS\
COMMAND INHIBIT (NOP) H X X X X X X
NO OPERATION (NOP) L H H H X X X
ACTIVE (select bank and activate row) L L H H X Bank/Row X 3
READ (select bank and column and start READ burst) L H L H X Bank/Col X 4
WRITE (select bank and column and start WRITE burst) L H L L X Bank/Col Valid 4
BURST TERMINATE L H H L X X Active
PRECHARGE (deactivate row in bank or banks) L L H L X Code X 5
AUTO REFRESH or SELF REFRESH (enter self refresh
mode)
LOAD MODE REGISTER L L L L X OpCode X 2
Write Enable/Output Enable - - - - L - Active 8
Write Inhibit/Output High-Z - - - - H - High-Z 8
LL
DQM ADDR DQs NOTES
X 6,7LHX X
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2 . A0-A11 define the op-code written to the Mode Register.
3 . A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4 . A0-A7 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10
5 . A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW .
7 . Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8 . Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
AS4SD4M16
Rev. 1.5 10/01
LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
“Don’t Care.”
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SDRAM
AS4SD4M16
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not affected.
NO OPERA TION (NOP)
The NO OPERA TION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS\ is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-A11. See
Mode Register heading in the Register Definition section. The
LOAD MODE REGISTER command can only be issued when
all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-A7
(x16) selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written
to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is
registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a speci-
fied time (tRP) after the PRECHARGE command is issued. Input
A10 determines whether one or all banks are to be precharged,
and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in the idle
state and must be activated prior to any READ or WRITE commands being issued to that bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-A7
(x16) selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to
the logic level on the DQM inputs two clocks earlier. If a given
DQM signal was registered HIGH, the corresponding DQs will
be High-Z two clocks later; if the DQM signal was registered
LOW , the DQs will provide valid data.
AS4SD4M16
Rev. 1.5 10/01
AUT O PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of the
bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ
or WRITE burst, except in the full-page burst mode, where
AUTO PRECHARGE does not apply . AUTO PRECHARGE is
nonpersistent in that it is either enabled or disabled for each
individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time,
as described for each burst type in the Operation section of this
data sheet.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
Austin Semiconductor, Inc.
BURST TERMINATE
The BURST TERMINA TE command is used to truncate either fixed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet.
AUT O REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS\-BEFORE-RAS\ (CBR)
REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’ t Care” during an
AUTO REFRESH command. The 64Mb SDRAM requires 4,096
AUTO REFRESH cycles every 64ms *(t
option. Providing a distributed AUTO REFRESH command
every 15.625µs/3.906µs will meet the refresh requirement and
ensure that each row is refreshed. Alternatively, 4,096 AUTO
REFRESH commands can be issued in a burst at the minimum
cycle rate (tRC), once every 64ms/ 16ms.
), regardless of width
REF
SDRAM
AS4SD4M16
SELF REFRESH
(Industrial -40°C to +85°C Only)
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains data
without external clocking. The SELF REFRESH command is
initiated like an AUTO REFRESH command except CKE is
disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become “Don’t Care,” with the
exception of CKE, which must remain LOW .
Once self refresh mode is engaged, the SDRAM
provides its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in self
refresh mode for a minimum period equal to t
remain in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for t
because time is required for the completion of any internal
refresh in progress.
If during normal operation AUTO REFRESH cycles
are issued in bursts (as opposed to being evenly distributed),
a burst of 4,096 AUTO REFRESH cycles should be completed
just prior to entering and just after exiting the self refresh mode.
The self refresh option is not available for the -55° to
+125° screening option.
and may
RAS
XSR
,
*64ms for -40° to +85° C ( Industrial Temperatures) and 16ms for -55° to +125°C (Military Temperatures)
AS4SD4M16
Rev. 1.5 10/01
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Austin Semiconductor, Inc.
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3
OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row, subject
to the
t
specification. t
RCD
clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on
which a READ or WRITE command can be entered. For
t
example, a
specification of 30ns with a 90 MHz clock
RCD
(11.11ns period) results in 2.7 clocks, rounded to 3. This is
reflected in Figure 4, which covers any case where 2 <
(MIN)/ tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles).
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is
t
defined by
RC
.
A subsequent ACTIVE command to another bank can
be issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. The minimum time
interval between successive ACTIVE commands to different
banks is defined by
t
RRD
(MIN) should be divided by the
RCD
.
t
RCD
SDRAM
AS4SD4M16
CLK
HIGH
CKE
2345678901
CS\
2345678901
RAS\
2345678901234
CAS\
2345678901234
WE\
23456789012345
A0-A11
23456789012345
BA0, 1
ACTIVATING A SPECIFIC ROW IN A
SPECIFIC BANK
ROW ADDRESS
BANK ADDRESS
Figure 3
2345678901
2345678901
2345678
2345678
23456789012
23456789012
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
t
NOP
RCD
READ or
WRITE
23
DON’T CARE
Figure 4
EXAMPLE: MEETING t
AS4SD4M16
Rev. 1.5 10/01
12
(MIN) WHEN 2<t
RCD
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
(MIN)/tCK<3
RCD
Austin Semiconductor, Inc.
1
1
1
0
8
3
8
3
4
1
4
1
4
1
3
3
4
4
SDRAM
AS4SD4M16
READs
READ bursts are initiated with a READ command, as shown in
Figure 5.
The starting column and bank addresses are provided
with the READ command, and AUTO PRECHARGE is either
enabled or disabled for that burst access. If AUTO PRECHARGE
is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the
following illustrations, AUTO PRECHARGE is disabled.
During READ bursts, the valid data-out element from
the starting column address will be available following the CAS
latency after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 6
shows general timing for each possible CAS latency setting.
CLK
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the end of the
page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-length READ
burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be
maintained. The first data element from the new burst follows
either the last element of a completed burst or the last desired
data element of alonger burst which is being truncated. The
new READ command should be issued x cycles before the clock
edge at which the last desired data element is valid, where x
equals the CAS latency minus one.
CLK
T0
T1
T2
T3
CKE
CS\
RAS\
CAS\
WE\
A0-A7: x16
A8, A9, A11: x16
A10
BA0, 1
HIGH
23456789012
234567890
23456789012
234567890123
234567890123
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
234567890123
Figure 5
READ COMMAND
COLUMN ADDRESS
BANK ADDRESS
234567
23456789
234567
234567890
234567890
234567890
COMMAND
CLK
COMMAND
DQ
DQ
T0
READ
READ
NOP
t
LZ
t
AC
CAS Latency = 2
T1
NOP
t
LZ
CAS Latency = 3
Figure 6
CAS LATENCY
T2
NOP
NOP
t
DOUT
t
AC
OH
T3
NOP
DOUT
T4
t
OH
2
2
DON’T CARE
23
23
UNDEFINED
AS4SD4M16
Rev. 1.5 10/01
13
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Austin Semiconductor, Inc.
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4
1234567
1234567
1234567
1234567
1234567
1234567
4
4
4
4
4
4
3
3
3
123
3
3
3
123
SDRAM
AS4SD4M16
This is shown in Figure 7 for CAS latencies of two and three;
data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. The 64Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A READ command can
T0 T1 T2 T3 T4 T5
CLK
COMMAND
ADDRESS
DQ
○○○○○○○○○○○○○○○○○○○○
READ READ
BANK,
COL
n
○○○○○○○○○○○○○○○○○○
NOP NOP
2
2
2
CAS Latency = 2
○○○○○○○○○○○○○○○○○○○○
23
23
23
DOUT
n
be initiated on any clock cycle following a previous READ
command. Full-speed random read accesses can be performed
to the same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.
T6
○○○○○○○○○○○○○○○○○○○○
NOP
2
2
2
DOUT
n+1
○○○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○○○
NOP
X=1 cycle
2
BANK,
COL
DOUT
n+2
b
2
2
DOUT
n+3
○○○○○○○○○○○○○○○○○○○○
NOP
2
2
2
DOUT
b
COMMAND
ADDRESS
AS4SD4M16
Rev. 1.5 10/01
T0 T1 T2 T3 T4 T5
CLK
○○○○○○○○○○○○○○○○○○○○
READ
BANK,
COL
○○○○○○○○○○○○○○○○○○
NOP NOP
23
23
n
23
○○○○○○○○○○○○○○○○○○
23
23
23
DQ
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
○○○○○○○○○○○○○○○○○○○○
NOP
23
23
23
DOUT
n
Figure 7
CONSECUTIVE READ BURSTS
14
T6
○○○○○○○○○○○○○○○○○○○○
READ
BANK,
COL
b
DOUT
n+1
○○○○○○○○○○○○○○○○○○○○
NOP
X=2 cycle
23
23
23
DOUT
n+2
○○○○○○○○○○○○○○○○○○○○
NOP
2
2
2
DOUT
n+3
T7
○○○○○○○○○○○○○○○○○○○○
NOP
12
12
12
DOUT
b
23
23
DON’T CARE
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Austin Semiconductor, Inc.
123456
123456
123456
123456
123456
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T0 T1 T2 T3 T4 T5
SDRAM
AS4SD4M16
COMMAND
ADDRESS
CLK
COMMAND
CLK
DQ
○○○○○○○○○○○○○○○○○○
READ
BANK,
COL
n
○○○○○○○○○○○○○○○○
READ
BANK,
COL
a
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
READ READ
BANK,
COL
D
OUT
n
BANK,
x
COL
D
OUT
a
m
CAS Latency = 2
T0 T1 T2 T3 T4 T5
○○○○○○○○○○○○○○○○○○
READ
○○○○○○○○○○○○○○○○
READ
○○○○○○○○○○○○○○○○
READ READ NOP
○○○○○○○○○○○○○○○○○○
NOP
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
NOP
2
2
2
D
OUT
x
○○○○○○○○○○○○○○○○○○
NOP
23
23
23
D
OUT
m
T6
○○○○○○○○○○○○○○○○○○
○○○○○○○○○○○○○○○○○○
NOP
AS4SD4M16
Rev. 1.5 10/01
ADDRESS
DQ
23
BANK,
COL
BANK,
n
COL
BANK,
a
COL
BANK,
x
COL
m
D
OUT
n
23
23
D
OUT
a
CAS Latency = 3
NOTE: Each READ command may be to either bank. DQM is LOW.
Figure 8
RANDOM READ ACCESSES
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
2
2
2
D
OUT
x
23
23
23
D
OUT
m
23
23
DON’T CARE
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