AUSTN AS4LC1M16883C Datasheet

AUSTIN SEMICONDUCTOR, INC.

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

DRAM

AVAILABLE AS MILITARY
SPECIFICATIONS

• MIL-STD 883

• SMD Planned

FEATURES

• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages

• High-performance CMOS silicon-gate process

• Single +3.3V ±0.3V power supply

• All device pins are TTL-compatible

• Refresh modes: ?R?A/S ONLY, ?C?A/S-BEFORE-?R?A/S (CBR),
HIDDEN

• BYTE WRITE access cycles

• 1,024-cycle refresh (10 row-, 10 column-addresses)

• Low power, 0.3mW standby; 180mW active, typical

• Extended Data-Out (EDO) PAGE access cycle

• 5V-tolerant I/Os (5.5V maximum V

OPTIONS MARKING

• Timing
60ns access (Contact Factory) -6
70ns access -7
80ns access -8

• Refresh Rate
Standard 16ms period None

• Packages
Ceramic SOJ ECJ No. 506
Ceramic Gull Wing ECG No. 604
Ceramic LCC EC No. 213

KEY TIMING PARAMETERS

SPEEDtRCtRACtPC

-6 105ns 60ns 25ns 30ns 15ns 12ns

-7 125ns 70ns 30ns 35ns 20ns 12ns

-8 150ns 80ns 40ns 40ns 20ns 20ns

GENERAL DESCRIPTION

The AS4LC1M16 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 con­figuration. The AS4LC1M16 has both BYTE WRITE and
WORD WRITE access cycles via two ?C?A/S pins (?C?A?S/L and
?C?A?S?H). These function in a similar manner to a single ?C?AS
of other DRAMs in that either ?C?A?S/L or ?C? A? S? H will generate

IH level)

t

AAtCACtCAS

1 MEG x 16 DRAM

3.3V, EDO PAGE MODE,
OPTIONAL EXTENDED REFRESH

PIN ASSIGNMENT (Top View)
44/50-Pin SOJ/LCC/Gull Wing

450mil

1

Vcc

2

DQ1

3

DQ2

4

DQ3

5

DQ4

6

Vcc

7

DQ5

8

DQ6

9

DQ7

10

DQ8

11

NC

15

NC

16

NC

17

WE

18

RAS

19

NC

20

NC

21

A0

22

A1

23

A2

24

A3

25

Vcc

an internal ?C?A/S.

The AS4LC1M16 ?C?A/S function and timing are deter­mined by the first ?C?A/S (?C?A?S/L or ?C?A?S?H) to transition LOW
and the last ?C?A/S to transition back HIGH. Use of only one
of the two results in a BYTE WRITE cycle. ?C?A?S/L transitioning
LOW selects an access cycle for the lower byte (DQ1-DQ8)
and ?C?A?S?H transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).

Each bit is uniquely addressed through the 20 address bits
during READ or WRITE cycles. These are entered 10 bits
(A0-A9) at a time. ?R?A/S is used to latch the first 10 bits and
?C?A/S the latter 10 bits. The ?C?A/S function also determines
whether the cycle will be a refresh cycle (?R?A/S ONLY) or an
active cycle (READ, WRITE or READ WRITE) once ?R?A/S
goes LOW.

Vss

50

DQ16

49

DQ15

48

DQ14

47

DQ13

46

Vss

45

DQ12

44

DQ11

43

DQ10

42

DQ9

41

NC

40

NC

36

CASL

35

CASH

34

OE

33

A9

32

A8

31

A7

30

A6

29

A5

28

A4

27

Vss

26

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
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AUSTIN SEMICONDUCTOR, INC.

,

,,

,,

,,,

,,

GENERAL DESCRIPTION (continued)

The ?C?A/S/L and ?C?A/S?H inputs internally generate a ?C?A/S

signal functioning in a similar manner to the single

?C?A/S input of other DRAMs. The key difference is each
?C?A/S input ( ?C?A/S/L and ?C?A/S?H ) controls its corresponding

8 DQ inputs during WRITE accesses. ?C?A/S/L controls DQ1
through DQ8 and ?C?A/S?H controls DQ9 through DQ16. The
two ?C?A/S controls give the MT4LC1M16E5(S) both BYTE
READ and BYTE WRITE cycle capabilities.

A logic HIGH on ?W/E dictates READ mode while a logic
LOW on ?W/E dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or ?C?A/S
(?C?A/S/L or ?C?A/S/H), whichever occurs last. An EARLY WRITE
occurs when WE is taken LOW prior to either ?C?A/S falling.
A LATE WRITE or READ-MODIFY-WRITE occurs when
WE falls after ?C?A/S (?C?A/S/L or ?C?A/S/H) was taken LOW.
During EARLY WRITE cycles, the data-outputs (Q) will
remain High-Z regardless of the state of ?O/E. During LATE
WRITE or READ-MODIFY-WRITE cycles, ?O/E must be
taken HIGH to disable the data-outputs prior to applying
input data. If a LATE WRITE or READ-MODIFY-WRITE is
attempted while keeping ?O/E LOW, no write will occur, and
the data-outputs will drive read data from the accessed
location.

The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
?O/E and ?W/E.

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

PAGE ACCESS

PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-address­defined page boundary. The PAGE cycle is always initiated
with a row -address strobed-in by ?R?A/S followed by a col­umn-address strobed-in by ?C?A/S. ?C?A/S may be toggled-in
by holding ?R?A/S LOW and strobing-in different column­addresses, thus executing faster memory cycles. Returning
?R?A/S HIGH terminates the PAGE MODE of operation.

EDO PAGE MODE

The AS4LC1M16 provides EDO PAGE MODE which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
?C?A/S returns HIGH. EDO provides for ?C?A/S precharge time

t

CP) to occur without the output data going invalid. This

(
elimination of ?C?A/S output control provides for pipeline
READs.

FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
?C?A /S. EDO-PAGE-MODE DRAMs operate similar to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after ?C?A/S goes HIGH during READs,
provided ?R?A/S and ?O/E are held LOW. If ?O/E is pulsed while
?R?A/S and ?C?A/S are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If ?O/E is toggled or
pulsed after ?C?A/S goes HIGH while ?R?A/S remains LOW, data
will transition to and remain High-Z (refer to Figure 1).

RAS

CASL/CASH

ADDR

DQ

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

OE

V

IL

ROW

OPEN

COLUMN (A)

VALID DATA (A)

t

OD

t

OES

The DQs go back to
Low-Z if

t

OE

t

OES is met.

COLUMN (B)

VALID DATA (A)

VALID DATA (B)

t

OD

t

OEHC

The DQs remain High-Z
until the next CAS cycle

t

OEHC is met.

if

COLUMN (C)

VALID DATA (C)

t

OEP

The DQs remain High-Z
until the next CAS cycle

t

OEP is met.

if

COLUMN (D)

t

OD

VALID DATA (D)

DON’T CARE

UNDEFINED

Figure 1

OUTPUT ENABLE AND DISABLE

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AUSTIN SEMICONDUCTOR, INC.

,

,

,

,,,

EDO PAGE MODE (continued)

?W/E can also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.

During an application, if the DQ outputs are wire OR’d,

?O/E must be used to disable idle banks of DRAMs. Alterna-

V

IH

RAS

V

IL

V

IH

CASL/CASH

V

IL

V

ADDR

IH

V

IL

V

IOH

DQ

V

IOL

V

IH

WE

V

IL

V

IH

OE

V

IL

ROW

OPEN

COLUMN (A)

VALID DATA (A)

t

WHZ

t

WPZ

The DQs go to High-Z if WE falls, and if tWPZ is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

tively, pulsing ?W/E to the idle banks during ?C?A/S HIGH time
will also High-Z the outputs. Independent of ?O/E control,
the outputs will disable after
from the rising edge of ?R?A/S or ?C?A/S, whichever occurs last.

COLUMN (B)

VALID DATA (B)

t

OFF, which is referenced

COLUMN (C)

INPUT DATA (C)

t

WHZ

WE may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).

COLUMN (D)

Figure 2

??

//

?W

/E CONTROL OF DQs

??

//

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020

2-95

DON’T CARE

UNDEFINED

AUSTIN SEMICONDUCTOR, INC.

BYTE ACCESS CYCLE

The BYTE WRITEs and BYTE READs are determined by
the use of ?C?A/S/L and ?C?A/S?H. Enabling ?C?A/S/L will select a
lower BYTE access (DQ1-DQ8). Enabling ?C?A/S?H will select
an upper BYTE access (DQ9-DQ16). Enabling both ?C?A/S/L
and ?C?A/S?H selects a WORD WRITE cycle.

The AS4LC1M16 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the excep­tion of the / ?C?A/S inputs. Figure 3 illustrates the BYTE WRITE
and WORD WRITE cycles.

Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A ?C?A/S precharge
must be satisfied prior to changing modes of operation
between the upper and lower bytes. For example, an EARLY

WORD WRITE LOWER BYTE WRITE

RAS

CASL

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

WRITE on one byte and a LATE WRITE on the other byte is
not allowed during the same cycle. However, an EARLY
WRITE on one byte and, after a ?C?A/S precharge has been
satisfied, a LATE WRITE on the other byte is permissable.

REFRESH

Preserve correct memory cell data by maintaining power
and executing a ?R?A/S cycle (READ, WRITE) or ?R?A/S refresh
cycle (?R?A/S ONLY, CBR, or HIDDEN) so that all 1,024
combinations of ?R?A/S addresses are executed at least every
16ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic ?R?A/S addressing.

CASH

WE

STORED

LOWER BYTE

(DQ1-DQ8)

OF WORD

UPPER BYTE

(DQ9-DQ16)

OF WORD

INPUT

DATA

0
0
1
0
0
0
0
0

X
X
X
X
X
X
X
X

INPUT

DATA

1
0
1
0
1
1
1
1

DATA

1
1
0
1
1
1
1
1

0
1
0
1
0
0
0
0

X = NOT EFFECTIVE (DON'T CARE)

STORED

DATA

0
0
1
0
0
0
0
0

1
0
1
0
1
1
1
1

STORED

DATA

0
0
1
0
0
0
0
0

1
0
1
0
1
1
1
1

INPUT
DATA

1
1
0
1
1
1
1
1

X
X
X
X
X
X
X
X

ADDRESS 1ADDRESS 0

INPUT

DATA

STORED

DATA

1
1
0
1
1
1
1
1

1
0
1
0
1
1
1
1

Figure 3

WORD AND BYTE WRITE EXAMPLE

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020

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AUSTIN SEMICONDUCTOR, INC.

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

FUNCTIONAL BLOCK DIAGRAM

WE

CASL

CASH

NO. 2 CLOCK
GENERATOR

COLUMN­ADDRESS

10

BUFFER

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

CONTROLLER

10

BUFFERS (10)

REFRESH

REFRESH
COUNTER

ROW-

ADDRESS

CAS

10

10

10

ROW

DECODER

1024

DATA-IN BUFFER

COLUMN

DECODER

1024

SENSE AMPLIFIERS

I/O GATING

1024 x 16

1024 x 1024 x 16

MEMORY

ARRAY

DQ1

16

DQ16

DATA-OUT

BUFFER

16

16

OE

RAS

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020

NO. 1 CLOCK
GENERATOR

2-97

Vcc
Vss

AUSTIN SEMICONDUCTOR, INC.

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

TRUTH TABLE

ADDRESSES

t

FUNCTION ?R?A/S ?C?A/S/L ?C?A/S/H ?W/E ?O/E

Standby H H>XH>X X X X X High-Z
READ: WORD L L L H L ROW COL Data-Out
READ: LOWER BYTE L L H H L ROW COL Lower Byte,

READ: UPPER BYTE L H L H L ROW COL Lower Byte, Data-Out

WRITE: WORD L L L L X ROW COL Data-In
(EARLY WRITE)

WRITE: LOWER L L H L X ROW COL Lower Byte, Data-In
BYTE (EARLY) Upper Byte, High-Z

WRITE: UPPER L H L L X ROW COL Lower Byte, High-Z
BYTE (EARLY) Upper Byte, Data-In

READ WRITE L L L H>LL>H ROW COL Data-Out, Data-In 1, 2
EDO-PAGE-MODE 1st Cycle L H>LH>L H L ROW COL Data-Out 2
READ 2nd Cycle L H>LH>L H L n/a COL Data-Out 2

Any Cycle L L>HL>H H L n/a n/a Data-Out 2
EDO-PAGE-MODE 1st Cycle L H>LH>L L X ROW COL Data-In 1
WRITE 2nd Cycle L H>LH>L L X n/a COL Data-In 1
EDO-PAGE-MODE 1st Cycle L H>LH>LH>LL>H ROW COL Data-Out, Data-In 1, 2
READ-WRITE 2nd Cycle L H>LH>LH>LL>H n/a COL Data-Out, Data-In 1, 2
HIDDEN READ L>H>L L L H L ROW COL Data-Out 2
REFRESH WRITE L>H>L L L L X ROW COL Data-In 1, 3
?R?A/S-ONLY REFRESH L H H X X ROW n/a High-Z
CBR REFRESH H>L L L H X X X High-Z 4

t

R

C DQs NOTES

Upper Byte, Data-Out

Upper Byte

NOTE: 1. These WRITE cycles may also be BYTE WRITE cycles (either ?C?A/S/L or ?C?A/S/H active).

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020

2. These READ cycles may also be BYTE READ cycles (either ?C?A/S/L or ?C?A/S/H active).

3. EARLY WRITE only.

4. Only one ?C?A/S must be active (?C?A/S/L or ?C?A/S/H).

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AUSTIN SEMICONDUCTOR, INC.

AS4LC1M16 883C

1 MEG x 16 DRAM

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC pin Relative to VSS .............. -1.0V to +4.6V

Voltage on NC, Inputs or I/O pins

Relative to Vss ................................................. -1.0V to +5.5V

Operating Temperature, T

...................................................................... T

Storage Temperature................................... -55°C to +150°C

(ambient) ..... TA(MIN)=-55°C

A

(MAX)=125°C

C

Power Dissipation ............................................................. 1W

Short Circuit Output Current ..................................... 50mA

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(Notes: 1, 2, 3) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VCC 3.0 3.6 V
Input High (Logic 1) Voltage, all inputs (including NC pins) VIH 2.0 VCC+1 V
Input Low (Logic 0) Voltage, all inputs (including NC pins) VIL -1.0 0.8 V
INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ 5.5V VCC = 3.6V II -2 2 µA4
(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT (Q is disabled; 0V ≤ VOUT ≤ 5.5V) VCC=3.6V IOZ -10 10 µA
OUTPUT LEVELS V

Output High Voltage (I
Output Low Voltage (I

OUT = -2.0mA)

OUT = 2.0mA) VOL 0.4 V

*Stresses greater than those listed under “Absolute Maxi­mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi­cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

OH 2.4 V

MAX

PARAMETER/CONDITION SYMBOL -6 -7 -8 UNITS NOTES

STANDBY CURRENT: (TTL) (?R?A/S = ?C?A/S = VIH)ICC1 22 2mA
STANDBY CURRENT: (CMOS) I

CC2 11 1mA

(?R?A/S = ?C?A/S = other inputs = VCC -0.2V)
OPERATING CURRENT: Random READ/WRITE

Average power supply current I

CC3 170 155 140 mA 5, 6

(?R?A/S, ?C?A/S address cycling: tRC = tRC [MIN])
OPERATING CURRENT: EDO PAGE MODE

Average power supply current I

CC4 130 120 110 mA 5, 6

(?R?A/S = VIL, ?C?A/S, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: ?R?A/S ONLY

Average power supply current I

CC5 160 145 130 mA 5, 6

(?R?A/S cycling, ?C?A/S=VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR

Average power supply current I

CC6 150 140 130 mA 5, 7

(?R?A/S, ?C?A/S address cycling: tRC = tRC [MIN])

AS4LC1M16 Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 3/97
DS000020

2-99