AUSTIN SMJ44C251B-10, SMJ44C251B-12 Datasheet

a(R)

a(C)

a(SQ)

a(SE)

’44C251B-10 100 ns 25 ns 30 ns 20 ns ’44C251B-12 120 ns 30 ns 35 ns 25 ns

Class B High-Reliability Processing

DRAM: 262144 Words × 4 Bits SAM: 512 Words × 4 Bits

Single 5-V Power Supply (±10% Tolerance)

Dual Port Accessibility–Simultaneous and Asynchronous Access From the DRAM and SAM Ports

Bidirectional-Data-Transfer Function Between the DRAM and the Serial-Data Register

4 × 4 Block-Write Feature for Fast Area Fill Operations; As Many as Four Memory Address Locations Written per Cycle From an On-Chip Color Register

Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design

Enhanced Page-Mode Operation for Faster Access

CAS-Before-RAS (CBR) and Hidden Refresh Modes

All Inputs/Outputs and Clocks Are TTL Compatible

Long Refresh Period

Every 8 ms (Max)

Up to 33-MHz Uninterrupted Serial-Data Streams

3-State Serial I/Os Allow Easy Multiplexing of Video-Data Streams

512 Selectable Serial-Register Starting Locations

Packaging: – 28-Pin J-Leaded Ceramic Chip Carrier

Package (HJ Suffix)

– 28-Pin Leadless Ceramic Chip Carrier

Package (HM Suffix)

– 28-Pin Ceramic Sidebrazed DIP

(JD Suffix)

– 28-Pin Zig-Zag In-Line (ZIP), Ceramic

Package (SV Suffix)

Split Serial-Data Register for Simplified Real-Time Register Reload

description

The SMJ44C251B multiport video RAM is a high-speed, dual-ported memory device. It consists of a dynamic random-access memory (DRAM) organized as 262144 words of 4 bits each interfaced to a serial-data register or serial-access memory (SAM) organized as 512 words of 4 bits each. The SMJ44C251B supports three types of operation: random access to and from the DRAM, serial access to and from the serial register, and bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer operations, the SMJ44C251B can be accessed simultaneously and asynchronously from the DRAM and SAM ports.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

pinouts

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SC SDQ0 SDQ1

DQ0 DQ1

GND

A8 A6 A5 A4

SDQ3 SDQ2

DQ3 DQ2 DSF

QSF A0 A1 A2 A3 A7

JD PACKAGE (TOP VIEW)

RAS

TRG

CAS

DSF DQ3

SDQ2

SDQ0

TRG

GND

A8 A5

DQ1

DQ2 SE SDQ3 SC SDQ1 DQ0 W RAS A8 A4

1 3 5 7 9 11 13 15 17 19 21 23 25 27

2 4 6

8 10 12 14 16 18 20 22 24 26 28

SV PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

27 26 25 24 23 22 21 20 19 18 17 16 15

SC SDQ0 SDQ1

TRG DQ0 DQ1

GND

RAS

A8 A6 A5 A4

SDQ3 SDQ2 SE DQ3 DQ2 DSF CAS QSF A0 A1 A2 A3 A7

HM PACKAGE

(TOP VIEW)

A3 A1

QSF

A7 A2 A0 CAS

1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SC SDQ0 SDQ1

DQ0 DQ1

GND

A8 A6 A5 A4

SDQ3 SDQ2

DQ3 DQ2 DSF

QSF A0 A1 A2 A3 A7

HJ PACKAGE (TOP VIEW)

RAS

TRG

CAS

description (continued)

During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial data register. The 512 × 4-bit serial-data register can be loaded from the memory row (transfer read), or the contents of the 512 × 4-bit serial-data register can be written to the memory row (transfer write).

The SMJ44C251B is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can be achieved by the device’s 4 × 4 block-write mode. The block-write mode allows four bits of data (present in an on-chip color-data register) to be written to any combination of four adjacent column-address locations. As many as 16 bits of data can be written to memory during each CAS

cycle time. Also on the DRAM port, a write mask or a write-per-bit feature allows masking any combination of the four input/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles. The mask register eliminates having to provide mask data on every mask-write cycle.

The SMJ44C251B offers a split-register transfer read (DRAM to SAM) feature for the serial tester (SAM port). This feature enables real-time register reload implementation for truly continuous serial data streams without critical timing requirements. The register is divided into a high half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array . For applications not requiring real-time register reload (for example, reloads done during CRT retrace periods), the single-register mode of operation is retained to simplify design. The SAM can also be configured in input mode, accepting serial data from an external device. Once the serial register within the SAM is loaded, its contents can be transferred to the corresponding column positions in any row in memory in a single memory cycle.

The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial rates up to 33 MHz. During the split-register mode of operation, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF , is included to indicate which half of the serial register is active at any given time in the split-register mode.

All inputs, outputs, and clock signals on the SMJ44C251B are compatible with Series 54 TTL devices. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility.

SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

description (continued)

Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup, row-address hold, and address multiplex is eliminated, and a memory cycle time reduction of up to 3× can be achieved, compared to minimum RAS

cycle

times. The maximum number of columns that can be accessed is determined by the maximum RAS

low time and page-mode cycle time used. The SMJ44C251B allows a full page (512 cycles) of information to be accessed in read, write, or read-modify-write mode during a single RAS

-low period using relatively conservative

page-mode cycle times. The SMJ44C251B employs state-of-the-art technology for very high performance combined with improved

reliability . For surface mount technology , the SMJ44C251B is offered in a 28-pin J-leaded chip carrier package (HJ suffix) or a 28-pin leadless ceramic chip carrier package (HM suffix). The SMJ44C251B is offered in a 28-pin 400-mil dual-in-line ceramic sidebrazed package (JD suffix) or a 28-pin ZIP ceramic package (SV suffix) for through-hole insertion. The L suffix device is rated for operation from 0°C to 70°C. The M suffix device is rated for operation from – 55°C to 125°C.

The SMJ44C251B and other multiport video RAMs are supported by a broad line of video/graphic processors from Texas Instruments, including the SMJ34010 and the SMJ34020 graphics processors.

functional block diagram

Column Decoder

Sense Amplifier

Split Register

Data Transfer

Gate

Serial Data

Pointer

W/B

Unlatch

W/B

Latch

Address

Mask

Write-

Per-Bit

Control

MUX

QSF

DQ0 DQ1 DQ2 DQ3

DSF

SDQ0 SDQ1 SDQ2 SDQ3

A0 A1 A2 A3 A4 A5 A6 A7 A8

RAS CAS TRG W SC SE

O u

t p u

B u

f f

I n p u

B u

f f

I n p u

B u

f f

S p

e c i a l

F u n c

i o n

L o g

S e r

O u

t p u

B u

f f

C o

S e r

I n p u

B u

f f

R o w

D e c o d e

C o

l u m n

B u

f f

R o w

B u

f f

R e

r e s h

C o u n

i m

i n g

e n e

S e

r i

d d

r e s s

C o u n

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

Function Table

RAS FALL

CAS

FALL

ADDRESS DQ0–DQ3

FUNCTION

CAS TRG W‡DSF SE DSF RAS CAS RAS

CAS

TYPE

†

CBR refresh L X X X X X X X X X R Register-to-memory transfer

(transfer write)

H L L X L X

Row

Addr

Tap

Point

X X T

Alternate transfer write (independent of SE

)

H L L H X X

Row Addr

Tap

Point

X X T

Serial-write-mode enable (pseudo-transfer write)

H L L L H X

Refresh

Addr

Tap

Point

X X T

Memory-to-register transfer (transfer read)

H L H L X X

Row Addr

Tap

Point

X X T

Split-register-transfer read (must reload tap)

H L H H X X

Row Addr

Tap

Point

X X T

Load and use write mask, Write data to DRAM

H H L L X L

Row Addr

Col

AddrDQMask

Valid Data

Load and use write mask, Block write to DRAM

H H L L X H

Row Addr

Blk Addr

A2–A8DQMask

Col

Mask

Persistent write-per-bit, Write data to DRAM

H H L H X L

Row Addr

Col

Addr

Valid Data

Persistent write-per-bit, Block write to DRAM

H H L H X H

Row Addr

Blk Addr

A2–A8

Col

Mask

Normal DRAM read/write (nonmasked)

H H H L X L

Row Addr

Col

Addr

Valid Data

Block write to DRAM (nonmasked)

H H H L X H

Row Addr

Blk Addr

A2–A8

Col

Mask

Load write mask H H H H X L

Refresh

Addr

X X

Mask

Load color register H H H H X H

Refresh

Addr

X X

Color

Data

Legend: H = High L = Low X = Don’t care

†

R = random access operation; T = transfer operation

‡

In persistent write-per-bit function, W

must be high during the refresh cycle.

DQ0–DQ3 are latched on the later of W

or CAS falling edge. Col Mask = H: Write to address/column location enabled DQ Mask = H: Write to I/O enabled

SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation

Depending on the type of operation chosen, the signals of the SMJ44C251B perform different functions. Table 1 summarizes the signal descriptions and the operational modes they control.

Table 1. Detailed Signal Description Versus Operational Mode

PIN DRAM TRANSFER SAM

A0–A8 Row, column address Row, tap address CAS Column enable, output enable Tap-address strobe DQi DRAM data I/O, write mask bits DSF Block-write enable

Persistent write-per-bit enable Color-register load enable

Split-register enable Alternate write-transfer enable

RAS Row enable Row enable SE Serial-in mode enable Serial enable SC Serial clock SDQ Serial-data I/O TRG Q output enable Transfer enable W Write enable, write-per-bit select Transfer-write enable

QSF

Split register

Active status NC/GND Make no external connection or tie to system VSS. V

5-V supply (typical)

Device ground

The SMJ44C251B has three kinds of operations: random-access operations typical of a DRAM, transfer operations from memory arrays to the SAM, and serial-access operations through the SAM port. The signals used to control these operations are described here, followed by discussions of the operations themselves.

address (A0–A8)

For DRAM operation, 18 address bits are required to decode one of the 262144 storage cell locations. Nine row-address bits are set up on A0–A8 and latched onto the chip on the falling edge of RAS

. Nine

column-address bits are set up on A0–A8 and latched onto the chip on the falling edge of CAS

. All addresses

must be stable on or before the falling edges of RAS

and CAS.

During the transfer operation, the states of A0–A8 are latched on the falling edge of RAS

to select one of the

512 rows where the transfer occurs. T o select one of 512 tap points (starting positions) for the serial-data input or output, the appropriate 9-bit column address (A0–A8) must be valid when CAS

falls.

row-address strobe (RAS

)

RAS

is similar to a chip enable because all DRAM cycles and transfer cycles are initiated by the falling edge

of RAS

. RAS is a control input that latches the states of row address, W, TRG, SE, CAS, and DSF onto the chip

to invoke DRAM and transfer functions.

column-address strobe (CAS

)

CAS

is a control input that latches the states of column address and DSF to control DRAM and transfer functions.

When CAS

is brought low during a transfer cycle, it latches the new tap point for the serial-data input or output.

CAS

also acts as an output enable for the DRAM outputs DQ0–DQ3.

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

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output enable/transfer select (TRG)

TRG

selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as

RAS

falls. During DRAM operation, TRG functions as an output enable for the DRAM outputs DQ0–DQ3. For

transfer operation, TRG

must be brought low before RAS falls.

write-mask select, write enable (W

)

In DRAM operation, W

enables data to be written to the DRAM. W is also used to select the DRAM write-per-bit

mode. Holding W

low on the falling edge of RAS invokes the write-per-bit operation. The SMJ44C251B supports

both the normal write-per-bit mode and the persistent write-per-bit mode. For transfer operation, W

selects either a read-transfer operation (DRAM to SAM) or a write-transfer operation

(SAM to DRAM). During a transfer cycle, if W

is high when RAS falls, a read transfer occurs; if W is low, a write

transfer occurs.

special function select (DSF)

DSF is latched on the falling edge of RAS

or CAS, similar to an address. DSF determines which of the following

functions are invoked on a particular cycle:

Persistent write-per-bit

Block write

Split-register transfer read

Mask-register load for the persistent write-per-bit mode

Color-register load for the block-write mode

DRAM data I/O, write-mask data (DQ0–DQ3)

DRAM data is written via DQ terminals during a write or read-modify-write cycle. In an early-write cycle, W

brought low prior to CAS

and the data is strobed in by CAS with data setup and hold times referenced to this

signal. In a delayed-write or read-modify-write cycle, W

is brought low after CAS and the data is strobed in by

with data setup and hold times referenced to this signal.

The 3-state DQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state as long as CAS

and TRG are held high. Data does not appear at the outputs until both CAS and TRG are brought

low. Once the outputs are valid, they remain valid while CAS

and TRG are low. CAS or TRG going high returns the outputs to the high-impedance state. In a register-transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle.

The write-per-bit mask is latched into the device via the random DQ terminals by the falling edge of RAS

. This

mask selects which of the four random I/Os are written.

serial data I/O (SDQ0–SDQ3)

Serial inputs and serial outputs share common I/O terminals. Serial-input or serial-output mode is determined by the previous transfer cycle. If the previous transfer cycle was a read transfer, the data register is in serial-output mode. While in serial-output mode, data in SAM is accessed from the least significant bit to the most significant bit. The data registers operate modulo 512; so after bit 511 is accessed, the next bits to be accessed are 00, 01, 02, etc. If the previous transfer cycle was either a write transfer or a pseudo transfer, the data register is in serial-input mode and signal data can be input to the register.

serial clock (SC)

Serial data is accessed in or out of the data register on the rising edge of SC. The SMJ44C251B is designed to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency.

SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

serial enable (SE)

During serial-access operations SE

is used as an enable/disable for SDQ in both the input and output modes.

If SE

is held as RAS falls during a write-transfer cycle, a pseudo-transfer write occurs. There is no actual transfer,

but the data register switches from the output mode to the input mode.

no connect/ground (NC/GND)

NC/GND is reserved for the manufacturer’s test operation. It is an input and should be tied to system ground or left floating for proper device operation.

special function output (QSF)

During split-register operation the QSF output indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of SAM. When QSF is high, the serial-address pointer is accessing the higher (most significant) 256 bits of SAM. QSF changes state upon crossing the boundary between the two SAM halves in the split-register mode.

During normal transfer operations QSF changes state upon completing a transfer cycle. This state is determined by the tap point being loaded during the transfer cycle.

power up

T o achieve proper device operation, an initial pause of 200 µs is required after power-up, followed by a minimum of eight RAS

cycles or eight CBR cycles, a memory-to-register transfer cycle, and two SC cycles.

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

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random-access operation

The random-access operation functions are summarized in Table 2 and described in the following sections.

Table 2. Random-Access-Operation Functions

RAS FALL

CAS

FALL

ADDRESS DQ0–DQ3

FUNCTION

CAS TRG W†DSF SE DSF RAS CAS RAS

CAS

‡

CBR refresh L X X X X X X X X X Load and use write mask,

Write data to DRAM

H H L L X L

Row Addr

Col

Addr

Mask

Valid Data

Load and use write mask, Block write to DRAM

H H L L X H

Row Addr

Blk Addr

A2–A8DQMask

Col

Mask

Persistent write-per-bit, Write data to DRAM

H H L H X L

Row Addr

Col

Addr

Valid Data

Persistent write-per-bit, Block write to DRAM

H H L H X H

Row Addr

Blk Addr

A2–A8

Col

Mask

Normal DRAM read/write (nonmasked)

H H H L X L

Row Addr

Col

Addr

Valid Data

Block write to DRAM (nonmasked)

H H H L X H

Row Addr

Blk Addr

A2–A8

Col

Mask

Load write mask H H H H X L

Refresh

Addr

X X

Mask

Load color register H H H H X H

Refresh

Addr

X X

Color

Data

Legend: H = High L = Low X = Don’t care

†

In persistent write-per-bit function, W

must be high during the refresh cycle.

‡

DQ0–DQ3 are latched on the later of W

or CAS falling edge. Col Mask = H: Write to address/column location enabled DQ Mask = H: Write to I/O enabled

enhanced page mode

Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row address setup-and-hold and address multiplex. The maximum RAS

low time and the CAS page cycle time used determine the number of

columns that can be accessed. Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251B to operate at a

higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS transitions low. A valid column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS

. In this case, data can be obtained after t

a(C)

max

(access time from CAS

low), if t

a(CA)

max (access time from column address) has been satisfied.

refresh

There are three types of refresh available on the SMJ44C251B: RAS-only refresh, CBR refresh, and hidden refresh.

SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

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RAS-only refresh

A refresh operation must be performed to each row at least once every 8 ms to retain data. Unless CAS is applied, the output buffers are in the high-impedance state, so the RAS

-only refresh sequence avoids any

output during refresh. Externally generated addresses must be supplied during RAS

-only refresh. Strobing each

of the 512 row addresses with RAS

causes all bits in each row to be refreshed. CAS can remain high (inactive)

for this refresh sequence to conserve power.

CAS-before-RAS (CBR) refresh

CBR refresh is accomplished by bringing CAS low earlier than RAS. The external row address is ignored and the refresh row address is generated internally when using CBR refresh. Other cycles can be performed in between CBR cycles without disturbing the internal address generation.

hidden refresh

A hidden refresh is accomplished by holding CAS low in the DRAM-read cycle and cycling RAS. The output data of the DRAM-read cycle remains valid while the refresh is being carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh.

write-per-bit

The write-per-bit feature allows masking of any combination of the four DQs on any write cycle (see Figure 1). The write-per-bit operation is invoked only when W

is held low on the falling edge of RAS. If W is held high on

the falling edge of RAS

, write-per-bit is not enabled and the write operation is performed to all four DQs. The

SMJ44C251B offers two write-per-bit modes: the nonpersistent write-per-bit mode and the persistent write-per-bit mode.

nonpersistent write-per-bit

When DSF is low on the falling edge of RAS, the write mask is reloaded. A 4-bit code (the write-per-bit mask) is input to the device via the random DQ terminals and latched on the falling edge of RAS

. The write-per-bit mask

selects which of the four random I/Os are written and which are not. After RAS

has latched the on-chip

write-per-bit mask, input data is driven onto the DQ terminals and is latched on the later falling edge of CAS

. When a data low is strobed into a particular I/O on the falling edge of RAS, data is not written to that I/O. When

a data high is strobed into a particular I/O on the falling edge of RAS

, data is written to that I/O.

persistent write-per-bit

When DSF is high on the falling edge of RAS, the write-per-bit mask is not reloaded: it retains the value stored during the last write-per-bit mask reload. This mode of operation is known as persistent write-per-bit because the write-per-bit mask is persistent over an arbitrary number of write cycles. The write-per-bit mask reload can be done during the nonpersistent write-per-bit cycle or by the mask-register-load cycle.

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

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persistent write-per-bit (continued)

RAS

CAS

A0–A8

DSF

DQ0–

DQ3

Nonpersistant Write-Per-Bit

DQ Mask = H: Write to I/O enabled

= L: Write to I/O disabled

Write-Mask-Register Load Persistent Write-Per-Bit

DQ Mask Write DataDQ Mask Write Data

Figure 1. Example of Write-Per-Bit Operations

block write

The block-write mode allows data (present in an on-chip color register) to be written into four consecutive column-address locations. The 4-bit color register is loaded by the color-register-load cycle. Both write-per-bit modes can be applied in the block-write cycle. The block-write mode also offers the 4 × 4 column-mask capability.

load color register

The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high on the falling edges of RAS

and CAS. A 4-bit code is input to the color register via the random I/O terminals and

latched on the later of the falling edge of CAS

or W. After the color register is loaded, it retains data until power

is lost or until another load-color-register cycle is executed.

block write cycle

After the color register is loaded, the block-write cycle can begin as a normal DRAM write cycle with DSF held high on the falling edge of CAS

(see Figures 2, 3, and 4). When the block-write cycle is invoked, each data bit in the 4-bit color register is written to selected bits of the four adjacent columns of the corresponding random I/O.

During block-write cycles, only the seven most significant column addresses (A2–A8) are latched on the falling edge of CAS

. The two least significant addresses (A0–A1) are replaced by four DQ bits (DQ0–DQ3), which

are also latched on the later of the falling edge of CAS

or W. These four bits are used as a column mask, and they indicate which of the four column-address locations addressed by A2–A8 are written with the contents of the color register during the block-write cycle. DQ0 enables a write to column-address A1 = 0 (low), A0 = 0 (low); DQ1 enables a write to column-address A1 = 0 (low), A0 = 1 (high); DQ2 enables a write to column-address A1 = 1 (high), A0 = 0 (low); DQ3 enables a write to column-address A1 = 1 (high), A0 = 1 (high). A high logic level enables a write, and a low logic level disables the write. A maximum of 16 bits (4 × 4) can be written to memory during each CAS

cycle in the block-write mode.

SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

block write cycle (continued)

12323 2

4 5 65

Load-Color-Register Cycle Block-Write Cycle

†

(no DQ mask)

Block-Write Cycle

†

(load and use DQ mask)

Block-Write Cycle

†

(use previously

loaded DQ mask)

RAS

CAS

A0–A8

†

TRG

DSF

DQ0–DQ3

†

W must be low during the block-write cycle.

NOTE: DQ0–DQ3 are latched on the later of W

or CAS falling edge except in block 6 (see legend).

Legend:

1. Refresh address

2. Row address

3. Block address (A2 –A8)

4. Color-register data

5. Column-mask data

6. DQ-mask data. DQ0–DQ3 are latched on the falling edge of RAS

= don’t care

Figure 2. Example Block-Write Diagram Operations

DQ0

Write-Mask

N + 1

N + 2 N + 3

I/O3

I/O2

I/O1

I/O0

Block-Write

Enable

Load

Color

DQ1

DQ2

DQ3

MUX

4-of-512

Decode

1-of-4

Decode

A2–A8

Write

Select

Write

Select

Write

Select

Write

Select

Color

Load Write

Mask

Write

Enable

Data

MUX

Block-Write

Enable

A0–A1

Figure 3. Block-Write Circuit Block Diagram

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

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block write cycle (continued)

DQ MASK

COLUMN

MASK

COLOR

DATA

COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4

DQ0 1 0 0 DQ0 Masked 0 0 0 DQ1 1 1 0

Block Write

DQ1 Masked 0 0 0 DQ2 0 1 1 DQ2 Masked Masked Masked Masked DQ3 1 1 1 DQ3 Masked 1 1 1

Figure 4. Example of Block Write Operation With DQ Mask and Address Mask

transfer operation

Transfer operations between the memory arrays (DRAM) and the data registers (SAM) are invoked by bringing TRG

low before RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS, determine which transfer operation is invoked. Figure 5 shows an overview of data flow between the random and the serial interfaces.

DQ0–DQ3

Col 511

Col

Random-Access Port

Row

511

256

256-Bit Data Register

Transfer-

Control

Logic

Serial

Counter

Serial-

I/O

Control

TRG

DSF

Transfer-

Pass Gate

Col

255

Col

256

Memory Array

262 144 Bits

256

Transfer-

Pass Gate

A0–A8

SDQ0–SDQ3

256 256

256-Bit Data Register

MUX

TRG

Figure 5. Block Diagram Showing One Random and One Serial-I/O Interface

SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

transfer operation (continued)

As shown in Table 3, the SMJ44C251B supports five basic modes of transfer operation:

Alternate-write transfer (independent of the state of SE)

Memory-to-register transfer (pseudo-transfer write). Switches serial port from serial-out mode to serial-in mode. No actual data transfer takes place between the DRAM and the SAM.

Memory-to-register transfer (normal-read transfer, transfer entire contents of DRAM row to SAM)

Split-register-read transfer (divides the SAM into a low and a high half. Only one half is transferred to the SAM while the other half is read from the serial I/O port.)

Table 3. Transfer-Operation Functions

RAS FALL

CAS

FALL

ADDRESS DQ0–DQ3

FUNCTION

CAS TRG W DSF SE DSF RAS CAS RAS

CAS

H L L X L X

Row Addr

Tap

Point

X X

Alternate-write transfer (independent of SE

)

H L L H X X

Row Addr

Tap

Point

X X

Serial-write-mode enable (pseudo-transfer write)

H L L L H X

Refresh

Addr

Tap

Point

X X

Memory-to-register transfer (normal read transfer)

H L H L X X

Row Addr

Tap

Point

X X

Split-register-read transfer (must reload tap)

H L H H X X

Row Addr

Tap

Point

X X

Legend:

H = High L = Low X = Don’t care

write transfer

All write-transfer cycles (except the pseudo write transfer) transfer the entire content of SAM to the selected row

in the DRAM. To invoke a write-transfer cycle, W

must be low when RAS falls. There are three possible

write-transfer operations: normal-write transfer, alternate-write transfer, and pseudo-write transfer.

All write-transfer cycles switch the serial port to the serial-in mode.

normal-write transfer (SAM-to-DRAM transfer)

A normal-write transfer cycle loads the contents of the serial-data register to a selected row in the memory array .

TRG

, W, and SE are brought low and latched at the falling edge of RAS. Nine row-address bits (A0–A8) are

also latched at the falling edge of RAS

to select one of the 512 rows available as the destination of the data

transfer. The nine column-address bits (A0–A8) are latched at the falling edge of CAS

to select one of the 512

tap points in SAM that are available for the next serial input.

During a write-transfer operation before RAS

falls, the serial-input operation must be suspended after a

minimum delay of t

d(SCRL)

but can be resumed after a minimum delay of t

d(RHSC)

after RAS goes high

(see Figure 6).

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

normal-write transfer (SAM-to-DRAM transfer) (continued)

RAS

CAS

A0–A8

TRG

d(SCRL)

d(RHSC)

Row Tap Point

Figure 6. Normal-Write-Transfer-Cycle Timing

alternate-write transfer (refer to Figure 30)

When DSF is brought high and latched at the falling edge of RAS in the normal-write-transfer cycle, the alternate-write transfer occurs.

pseudo-write transfer (write-mode control) (refer to Figure 28)

T o invoke the pseudo-write transfer (write-mode control cycle), SE is brought high and latched at the falling edge of RAS

. The pseudo-write transfer does not actually invoke any data transfer but switches the mode of the serial

port from the serial-out (read) mode to the serial-in (write) mode. Before serial data can be clocked into the serial port via the SDQ terminals and the SC input, the SDQ terminals

must be switched into input mode. Because the transfer does not occur during the pseudo-transfer write, the row address (A0–A8) is in the don’t care state and the column address (A0–A8), which is latched on the falling edge of CAS

, selects one of the 512 tap points in the SAM that are available for the next serial input.

read transfer (DRAM-to-SAM transfer) (refer to Figure 7)

During a read-transfer cycle, data from the selected row in DRAM is transferred to SAM. There are two read-transfer operations: normal-read transfer and split-register-read transfer.

normal-read transfer

(refer to

Figure 7

)

The normal-read-transfer operation loads data from a selected row in DRAM into SAM. TRG is brought low and latched at the falling edge of RAS

. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS to select one of the 512 rows available for transfer. The nine column-address bits (A0–A8) are latched at the falling edge of CAS

to select one of the SAM’s 512 available tap points where the serial data is read out.

A normal-read transfer can be performed in three ways: early-load read transfer, real-time or midline-load read transfer, and late-load read transfer. Each of these offers the flexibility of controlling the TRG

trailing edge in

the read-transfer cycle (see Figure 7).

SMJ44C251B

262144 BY 4-BIT

MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

normal-read transfer (continued)

Row Tap Point Row Tap Point Row Tap Point

Bit

512

Tap

Bit

510

Bit

511

Tap

Bit

510

Bit

511

Tap

Bit

Early-Load Read Transfer Real-Time-Reload Read T ransfer Late-Load Read Transfer

RAS

CAS

A0–A8

TRG

Figure 7. Normal-Read-Transfer Timings

split-register-read transfer

In split-register-read-transfer operation, the serial-data register is split into halves. The low half contains bits 0–255, and the high half contains 256–511. While one half is being read out of the SAM port, the other half can be loaded from the memory array.

T o invoke a split-register read-transfer cycle, DSF is brought high, TRG

is brought low, and both are latched at

the falling edge of RAS

. Nine row-address bits (A0–A8) are also latched at the falling edge of RAS to select one of the 512 rows available for the transfer. The nine column-address bits (A0–A8) are latched at the falling edge of CAS

, where address bits A0–A7 select one of the 255 tap points in the specified half of SAM and address bit A8 selects which half is to be transferred. If A8 is a logic low, the low half is transferred. If A8 is a logic high, the high half is transferred. SAM locations 255 and 511 cannot be used as tap points.

A normal-read transfer must precede the split-register-read transfer to ensure proper operation. After the normal-read-transfer cycle, the first split-register read transfer can follow immediately without any minimum SC requirement. However, there is a minimum requirement of a rising edge of SC between split-register read-transfer cycles.

QSF indicates which half of the SAM is being accessed during serial-access operation. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of the SAM. When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. QSF changes state upon completing a normal-read-transfer cycle. The tap point loaded during the current transfer cycle determines the state of QSF . In split-register read-transfer mode, QSF changes state when a boundary between the two register halves is reached (see Figure 8 and Figure 9).

SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM

SGMS058A – MARCH 1995 – REVISED JUNE 1995

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

split-register-read transfer (continued)

RAS

CAS

DSF

TRG

QSF

Tap

Point N

d(GHQSF)

Read Transfer With Tap Point N

d(CLQSF)

Split-Register Read Transfer

Figure 8. Example of a Split-Register Read-Transfer Cycle After a Normal Read-Transfer Cycle

255

or 511

a(SCQSF)

RAS

CAS

DSF

TRG

QSF

Tap

Point N

Split-Register Read Transfer With Tap Point N

Split-Register Read Transfer

d(MSRL)

d(RHMS)

Figure 9. A Split-Register Read-Transfer Cycle After a Split-Register Read-Transfer Cycle

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AUSTIN SMJ44C251B-10, SMJ44C251B-12 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual