AUSTIN SMJ416400 Datasheet

’416400-70 70 ns 18 ns 35 ns 130 ns ’416400-80 80 ns 20 ns 40 ns 150 ns ’416400-10 100 ns 25 ns 45 ns 180 ns

Enhanced Page-Mode Operation for Faster

CAC

Memory Access

CAS-Before-RAS (CBR) Refresh

Long Refresh Period

4096 Cycles Refresh in 32 ms

3-State Unlatched Output

Low Power Dissipation

All Inputs, Outputs, and Clocks are TTL-Compatible

Operating Free-Air Temperature Range

– 55°C to 125°C

description

The SMJ416400 series is a set of high-speed 16777216-bit dynamic random-access memories (DRAMs), organized as 4194304 words of four bits each. The series employs technology for high performance, reliability, and low power.

These devices feature maximum RAS times of 70 ns, 80 ns, and 100 ns. All inputs, outputs, and clocks are compatible with series 54 TTL. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.

CYCLE

access

FNC PACKAGE

DQ1 DQ2

RAS

A1 1

A10

A0 A1 A2 A3

DQ1 DQ2

RAS

A1 1

NC NC

A10

A0 A1 A2 A3

(TOP VIEW)

DQ4 DQ3 CAS OE A9

A8 A7 A6 A5 A4 V

HKB PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A9 CAS DQ3

DQ1 RAS

A10

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SV PACKAGE

(TOP VIEW)

OE DQ2 V

DQ4 W A1 1 A0 A2 V

A4 A6 A8

DQ4 DQ3 CAS OE A9 NC NC A8 A7 A6 A5 A4 V

The SMJ416400 is offered in 450-mil 24/28-pin surface-mount small-outline leadless chip carrier (FNC suffix), 28-lead flatpack (HKB suffix), and 24-lead ZIP (SV suffix) packages. The packages are characterized for operation from –55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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PIN NOMENCLATURE

A0–A1 1 Address Inputs CAS DQ1–DQ4 Data In/Data Out NC No Internal Connection OE RAS W V

Column-Address Strobe

Output Enable Row-Address Strobe Write Enable 5-V Supply Ground

SMJ416400 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SGMS042E – MARCH 1992 – REVISED MARCH 1996

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FNC and HKB packages.

†

RAM 4096K × 4

/21D10

/21D11

C21[ROW]

C20[COLUMN]

A0 A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11

RAS

CAS

DQ1

DQ2 DQ3 DQ4

10 11 12 13 16 17 18 19 20 23 9 6

4 24

3 26 27

20D12/21D0

20D21/21D9

G23/[REFRESH ROW] 24[PWR DWN]

G24

23,20D 24 G25

A,22D

4 194 303

23C22

,25EN

A,Z26

functional block diagram

A0 A1

A11

‡

Column address 10 and column address 11 are not used.

ColumnAddress Buffers

Row-

Address

Buffers

‡

RAS CAS W OE

Timing and Control

Column Decode

Sense Amplifiers

256K Array 256K Array

256K Array

R o

256K Array

w D

e c o d e

256K Array

I/O

Buffers

4 of 32

Selection

Data-

Reg.

Data-

Out

Reg.

DQ1–DQ4

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SMJ416400

4194304 BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS042E – MARCH 1992 – REVISED MARCH 1996

operation

enhanced page mode

Page-mode operation allows faster memory access by keeping the same row address and strobing random column addresses onto the chip. The time required to set up and strobe row addresses for the same page is eliminated. The maximum number of columns that can be addressed is determined by t low width.

, the maximum RAS

RAS

The column-address buffers in this CMOS device are activated on the falling edge of RAS transparent or flow-through latch while CAS buffers and also serves as an output-enable. This feature allows the SMJ416400 to operate at a higher data bandwidth than conventional page-mode parts because retrieval begins as soon as the column address is valid, rather than when CAS column address can be presented immediately after row-address hold time has been satisfied, usually well in advance of the falling edge of CAS low) if tAA maximum (access time from column address) and t address for the next cycle is valid at the time CAS of t

address (A0–A11)

Twenty-two address bits are required to decode one of 4194304 storage-cell locations. Twelve row-address bits are set on inputs A0 through A11 and latched onto the chip by the row-address strobe, RAS column-address bits are set on A0 through A9 and latched onto the chip by the column-address strobe, CAS Row address A11 is required during a normal access and during RAS 4096 refresh cycles. All addresses must be stable on or before the falling edges of RAS to a chip-enable in that it activates the sense amplifiers as well as the row decoder. CAS activating the output buffer, as well as latching the address bits into the column-address buffer.

write enable (W

The read or write mode is selected through the write-enable (W and a logic low selects the write mode. W The data input is disabled when the read mode is selected. When W out remains in the high-impedance state for the entire cycle permitting a write operation that is independent of the state of OE

CPA

or t

CAC

)

goes low. The performance improvement is referred to as enhanced page mode. A valid

. In this case, data is obtained after t

. This permits an early-write operation to be completed with OE grounded.

is high. The falling edge of CAS latches the addresses into these

maximum (access time from CAS

CAC

have been satisfied. When the column

goes high, access time is determined by the later occurrence

can be driven from standard TTL circuits without a pullup resistor.

OEA

-only refresh as the device requires and CAS. RAS is similar

is used as a chip select,

) input. A logic high on W selects the read mode

goes low prior to CAS (early write), data

. They act as a

. Ten

data in/data out (DQ1–DQ4)

Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS or W strobes data into the on-chip data latch. In the early-write cycle, W is brought low prior to CAS and data is strobed in by CAS cycle, CAS

The 3-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two series 54 TTL loads. The output is in the high-impedance (floating) state until CAS the output becomes valid at the latest occurrence of t CAS does not change, but retains the state just read.

output enable (OE

controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance state. Bringing OE state. Both RAS in the low-impedance state, the output buffers remain in this state until either OE

is already low; data is strobed in by W with setup and hold times referenced to this signal.

going high returns it to the high-impedance state. In a delayed-write or read-modify-write cycle, the output

with setup and hold times referenced to this signal. In a delayed write or read-modify-write

is brought low. In a read cycle,

, tAA, t

RAC

)

low during a normal cycle activates the output buffers, putting them in the low-impedance

and CAS must be brought low for the output buffers to go into the low-impedance state. Once

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CAC

, or t

and remains valid while CAS is low.

CP A

or CAS is brought high.

SMJ416400 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SGMS042E – MARCH 1992 – REVISED MARCH 1996

refresh

A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected. A RAS

-only operation can be used by holding CAS at a high (inactive) level, conserving power as the output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS refresh. Hidden refresh can be performed by holding CAS the specified precharge period, similar to a RAS

-only refresh cycle except with CAS held low. Valid data is maintained at the output throughout the hidden-refresh cycle. An internal-refresh address provides the refresh address during hidden refresh.

CAS

-before-RAS (CBR) refresh

at VIL after a read operation and by cycling RAS after

-only

CBR refresh is used by bringing CAS falls (see parameter t

). For successive CBR refresh cycles, CAS can remain low while cycling RAS. For this

CHR

low earlier than RAS (see parameter t

) and holding it low after RAS

CSR

mode of refresh, the external addresses are ignored and the refresh address is generated internally.

power up

T o achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after full V (RAS

-only or CBR) cycle.

absolute maximum ratings over operating free-air temperature range

Supply voltage range, V

level is achieved. These eight initialization cycles need to include at least one refresh

†

– 1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on any pin (see Note 1) – 1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short-circuit output current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

– 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage 4.5 5 5.5 V

High-level input voltage 2.4 6.5 V

Low-level input voltage (see Note 2) –1 0.8 V

Operating free-air temperature – 55 125

NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

°C

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PARAMETER

TEST CONDITIONS

UNIT

Standby current

SMJ416400

4194304 BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS042E – MARCH 1992 – REVISED MARCH 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

’416400-70 ’416400-80 ’416400-10

MIN MAX MIN MAX MIN MAX

High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V

Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V

Input current (leakage)

Output current (leakage) VO = 0 V to VCC, CAS high ± 10 ± 10 ± 10 µA

Read- or write-cycle current

CC1

(see Note 3)

CC2

Average refresh current

CC3

(RAS

only or CBR)

Average page current

CC4

(see Note 4) Standby current

CC7

output enable

†

Minimum cycle, VCC = 5.5 V

NOTES: 3. Measured with a maximum of one address change while RAS

4. Measured with a maximum of one address change while CAS

†

capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5)

i(A)

i(RC)

i(OE)

i(W)

‡

Input capacitance for ZIP (SV suffix) package is 12 pF.

NOTE 5: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal

Input capacitance, A0–A11 Input capacitance, RAS and CAS Input capacitance, OE Input capacitance, W Output capacitance 14 pF

applied to the pin under test. All other pins are open.

‡

VI = 0 V to 6.5 V, All others = 0 V to V

VCC = 5.5 V, Minimum cycle 80 70 60 mA VIH = 2.4 V (TTL),

After one memory cycle, RAS

and CAS high

VIH = VCC – 0.05 V (CMOS), After one memory cycle, RAS

and CAS high

RAS cycling, CAS

high (RAS only),

RAS

low after CAS low (CBR) RAS low, CAS cycling 65 60 55 mA RAS = VIH, CAS = VIL,

Data out = enabled

PARAMETER MIN MAX UNIT

‡

= V = V

± 10 ± 10 ± 10 µA

2 2 2 mA

1 1 1 mA

80 70 60 mA

5 5 5 mA

9 pF 8 pF 8 pF 8 pF

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SMJ416400

PARAMETER

UNIT

4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY

SGMS042E – MARCH 1992 – REVISED MARCH 1996

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 6)

’416400-70 ’416400-80 ’416400-10

MIN MAX MIN MAX MIN MAX

CAC

CPA

RAC

OEA

OFF

OEZ

NOTES: 6. V alid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data

timing requirements over recommended ranges of supply voltage and operating free-air temperature

RWC

PRWC

RASP

RAS

CAS

ASC

ASR

RCS

CWL

RWL

WCS

WRP

CAH

RAH

RCH

RRH

NOTES: 8. All cycle times assume tT = 5 ns, referenced to V

Access time from column-address 35 40 45 ns Access time from CAS low 18 20 25 ns Access time from column precharge 40 45 50 ns Access time from RAS low 70 80 100 ns Access time from OE low 18 20 25 ns Output disable time after CAS high (see Note 7) 0 18 0 20 0 25 ns Output disable time after OE high (see Note 7) 0 18 0 20 0 25 ns

state prior to the specified access times as the outputs are driven when CAS

7. t

9. To assure tPC min, t

10. In a read-write cycle, t

11. In a read-write cycle, t

12. Referenced to the later of CAS

13. Either t

and t

OFF

Cycle time, random read or write (see Note 8) 130 150 180 ns Cycle time, read-write (see Note 8) 181 205 245 ns Cycle time, page mode read or write (see Notes 8 and 9) 45 50 55 ns Cycle time, page mode read-write (see Note 8) 96 105 120 ns Pulse duration, RAS low, page mode (see Note 10) 70 100 000 80 100 000 100 100 000 ns Pulse duration, RAS low, nonpage mode (see Note 10) 70 10 000 80 10 000 100 10 000 ns Pulse duration, CAS low (see Note 11) 18 10 000 20 10 000 25 10 000 ns Pulse duration, CAS high 10 10 10 ns Pulse duration, RAS high (precharge) 50 60 70 ns Pulse duration, W low 10 10 10 ns Setup time, column address before CAS going low 0 0 0 ns Setup time, row address before RAS going low 0 0 0 ns Setup time, data (see Note 12) 0 0 0 ns Setup time, W high before CAS going low 0 0 0 ns Setup time, W low before CAS going high 18 20 25 ns Setup time, W low before RAS going high 18 20 25 ns Setup time, W low before CAS going low

(early-write operation only) Setup time, W high before RAS going low (CBR refresh only) 10 10 10 ns Hold time, column address after CAS low 15 15 15 ns Hold time, data (see Note 12) 15 15 15 ns Hold time, row address after RAS low 10 10 10 ns Hold time, W high after CAS high (see Note 13) 0 0 0 ns Hold time, W high after RAS high (see Note 13) 0 0 5 ns

are specified when the outputs are no longer driven. The outputs are disabled by bringing either OE

OEZ

’416400-70 ’416400-80 ’416400-10

MIN MAX MIN MAX MIN MAX

and V

RRH

or t

should be ≥ tCP.

ASC

and t

RWD

and t

CWD

must be satisfied for a read cycle.

RCH

must be observed.

RWL

must be observed.

CWL

or W in write operations

IH(min)

IL(max)

goes low.

or CAS high.

0 0 0 ns

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UNIT

SMJ416400

4194304 BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SGMS042E – MARCH 1992 – REVISED MARCH 1996

timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued)

’416400-70 ’416400-80 ’416400-10

MIN MAX MIN MAX MIN MAX

WCH

WRH

OEH

ROH

RHCP

AWD

CHR

CRP

CSH

CSR

CWD

OED

RAD

RAL

CAL

RCD

RPC

RSH

RWD

CPW

REF

†

Transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 30 ns. This is assured by design but not tested.

NOTE 14: The maximum value is specified only to assure access time.

Hold time, W low after CAS low (early-write operation only) 15 15 15 ns Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns Hold time, OE command 18 20 25 ns Hold time, RAS referenced to OE 10 10 10 ns Hold time, RAS low after CAS precharge 40 45 50 ns Delay time, column address to W going low

(read-write operation only) Delay time, RAS low to CAS going high (CBR refresh only) 10 10 20 ns Delay time, CAS high to RAS going low 5 5 5 ns Delay time, RAS low to CAS going high 70 80 100 ns Delay time, CAS low to RAS going low (CBR refresh only) 5 5 10 ns Delay time, CAS low to W going low (read-write operation only) 46 50 60 ns Delay time, OE to data 18 20 25 ns Delay time, RAS low to column address (see Note 14) 15 35 15 40 15 55 ns Delay time, column address to RAS going high 35 40 45 ns Delay time, column address to CAS going high 35 40 45 ns Delay time, RAS low to CAS low (see Note 14) 20 52 20 60 20 75 ns Delay time, RAS high to CAS going low 0 0 0 ns Delay time, CAS low to RAS going high 18 20 25 ns Delay time, RAS low to W going low (read-write operation only) 98 110 135 ns Delay time, W going low after CAS precharge

(read-write operation only) Refresh time interval 32 32 32 ms Transition time 3

63 70 80 ns

†

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AUSTIN SMJ416400 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual