AUSTIN SMJ28F010B-12JDDM, SMJ28F010B-15JDDM, SMJ28F010B-20JDDM Datasheet
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Organization . . . 131072 × 8-Bit Flash
Memory
D
Pin Compatible With Existing 1M-bit
EPROMs
D
High-Reliability MIL-PRF-38535 Processing
D
VCC Tolerance ±10%
D
All Inputs/Outputs TTL Compatible
D
Maximum Access/Minimum Cycle Time
28F010B-12 120 ns
’28F010B-15 150 ns
’28F010B-20 200 ns
D
Industry-Standard Programming Algorithm
D
10000 Program/Erase-Cycle
D
Latchup Immunity of 250 mA on All Input
and Output Lines
D
Low Power Dissipation (VCC = 5.5 V)
–Active Write . . . 55 mW
–Active Read...165 mW
–Electrical Erase...82.5 mW
–Standby . . . 0.55 mW
(CMOS-Input Levels)
D
Military Temperature Range
– 55°C to 125°C
description
The SMJ28F010B is a 1048576-bit, programmable read-only memory that can be electrically bulk-erased and
reprogrammed. It is available in 10000 program/erase-endurance-cycle version.
The SMJ28F010B flash memory is offered in a 32-lead ceramic 600-mil side-braze dual in-line package (DIP)
(JDD suffix) and a leadless ceramic chip carrier (FE suffix).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
A0–A16 Address Inputs
DQ0–DQ7 Inputs (programming)/Outputs
E Chip Enable
G
Output Enable
NC No Internal Connection
V
CC
5-V Power Supply
V
PP
12-V Power Supply
V
SS
Ground
W
Write Enable
PIN NOMENCLATURE
JDD or FE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
PP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
V
CC
W
NC
A14
A13
A8
A9
A1 1
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
device symbol nomenclature
Temperature Range Designator
M=–55°C to 125°C
Package Designator
JDD = Ceramic Side-Braze
Dual- In-Line Package
Speed Designator
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
-12 JDD MSMJ28F010B
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
logic symbol
†
A
0
131 071
FLASH
MEMORY
131 072 × 8
16
0
G1
[PWR DWN]
G2
1, 2 EN (READ)
1C3 (WRITE)
A, 3D
∇ 4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
E
G
W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
31
13
14
15
17
18
19
20
21
A, Z4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the JDD package.
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram
Erase-Voltage Switch
V
PP
A0–A16
A
d
d
r
e
s
s
L
a
t
c
h
Column Decoder
Row Decoder
Chip-Enable and
Output-Enable
Logic
DQ0–DQ7
Program-Voltage
Switch
W
1048576-Bit
Array Matrix
To Array
STB
STB
Input/Output Buffers
E
G
State Control
Program/Erase
Stop Timer
Command Register
Data Latch
Column Gating
8
17
SMJ28F010B
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FLASH MEMORY
SGMS738 – APRIL 1998
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
operation
Table 1 lists the modes of operation for the device.
Table 1. Operation Modes
FUNCTION
†
MODE
V
PP
‡
(1)
E
(22)
G
(24)
A0
(12)
A9
(26)
W
(31)
DQ0–DQ7
(13–15, 17–21)
Read V
PPL
V
IL
V
IL
X X
V
IH
Data Out
Output Disable V
PPL
V
IL
V
IH
X X
V
IH
Hi-Z
Standby and Write Inhibit V
PPL
V
IH
X X X
X
Hi-Z
Read
Algorithm-Selection Mode V
V
V
V
IL
V
V
Manufacturer-Equivalent
Code 89h
g
PPLILIL
V
IH
ID
IH
Device-Equivalent Code B4h
Read V
PPH
V
IL
V
IL
X X
V
IH
Data Out
Read/
Output Disable V
PPH
V
IL
V
IH
X X
V
IH
Hi-Z
Write
Standby and Write Inhibit V
PPH
V
IH
X X X
X
Hi-Z
Write V
PPH
V
IL
V
IH
X X
V
IL
Data In
†
X can be VIL or VIH.
‡
V
PPL
≤ VCC + 2 V; V
PPH
is the programming voltage specified for the device. For more details, see the recommended operating conditions.
read/output disable
When the outputs of two or more SMJ28F010B devices are connected in parallel on the same bus, the output
of any particular device in the circuit can be read with no interference from the competing outputs of other
devices. Reading the output of the SMJ28F010B is enabled when a low-level signal is applied to the E
and G
pins. All other devices in the circuit must have their outputs disabled by applying a high-level signal to one of
these pins.
standby and write inhibit
Active I
CC
current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 µA with a
high CMOS level on E
. In this mode, all outputs are in the high-impedance state. The SMJ28F010B draws active
current when it is deselected during programming, erasure, or program/erase verification. It continues to draw
active current until the operation is terminated.
algorithm-selection mode
The algorithm-selection mode provides access to a binary code identifying the correct programming and erase
algorithms. This mode is activated when A9 ( pin 26) is forced to V
ID
. Two identifier bytes are accessed by
toggling A0. All other addresses must be held low.
A0 low selects the manufacturer-equivalent code 89h, and
A0 high selects the device-equivalent code B4h, as shown in Table 2.
Table 2. Algorithm-Selection Modes
PINS
IDENTIFIER
§
A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 HEX
Manufacturer-Equivalent Code V
IL
1 0 0 0 1 0 0 1 89
Device-Equivalent Code V
IH
1 0 1 1 0 1 0 0 B4
§
E =VIL, G = VIL, A1–A8 = VIL, A9 = VID, A10–A16 = VIL, VPP = V
PPL
.
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic 0. Then the entire chip is erased. At this point, the bits, which are now logic 1s, can be programmed
accordingly. See the fast-write and fast-erase algorithms for further details.
command register
The command register controls the program and erase functions of the SMJ28F010B. The algorithm-selection
mode can be activated using the command register in addition to the previously described method. When V
PP
is high, the contents of the command register and the function being performed can be changed. The command
register is written to when E
is low and W is pulsed low. The address is latched on the leading edge of the pulse,
while the data is latched on the trailing edge. Accidental programming or erasure is minimized because two
commands must be executed to invoke either operation. The command register is inhibited when V
CC
is below
the erase/write lockout voltage, V
LKO
.
power-supply considerations
Each device must have a 0.1-µF ceramic capacitor connected between V
CC
and VSS to suppress circuit noise.
Changes in current drain on V
PP
require it to have a bypass capacitor as well. Printed-circuit traces for both
power supplies should be appropriate to handle the current demand.
command definitions
The commands include read, algorithm-selection mode, set-up-erase, erase, erase-verify, set-up-program,
program, program-verify, and reset. Table 3 lists the command definitions with the required bus cycles.
Table 3. Command Definitions
REQUIRED
FIRST BUS CYCLE SECOND BUS CYCLE
COMMAND
BUS
CYCLES
OPERATION†ADDRESS DATA OPERATION†ADDRESS DATA
Read 1 Write X 00h Read RA RD
Algorithm-Selection Mode 3 Write X 90h Read
0000h
0001h
89h
B4h
Set-Up-Erase/Erase 2 Write X 20h Write X 20h
Erase-Verify 2 Write EA A0h Read X EVD
Set-Up-Program/Program 2 Write X 40h Write PA PD
Program-Verify 2 Write X C0h Read X PVD
Reset 2 Write X FFh Write X FFh
Legend:
EA Address of memory location to be read during erase verify
RA Address of memory location to be read
PA Address of memory location to be programmed. Address is latched on the falling edge of W
.
RD Data read from location RA during the read operation
EVD Data read from location EA during erase verify
PD Data to be programmed at location PA. Data is latched on the rising edge of W
.
PVD Data read from location PA during program verify
†
Modes of operation are defined in Table 1.
read command
Memory contents can be accessed while V
PP
is high or low. When VPP is high, writing 00h into the command
register invokes the read operation. When the device is powered up, the default contents of the command
register are 00h and the read operation is enabled. The read operation remains enabled until a different
command is written to the command register.
SMJ28F010B
131072 BY 8-BIT
FLASH MEMORY
SGMS738 – APRIL 1998
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
algorithm-selection mode command
The algorithm-selection mode is activated by writing 90h into the command register. The device-equivalent code
(B4h) is identified by the value read from address location 0001h, and the manufacturer-equivalent code (89h)
is identified by the value read from address location 0000h.
set-up-erase/erase commands
The erase-algorithm initiates with E
= VIL, W = VIL, G = VIH, VPP = V
PPH
, and VCC = 5 V . T o enter the erase mode,
write the set-up-erase command, 20h, into the command register. After the SMJ28F010B is in the erase mode,
writing a second erase command, 20h, into the command register invokes the erase operation. The erase
operation begins on the rising edge of W
and ends on the rising edge of the next W. The erase operation requires
at least 9.5 ms to complete before the erase-verify command, A0h, can be loaded.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a command is received.
program-verify command
The SMJ28F010B can be programmed sequentially or randomly , because it is programmed one byte at a time.
Each byte must be verified after it is programmed. The program-verify operation prepares the device to verify
the most recently programmed byte. To invoke the program-verify operation, C0h must be written into the
command register. The program-verify operation ends on the rising edge of W
.
While verifying a byte, the SMJ28F010B applies an internal margin voltage to the designated byte. If the true
data and programmed data match, programming continues to the next designated byte location; otherwise, the
byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte
programming.
erase-verify command
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, A0h, into the command register. This command causes
the device to exit the erase mode on the rising edge of W
. The address of the byte to be verified is latched on
the falling edge of W
. The erase-verify operation remains enabled until a command is written to the command
register.
T o determine whether all the bytes have been erased, the SMJ28F010B applies a margin voltage to each byte.
If FFh is read from the byte, all bits in the designated byte have been erased. The erase-verify operation
continues until all of the bytes have been verified. If FFh is not read from a byte, an additional erase operation
needs to be executed. Figure 2 shows the combination of commands and bus operations for electrically erasing
the SMJ28F010B.
set-up-program/program commands
The programming algorithm initiates with E
= VIL, W = VIL, G = VIH, VPP = V
PPH
, and VCC = 5 V . To enter the
programming mode, write the set-up-program command, 40h, into the command register. The programming
operation is invoked by the next write-enable pulse. Addresses are latched internally on the falling edge of W
,
and data is latched internally on the rising edge of W
. The programming operation begins on the rising edge
of W
and ends on the rising edge of the next W pulse. The program operation requires 10 µs for completion
before the program-verify command, C0h, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a command is received.
reset command
To reset the SMJ28F010B after set-up-erase-command or set-up-program-command operations without
changing the contents in memory, perofrm two consecutive writes of FFh into the command register. After
executing the reset command, the device defaults to the read mode.
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