AUSTIN SMJ27C256-15JM, SMJ27C256-17JM, SMJ27C256-20JM, SMJ27C256-25JM, SMJ27C256-30JM Datasheet

Austin Semiconductor, Inc.

UVEPROM

SMJ27C256

256K UVEPROM

UV Erasable Programmable
Read-Only Memory

A V AILABLE AS MILIT AR Y
SPECIFICA TIONS

• SMD 5962-86063

• MIL-STD-883

FEATURES

• Organized 32,768 x 8

• Single +5V ±10% power supply

• Pin-compatible with existing 256K ROM’s and
EPROM’s

• All inputs/outputs fully TTL compatible

• Power-saving CMOS technology

• Very high-speed SNAP! Pulse Programming

• 3-state output buffers

• 400-mV DC assured noise immunity with standarad
TTL loads

• Latchup immunity of 250 mA on all input and output
pins

• Low power dissipation (CMOS Input Levels)

PActive - 165mW Worst Case
PStandby - 1.7mW Worst Case (CMOS-input levels)

OPTIONS MARKING

• Timing

150ns access -1 5
170ns access -1 7
200ns access -2 0
250ns access -25
300ns access -3 0

• Package(s)

Ceramic DIP (600mils) J No. 110

• Operating Temperature Ranges

Military (-55oC to +125oC) M

For more products and information

please visit our web site at

www.austinsemiconductor .com

PIN ASSIGNMENT

(Top View)

32-Pin DIP (J)

(600 MIL)

V

1

PP

2

A12

3

A7

4

A6

5

A5

6

A4

7

A3

8

A2

9

A1

10

A0

11

DQ0

12

DQ1

13

DQ2

14

GND

Pin Name Function

A0 - A14 Address Inputs

DA0-DQ7 Inputs (programming)/Outputs

E\ Chip Enable/Power Down
G\ Output Enable

GND Ground

V
V

5V Supply

CC

13V Programming Power Supply

PP

Vcc

28

A14

27

A13

26

A8

25

A9

24

A11

23

G\

22

A10

21

E\

20

DQ7

19
18

DQ6

17

DQ5

16

DQ4

15

DQ3

GENERAL DESCRIPTION

The SMJ27C256 series is a set of 262,144 bit, ultraviolet­light erasable, electrically programmable read-only
memories. These devices are fabricated using power-saving
CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data
inputs) can be driven by Series 54 TTL circuits without the
use of external pullup resistors. Each output can drive one
Series 54 TTL circuit without external resistors. The data
outputs are 3-state for connecting multiple devices to a
common bus. The SMJ27C256 is pin-compatible with
28-pin 256K ROMs and EPROMs. It is offered in a 600mil
dual-in-line ceramic pagackage (J suffix) rated for operation
from -55°C to 125°C.
Because this EPROM operates from a single 5V supply (in
the read mode), it is ideal for use in microprocessor-based
systems. One other supply (13V) is needed for programming.
All programming signals are TTL level. This device is
programmable by the SNAP! Pulse programming algorithm.

The SNAP! Pulse programming algorithm uses a VPP of 13V
and a VCC of 6.5V for a nominal programming time of four

seconds. For programming outside the system, existing
EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.

SMJ27C256

Rev. 1.0 9/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

1

Austin Semiconductor, Inc.

9

FUNCTIONAL BLOCK DIAGRAM*

EPROM 32,768 x 8

10

A0
A1

8

A2
A3

6

A4
A5 DQ0

4

A6 DQ1
A7 DQ2

25

A8 DQ3

24

A9 DQ4

E\

G\

21
23

2

26

27
20

22

[PWR DWN]

&

A10 DQ5
A11 DQ6
A12 DQ7
A13
A14

A

EN

0

32,767

A
A
A
A
A
A
A
A

11
12
13
15

16
17
18
19

UVEPROM

SMJ27C256

* This symbol is in accordance with ANSI/IEEE std 91-1984 and IEC Publication 617-12.

OPERATION

The seven modes of operation for the SMJ27C256 are listed in Table 1. The read mode requires a single 5V supply. All
inputs are TTL level except for VPP during programming (13V for SNAP! Pulse), and (12V) on A9 for signature mode.

T ABLE 1. OPERA TION MODES

2

V

V

V

PP

V

CC

MODE*

PROGRAM

INHIBIT

IL

IH

V

IH

V

IL

V

PP

V

CC

V

IH

X

V

PP

V

CC

SIGNATURE MODE

V
V

V

ID

V

IL

CODE

MFG DEVICE

97

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

V

IL

V

IL
CC
CC

V
V

04

FUNCTION

(PINS)

E\ (20)
G\ (22)
V

(1) V

PP

V

(28) V

CC

READ

V
V

IL

IL
CC
CC

OUTPUT

DISABLE

V

IL

V

IH

V

CC

V

CC

STANDBY PROGRAMMING VERIFY

V

IH

X

V

CC

V

CC

A9 (24) X X X X X X
A0 (10) X X X X X X

DQ0-DQ7

(11-13, 15-19)

* X can be VIL or VIH.

SMJ27C256

Rev. 1.0 9/01

Data Out High-Z High-Z Data In Data Out High-Z

ID
IH

Austin Semiconductor, Inc.

UVEPROM

SMJ27C256

READ/OUTPUT DISABLE

When the outputs of two or more SMJ27C256s are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from the
competing outputs of the other devices. T o read the output of
the selected SMJ27C256, a low-level signal is applied to E\
and G\. All other devices in the circuit should have their
outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.

LA TCHUP IMMUNITY

Latchup immunity on the SMJ27C256 is a minimum of 250mA
on all inputs and outputs. This feature provides latchup
immunity beyond any potential transients at the printed
circuit board level when the EPROM is interfaced to industry
standard TTL or MOS logic devices. Input/output layout
approach controls latchup without compromising performance
or packing density.

POWER DOWN

Active ICC supply current can be reduced from 25mA
(SMJ27C256-15 through SMJ27C256-25) to 500µA (TTL­level inputs) or 300µA (CMOS-level inputs) by applying a high
TTL/CMOS signal to the E\ pin. In this mode all outputs are
in the high-impedance state.

ERASURE

Before programming, the SMJ27C256 is erased by exposing
the chip through the transparent lid to a high-intensity ultra­violet light (wavelength 2537 Å). EPROM erasure before
programming is necessary to ensure that all bits are in the
logic-high state. Logic-lows are programmed into the desired
locations. A programmed logic-low can be erased only by
ultraviolet light. The recommended minimum exposure dose
(UV intensity x exposure time) is 15W•s/cm2. A typical
12mW/cm2, filterless UV lamp erases the device in
21 minutes. The lamp should be located about 2.5cm above
the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains
the correct wavelength for erasure; therefore, when using the
SMJ27C256, the window should be covered with an opaque
label.

SNAP! PULSE PROGRAMMING

The SMJ27C256 EPROM is programmed by using the SNAP!
Pulse programming algorithm as illustrated by the flowchart
in Figure 1. This algorithm programs the device in a nominal
time of 4 seconds. Actual programming time varies as a
function of the programmer used.

Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed.

The SNAP! Pulse programming algorithm uses initial pulses
of 100 microseconds (µs) followed by a byte-verification step
to determine when the addressed byte has been successfully
programmed. Up to ten 100µs pulses per byte are provided
before a failure is recognized.

The programming mode is achieved when V
VCC= 6.5V, G\ = VIH, and E\ = VIL. More than one device can

be programmed when the devices are connected in parallel.
Locations can be programmed in any order. When the SNAP!
Pulse programming routine is completed, all bits are verified

with VCC = VPP = 5V.

PP

= 13V,

PROGRAM INHIBIT

Programming can be inhibited by maintaining a high-level
input on E\.

PROGRAM VERIFY

Programmed bits can be verified with VPP = 13V when
G\ = VIL, and E\ = VIH.

SIGNA TURE MODE

The signature mode provides access to a binary code
identifying the manufacturer and device type. This mode is
activated when A9 is forced to 12V ±0.5V. Two identifier

bytes are accessed by A0 (terminal 10); i.e., A0=VIL accesses
the manufacturer code, which is output on DQ0-DQ7; A0=V

accesses the device code, which is also output on DQ0-DQ7.
All other addresses must be held at VIL. Each byte contains
odd parity on bit DQ7. The manufacturer code for these
devices is 97h and the device code is 04h.

IH

SMJ27C256

Rev. 1.0 9/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

3

UVEPROM

SMJ27C256

Austin Semiconductor, Inc.

FIGURE 1. SNAP! PULSE PROGRAMMING FLOW CHART

START

Address = First Location

Increment

Address

VCC = 6.5V, VPP = 13V

Program One Pulse = tW = 100µs

Last

Address?

Yes

Address = First Location

X = 0

Program One Pulse = t

Verify

Byte

Pass

Fail

X = X+1

Increment Address

= 100µs

W(E)PR

No

X = 10?

Program

Mode

Interactive

Mode

SMJ27C256

Rev. 1.0 9/01

No

VCC = VPP = 5V ± 10%

Last

Address?

Yes

Compare
All Bytes

to Original

Data

Pass

Device Passed

Fail

4

Yes

Device Failed

Final

Verification

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.