AUSTIN MT4C1004J883C Datasheet
AUSTIN SEMICONDUCTOR, INC.
AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
MT4C1004J 883C
256K x 4 SRAM
4 MEG x 1 DRAM
DRAM
AVAILABLE AS MILITARY
SPECIFICATONS
• SMD 5962-90622
• MIL-STD-883
FEATURES
• Industry standard x1 pinout, timing, functions and
packages
• High-performance, CMOS silicon-gate process
• Single +5V ±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S
and HIDDEN
• FAST PAGE MODE access cycle
• CBR with ?W/E a HIGH (JEDEC test mode capable via
WCBR)
OPTIONS MARKING
• Timing
70ns access - 7
80ns access - 8
100ns access -10
120ns access -12
(CBR),
4 MEG x 1 DRAM
FAST PAGE MODE
PIN ASSIGNMENT (Top View)
18-Pin DIP
1
D
2
WE
3
RAS
4
*A10
5
A0
6
A1
7
A2
8
A3
9
Vcc
18
Vss
17
Q
16
CAS
15
A9
14
A8
13
A7
12
A6
11
A5
10
A4
20-Pin SOJ
20-Pin LCC
20-Pin Gull Wing
1
D
2
WE
3
RAS
4
NC
5
*A10
20-Pin ZIP
A9
1
Q
3
D
5
RAS
7
NC
9
A0
11
A2
13
Vcc
15
A5
17
A7
19
26
Vss
25
Q
24
CAS
23
NC
22
A9
CAS
2
Vss
4
WE
6
A10*
8
NC
10
A1
12
A3
14
A4
16
A6
18
A8
20
• Packages
9
18
Ceramic DIP (300 mil) CN No. 101
Ceramic DIP (400 mil) C No. 102
Ceramic LCC ECN No. 202
Ceramic SOJ ECJ No. 504
Vcc
A0
10
A1
11
A2
12
A3
13
A8
17
A7
16
A6
15
A5
14
A4
Ceramic ZIP CZ No. 400
Ceramic Gull Wing ECG No. 600
*Address not used for /R/A//S-ONLY REFRESH
GENERAL DESCRIPTION
The MT4C1004J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x1 configuration. During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits which are entered 11
bits (A0-A10) at a time. /R/A/S is used to latch the first 11 bits
and /C/A/S the latter 11 bits. A READ or WRITE cycle is
selected with the ?W/E input. A logic HIGH on ?W/E dictates
READ mode while a logic LOW on ?W/E dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
MT4C1004J 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000021
falling edge of ?W/E or /C/A/S, whichever occurs last. If ?W/E
goes LOW prior to /C/?A/S going LOW, the output pin remains
open (High-Z) until the next /C/A/S cycle. If ?W/E goes LOW
after data reaches the output pin, Q is activated and retains
the selected cell data as long as /C/A/S remains LOW (regardless of ?W/E or /R/A/S). This LATE-?W/E pulse results in a
READ-WRITE cycle. FAST PAGE MODE operations allow
faster data operations (READ, WRITE or READ-MODIFYWRITE) within a row-address (A0 -A10) defined page
2-23
AUSTIN SEMICONDUCTOR, INC.
AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
MT4C1004J 883C
256K x 4 SRAM
4 MEG x 1 DRAM
boundary. The FAST PAGE MODE cycle is always initiated with a row address strobed-in by /R/A/S followed by a
column address strobed-in by /C/A/S. /C/A/S may be toggled-in
by holding /R/A/S
LOW and strobing-in different column
addresses, thus executing faster memory cycles. Returning
/R/A/S HIGH terminates the FAST PAGE MODE operation.
Returning /R//A/S and /C/A/S HIGH terminates a memory cycle
and decreases chip current to a reduced standby level. Also,
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE
CAS
*EARLY-WRITE
DETECTION CIRCUIT
A10
NO. 2 CLOCK
GENERATOR
COLUMN
ADDRESS
11
11
BUFFER(11)
REFRESH
CONTROLLER
REFRESH
COUNTER
10
ROW
ADDRESS
BUFFERS (11)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
the chip is preconditioned for the next cycle during the /R/A/
S HIGH time. Memory cell data is retained in its correct state
by maintaining power and executing any /R?A/S cycle (READ,
WRITE, /R?A/S-ONLY, /C/A/S-BEFORE-/R/A/S, or HIDDEN
FRESH) so that all 1,024 combinations
of /R?A/S addresses
(A0 -A9) are executed at least every 16ms, regardless of
sequence. The /C?A/S - BEFORE-/R?A/S cycle will
refresh counter for automatic /R/?A/S addressing.
DATA IN
BUFFER
DATA OUT
BUFFER
1024
DECODER
COLUMN
DECODER
4096
SENSE AMPLIFIERS
I/O GATING
4096
MEMORY
ARRAY
11
1
10
ROW
RE-
invoke the
D
Q
RAS
NO. 1 CLOCK
GENERATOR
Vcc
Vss
*NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)
MT4C1004J 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000021
2-24
MT5C1005 883C
AUSTIN SEMICONDUCTOR, INC.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C
256K x 4 SRAM
4 MEG x 1 DRAM
TRUTH TABLE
ADDRESSES DATA
FUNCTION ?R/A/S ?C/A/S ?W/E
Standby H H>X X X X Don’t Care High-Z
READ L L H ROW COL Don’t Care Data Out
EARLY-WRITE L L L ROW COL Data In High-Z
READ-WRITE L L H>L ROW COL Data In Data Out
FAST-PAGE-MODE 1st Cycle L H>L H ROW COL Don’t Care Data Out
READ 2nd Cycle L H>L H n/a COL Don’t Care Data Out
FAST-PAGE-MODE 1st Cycle L H>L L ROW COL Data In High-Z
EARLY-WRITE 2nd Cycle L H>L L n/a COL Data In High-Z
FAST-PAGE-MODE 1st Cycle L H>LH>L ROW COL Data In Data Out
READ-WRITE 2nd Cycle L H>LH>L n/a COL Data In Data Out
/R/A/S-ONLY REFRESH L H X ROW n/a Don’t Care High-Z
HIDDEN READ L>H>L L H ROW COL Don’t Care Data Out
REFRESH WRITE L>H>L L L ROW COL Data In High-Z
/C/A/S-BEFORE-/R/A/S REFRESH H>L L H X X Don’t Care High-Z
t
R
t
C D (Data In) Q (Data Out)
MT4C1004J 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000021
2-25
AUSTIN SEMICONDUCTOR, INC.
AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
MT4C1004J 883C
256K x 4 SRAM
4 MEG x 1 DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin Relative to VSS ............... -1.0V to +7.0V
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
Lead Temperature (Soldering 5 Seconds)................. 270°C
Storage Temperature................................... -65°C to +150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (-55°C ≤ TA ≤ 125°C; VCC = 5V ± 10%)
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
Supply Voltage V
Input High (Logic 1) Voltage, All Inputs V
Input Low (Logic 0) Voltage, All Inputs V
INPUT LEAKAGE CURRENT
Any Input 0V ≤ VIN ≤ 5.5V VCC=5.5V II -5 5 µA
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT (Q is Disabled, 0V ≤ V
OUT ≤ 5.5V) VCC=5.5V IOZ -5 5 µA
OUTPUT LEVELS V
Output High Voltage (I
Output Low Voltage (I
OUT = -5mA)
OUT = 4.2mA) VOL 0.4 V
CC 4.5 5.5 V
IH 2.4 VCC+.5 V
IL -.5 0.8 V
OH 2.4 V
MAX
PARAMETER/CONDITION SYMBOL -7 -8 -10 -12 UNITS NOTES
STANDBY CURRENT (TTL) I
(/R/A/S = /C/A/S = V
IH)
STANDBY CURRENT (CMOS) I
(/R/A/S = /C/A/S = V
CC -0.2V; all other inputs = VCC -0.2V)
CC1 4444mA
CC2 2222mA
OPERATING CURRENT: Random READ/WRITE
Average Power-Supply Current I
(/R/A/S, /C/A/S, Address Cycling:
t
RC = tRC (MIN))
CC3 85 75 65 65 mA 3, 4
OPERATING CURRENT: FAST PAGE MODE
Average Power-Supply Current I
(/R/A/S = V
IL, /C/A/S, Address Cycling:
t
PC = tPC (MIN))
CC4 60 50 45 40 mA 3, 4
REFRESH CURRENT: /R/A/S-ONLY
Average Power-Supply Current I
(/R/A/S Cycling, /C/A/S = V
t
IH:
RC = tRC (MIN))
CC5 85 75 65 65 mA 3
REFRESH CURRENT: /C/A/S-BEFORE-/R/A/S
Average Power-Supply Current I
(/R/A/S, /C/A/S, Address Cycling:
MT4C1004J 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000021
t
RC = tRC (MIN))
2-26
CC6 85 75 65 65 mA 3, 5
MT5C1005 883C
AUSTIN SEMICONDUCTOR, INC.
AUSTIN SEMICONDUCTOR, INC.
MT4C1004J 883C
256K x 4 SRAM
4 MEG x 1 DRAM
CAPACITANCE
PARAMETER SYMBOL MIN MAX UNITS NOTES
Input Capacitance: A0-A10, D C
Input Capacitance: /R/A/S, /C/A/S, ?W/EC
Output Capacitance: Q C
I1 7pF2
I27pF2
O 8pF2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C ≤ TC ≤ 125; VCC = 5V ± 10%)
AC CHARACTERISTICS -7 -8 -10 -12
PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Random READ or WRITE cycle time
READ-WRITE cycle time
FAST-PAGE-MODE READ
or WRITE cycle time
FAST-PAGE-MODE READ-WRITE
cycle time
Access time from /R/A/S
Access time from /C/A/S
Access time from column address
Access time from /C/A/S precharge
/R/A/S pulse width
/R/A/S pulse width (FAST PAGE MODE)
/R/A/S hold time
/R/A/S precharge time
/C/A/S pulse width
/C/A/S hold time
/C/A/S precharge time
/C/A/S precharge time (FAST PAGE MODE)
/R/A/S to /C/A/S delay time
/C/A/S to /R/A/S precharge time
Row address setup time
Row address hold time
/R/A/S to column
address delay time
Column address setup time
Column address hold time
Column address hold time
(referenced to /R/A/S)
Column address to
/R/A/S lead time
Read command setup time
Read command hold time
(referenced to /C/A/S)
Read command hold time
(referenced to /R/A/S)
/C/A/S to output in Low-Z
Output buffer turn-off delay
?W/E command setup time
t
RC 130 150 180 220 ns
t
RWC 155 175 210 255 ns
t
PC 40 45 55 70 ns
t
PRWC 65 70 85 140 ns
t
RAC 70 80 90 120 ns 14
t
CAC 20 20 25 30 ns 15
t
AA 35 40 45 60 ns
t
CPA 35 40 45 60 ns
t
RAS 70 10,000 80 10,000 100 10,000 120 100,000 ns
t
RASP 70 100,000 80 100,000 100 100,000 120 100,000 ns
t
RSH 20 20 25 30 ns
t
RP 50 60 70 90 ns
t
CAS 20 10,000 20 10,000 25 10,000 30 10,000 ns
t
CSH 70 80 100 120 ns
t
CPN 10 10 12 15 ns 16
t
CP 10 10 12 15 ns
t
RCD 20 50 20 60 25 75 25 90 ns 17
t
CRP 5 5 5 10 ns
t
ASR 0 0 0 0 ns
t
RAH 10 10 15 15 ns
t
RAD 15 35 15 40 20 50 20 60 ns 18
t
ASC 0 0 0 0 ns
t
CAH 15 20 25 25 ns
t
AR 50 60 70 85 ns
t
RAL 35 40 50 60 ns
t
RCS 0 0 0 0 ns
t
RCH 0 0 0 0 ns 19
t
RRH 0 0 0 0 ns 19
t
CLZ 0 0 0 0 ns
t
OFF0200 20 0 20020ns20
t
WCS 0 0 0 0 ns 21
MT4C1004J 883C Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
REV. 11/97
DS000021
2-27
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