2.0 General Description...............................................................................................................................5
5.0 Signal Interface ....................................................................................................................................12
5.2 Signal Pin........................................................................................................................................................................ 12
5.3 Signal Description .......................................................................................................................................................... 14
5.4 Signal Electrical Characteristics..................................................................................................................................... 15
5.5 Signal for Lamp connector ............................................................................................................................................. 15
6.0 Pixel Format Image..............................................................................................................................16
7.0 Parameter guide line for CCFL Inverter...........................................................................................16
11.1 Reliability Test Conditions...........................................................................................................................................21
13.3 Screw Hole Depth and Center Position........................................................................................................................ 25
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 2/2
II Record of Revision
Version and Date Page Old description New Description Remark
V1. 2004/3/3 All First Release NA
V2. 2004/3/10 17 NA Add note 6 Update
V3. 2004/3/23 17
V4. 2004/5/13 16 CCFL DP-1 CCFL DP-1 Update
17 Tim ing Ch ar ac ter is ti cs Timing Ch ara ct er is tic s Update
18 Tim ing De fi nit io n Timing De fin iti on Update
19 Pow er Co ns ump ti on Power C on su mpt io n Update
24 LCM dr aw ing (R ea r V iew ) LCM dra wi ng (R ear Vi ew ) Update
V5. 2004/6/29 23 LCM drawing (Front View) LCM drawing (Front View) Update
V.6 2004/7/5 8 N/A Add viewing angle min value Add
Clock frequency and Horizontal Section Clock frequency and Horizontal Section
Update
www.jxlcd.com
www.jxlcd.com
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 3/3
1.0 Handling Precautions
1) Do not press or scratch the surface harder than a HB pencil lead because the polarizers are very fragile
and could be easily damaged.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water droplets or oil immediately. Long contact with the droplets may cause discoloration or
spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.
6) Protect the module from static electricity and insure proper grounding when handling. Static electricity
may cause damage to the CMOS Gate Array IC.
7) Do not disassemble the module.
8) Do not press the reflector sheet at the back of the module.
9) Avoid damaging the TFT module. Do not press the center of the CCFL Reflector when it was taken out
from the packing container. Instead, press at the edge of the CCFL Reflector softly.
10) Do not rotate or tilt the signal interface connector of the TFT module when you insert or remove other
connector into the signal interface connector.
11) Do not twist or bend the TFT module when installation of the TFT module into an enclosure (Notebook
PC Bezel, for example). It should be taken into consideration that no bending/twisting forces are applied
to the TFT module from outside when designing the enclosure. Otherwise the TFT module may be
damaged.
12) Cold cathode fluorescent lamp in LCD contains a small amount of mercury. Please follow local regulations for
disposal.
13) The LCD module contains a small amount of material that has no flammability grade, so it should be supplied
by power complied with requirements of limited power source (2.11, IEC60950 or UL1950).
14) The CCFL in the LCD module is supplied with Limited Current Circuit (2.4, IEC60950 or UL 60950). Do not
connect the CCFL in Hazardous Voltage Circuit.
www.jxlcd.com
www.jxlcd.com
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 4/4
2.0 General Description
This specification applies to the 17 inch Color TFT/LCD Module B170PW02
This module is designed for a display unit of notebook style personal computer.
The screen format is intended to support the WXGA +(1440(H) x 900(V)) screen and 262k colors (RGB 6-bits
data driver).
All input signals are LVDS interface compatible.
This module does not contain an inverter card for backlight.
The following items are characteristics summary on the table under 25 ℃ condition:
ITEMS Unit SPECIFICATIONS
Screen Diagonal [mm] 17.0”
Active Area [mm] 367.20(H) x 229.50(V)
Pixels H x V 1440 (x3) x 900
Pixel Pitch [mm] 0..255(per one triad) x 0.255
Pixel Arrangement R.G.B. Vertical Stripe
Display Mode Normally White
Typical White Luminance(CCFL=6.0mA) [cd/m2] 385 Typ.(5 points average)
Contrast Ratio 350 : 1 Min ,400:1 Typ
Response Time [msec] 16 Typ.
Nominal Input Voltage VDD [Volt] +3.3 Typ.
Typical Power Consumption
(VDD line + VCFL line)
Weight [Grams] 1100g max. (w/o Inverter)
Physical Size [mm] 382.2(W) x 246.8(H) x 10.0(upper) max.
Electrical Interface 2 channel LVDS (4pair/1 channel)
Surface treatment Glare, low reflection
Support Color Native 262K colors ( RGB 6-bit data driver )
Temperature Range
Operating
Storage (Shipping)
www.jxlcd.com
www.jxlcd.com
[Watt] 13 Watt (w/o Inverter, All black pattern)@LCM
circuit 3.3 Watt(typ.),B/L input 9.8 Watt (typ.)
/8.6(lower) max
o
[
C]
o
[
C]
0 to +50
-20 to +60
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
Red x0.5800.610 0.640
Red y0.3100.340 0.370
Green x0.2850.315 0.345
Green y0.5200.550 0.580
Blue x0.1150.145 0.175
Blue y0.0850.115 0.145
White x0.2900.320 0.350
White y
Note 1: Definition of 5 ,13 points position & white uniformity:
White uniformity is defined as the following with five/thirteen measurements (1~13).
ConditionsMin.Typ.Max.Note
355385 - 1,2,3
60
60
50
50
70
70
60
60
-
-
-
-
0.3000.330 0.360
2,7
1
5
2,7
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 8/8
www.jxlcd.com
www.jxlcd.com
10mm
10mm
10mm
6
9
11
7201080 360
7
1
5
3
12
2
4
10mm
8
10
13
10mm
225
450
675
Maximum Brightness of five (1,2,3,4,5) points
δ
=
W5
Minimum Brightness of five (1,2,3,4,5) points
Maximum Brightness of thirteen points
δ
=
W13
Minimum Brightness of thirteen points
Note 2: Measurement method
The LCD module should be stabilized at given temperature for 30 minutes to avoid abrupt temperature change
during measuring. In order to stabilize the luminance, the measurement should be executed after lighting Backlight
for 30 minutes in a stable, windless and dark room.
Photodetector
(BM-5A,BM-7 or equivalent)
Field=2°
www.jxlcd.com
LCD Panel
www.jxlcd.com
Center of the screen
Note 3: Definition of Average Luminance of White (Y
Measure the luminance of gray level 63 at 5 points,Y
L (x) is corresponding to the luminance of the point X at Figure in Note (1).
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 9/9
):
L
= [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
L
50 cm
TFT-LCD Module
g
Note 4: Definition of Cross Talk (CT)
CT = | YB – YA | / YA × 100 (%)
Where
Y
A = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
Note 5: Definition of response time:
The output signals of BM-7 or equivalent are measured when the input signals are changed from “Black” to
“White” (falling time) and from “White” to “Black” (rising time), respectively. The response time interval between the
10% and 90% of amplitudes. Refer to figure as below.
www.jxlcd.com
www.jxlcd.com
"Black"
100%
S
i
90%
g
n
a
l
(
R
e
l
a
t
i
v
e
v
a
l
u
10%
e
)
0%
Tr
Tf
"White""White"
Note 6. Definition of contrast ratio:
Contrast ratio is calculated with the following formula.
Contrast ratio (CR)=
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 10/10
Brightness on the “White” state
Bri
htness on the “Black” state
Note 7. Definition of viewing angle
Viewing angle is the measurement of contrast ratio ≧10, at the screen center, over a 180° horizontal and
180° vertical range (off-normal viewing angles). The 180° viewing angle range is broken down as follows; 90°
(θ) horizontal left and right and 90° (Φ) vertical, high (up) and low (down). The measurement direction is
typically perpendicular to the display surface with the screen rotated about its center to develop the desired
measurement viewing angle.
www.jxlcd.com
www.jxlcd.com
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 11/11
y
5.0 Signal Interface
55..11 CCoonnnneeccttoorrss
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
Connector Name / Designation
Manufacturer
Type / Part Number
Mating Housing/Part Number
Mating Contact/Part Number
Connector Name / Designation
Manufacturer
Type / Part Number
Mating Type / Part Number
55..22 SSiiggnnaall PPiinn
(1).Input signal interface
Pin no S
1 GND Ground
www.jxlcd.com
For Signal Connector
JAE or compatible
FI-XB30S-HF10 or compatible
FI-X30H
FI-XC3-1-15000
For Lamp Connector
JST
BHSR-02VS-1
SM02B-BHSS-1-TB
mbol FunctionEtc.
www.jxlcd.com
2 VDD Power supply ,3.3 V (typical)
3 VDD Power supply ,3.3 V (typical)
4 V
5 NC Reserved for supplier test
6 CLK
7 Data
8 Odd_RxIN0- -LVDS differential data input
9 Odd_RxIN0+ +LVDS differential data input
10 GND Ground
11 Odd_RxIN1- -LVDS differential data input
12 Odd_RxIN1+ +LVDS differential data input
13 GND Ground
14 Odd_RxIN2- -LVDS differential data input
15 Odd_RxIN2+ +LVDS differential data input
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
19 GND Ground
20 Even_RxIN0- -LVDS differential data input
21 Even_RxIN0+ +LVDS differential data input
22 GND Ground
23 Even_RxIN1- -LVDS differential data input
24 Even_RxIN1+ +LVDS differential data input
25 GND Ground
26 Even_RxIN2- -LVDS differential data input
27 Even_RxIN2+ +LVDS differential data input
28 GND Ground
29 Even_RxCLKIN- -LVDS differential clock input
30 Even_RxCLKIN+ +LVDS differential clock input
(2) LVDS channel interface data mapping diagram
ODD pair( 1st pixel input)
CK
DIN1
DIN2
DIN3
Even pair(2nd pixel input)
CK
DIN1
DIN2
www.jxlcd.com
www.jxlcd.com
G0R5R4R3R2 R1R0
B1B0G5G4G3 G2G1
DEVSHSB5B4 B3B2
G0R5R4R3R2 R1R0
B1B0G5G4G3 G2G1
DIN3
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 13/13
DEVSHSB5B4 B3B2
55..33 SSiiggnnaall DDeessccrriippttiioonn
The module uses a LVDS receiver embedded in AUO’s ASIC. LVDS is a differential signal technology for LCD
interface and high-speed data transfer device.
Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
Red-pixel Data
www.jxlcd.com
www.jxlcd.com
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
Green-pixel Data
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data
Data Clock
Display Timing
Vertical Sync
Horizontal Sync
LVDS differential data input (Red0-Red5, Green0)
LVDS differential data input (Green1-Green5, Blue0-Blue1)
LVDS differential data input (Blue2-Blue5, Hsync, Vsync, DSPTMG)
LVDS differential clock input
Red-pixel Data
Each red pixel's brightness data consists of these 6 bits
pixel data.
Green-pixel Data
Each green pixel's brightness data consists of these 6 bits
pixel data.
Blue-pixel Data
Each blue pixel's brightness data consists of these 6 bits
pixel data.
The typical frequency is 48.2 MHz. The signal is used to
strobe the pixel data and DSPTMG signals. All pixel data
shall be valid at the falling edge when the DSPTMG signal
is high.
This signal is strobed at the falling edge of
-DTCLK. When the signal is high, the pixel data shall be
valid to be displayed.
The signal is synchronized to -DTCLK .
The signal is synchronized to -DTCLK .
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 14/14
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
Input signals shall be in low status when VDD is off.
It is recommended to refer the specifications of SN75LVDS86DGG (Texas Instruments) in detail.
Signal electrical characteristics are as follows;
Parameter Condition Min Max Unit
Vth
Vtl
Differential Input High
Voltage(Vcm=+1.2V)
Differential Input Low
Voltage(Vcm=+1.2V)
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 15/15
6.0 Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format.
1
2
14391440
1st Line
900th Line
R GB R GB
R GB R GB
R G B R GB
R G B R GB
7.0 Parameter guide line for CCFL Inverter
www.jxlcd.com
www.jxlcd.com
Parameter
White Luminance
5 points average
CCFL current(ICFL) 6.0 7.0 [mA] rms
CCFL Frequency(FCFL) 45 50 80 [KHz]
CCFL Ignition Voltage(Vs)
CCFL Voltage (Reference)
(VCFL)
CCFL Power consumption
(PCFL)
Note 1: DP-1 are AUO recommended Design Points.
*1 All of characteristics listed are measured under the condition using the AUO Test inverter.
*2 In case of using an inverter other than listed, it is recommended to check the inverter carefully. Sometimes,
interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit ver carefully. Impedance of CCFL, for instance,
becomes more than 1 [M ohm] when CCFL is damaged.
Min DP-1MaxUnitsCondition
350
775 815 940 [Volt] rms
385
9.8
1500 [Volt] rms
[cd/m
[Watt]
2
]
(Ta=25
(Ta=25
Note 2
(Ta=25
Note 3
(Ta= 0
Note 4
(Ta=25
Note 5
(Ta=25
Note 5, 6
℃)
℃)
℃)
℃)
℃)
℃)
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 16/16
*4 Generally, CCFL has some amount of delay time after applying start-up voltage. It is recommended to keep
on applying start-up voltage for 1 [Sec] until discharge.
*5 The CCFL inverter operating frequency must be carefully chosen so that no interfering noise stripes on the
screen were induced.
*6 Reducing CCFL current increases CCFL discharge voltage and generally increases CCFL discharge
frequency. So all the parameters of an inverter should be carefully designed so as not to produce too much
leakage current from high-voltage output of the inverter.
Note 2: It should be employed the inverter, which has “Duty Dimming”, if ICCFL is less than 4mA.
Note 3: The CCFL inverter operating frequency should be carefully determined to avoid interference between
inverter and TFT LCD.
Note 4: The inverter open voltage should be designed larger than the lamp starting voltage at T=0
backlight may be blinking for a moment after turning on or not be able to turn on. The open voltage should
be measured after ballast capacitor. If an inverter has shutdown function it should keep its open voltage. for
longer than 1 second even if lamp connector is open.
Note 5: Calculator value for reference (ICFL×VCFL=PCFL)
Note 6: This model has 2 CCFL lamps.
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 17/17
88..22 TTiimmiinngg DDeeffiinniittiioonn
www.jxlcd.com
www.jxlcd.com
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 18/18
9.0 Power Consumption
Input power specifications are as follows;
Symbol Parameter Min Typ Max UnitsCondition
Module
VDD Logic/LCD Drive
PDD VDD Power 2.15 [Watt] All White pattern
PDD Max VDD Power max 3.3 [Watt] All BLACK pattern
IDD IDD Current 630 mA All White pattern
IDD Max IDD Current max 1000 mA All BLACK pattern
VDDrp Allowable
VDDns Allowable
Lamp
ICFL CCFL current 3.0 6.0 7.0 [mA]
VCFL CCFL Voltage
PCFL CCFL Power
Total Power
Consumption
3.0 3.3 3.6 [Volt] Load Capacitance 20uF
Voltage
100 [mV]
Logic/LCD Drive
Ripple Voltage
100 [mV]
Logic/LCD Drive
Ripple Noise
(Reference)
www.jxlcd.com
www.jxlcd.com
consumption
13.1 Watt typ (w/o Inverter, All black pattern)@LCM circuit 3.3 Watt(typ.),B/L input 9.8
Watt(typ.)
785
9.8
p-p
p-p
rms
[Volt]
rms
[Watt]
(Ta=25
(Ta=25
(Ta=25
℃)
℃)
℃)
Note : VDD=3.3V
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 19/19
10. Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals
from any system shall be Hi-Z state or low level when VDD is off.
Sequence of Power-on/off and signal-on/off
Power Supply VDD
LVDS Interface
Backlight On
Apply the lamp voltage within the LCD operating range. When the backlight turns on before the
LCD operation or the LCD turns off before the backlight turns off, the display may momentarily
become abnormal.
0.1VDD
www.jxlcd.com
www.jxlcd.com
T1
0.9VDD
T2
T5
0.9VDD
T6
T3
0.1VDD
≦T1≦10ms
1ms
≦T2≦50ms
6ms
≦T3<50ms
0ms
400ms
200ms
200ms
≦T4
≦T5
≦T6
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
Items Required Condition
Temperature Humidity Bias
High Temperature Operation
Low Temperature Operation
Continuous Life
On/Off Test ON/30 sec. OFF/30sec., 30,000 cycles
Hot Storage
Cold Storage
Thermal Shock Test
Hot Start Test
Cold Start Test
Shock Test (Non-Operating)
Vibration Test (Non-Operating)
ESD
Altitude Test
Maximum Side Mount Torque 2.5kgf.cm .
CCFL Life : 10,000 hours minimum
MTBF(Excluding the CCFL) : 30,000 hours with a confidence level 90%
Screw hole minimum depth, from side surface =2.5 mm (See drawing)
Screw hole center location, from front surface = 4.2
Screw maximum length = 2.3 mm (See drawing)
Screw Torque: Maximum2.5 kgzf-cm
± 0.3mm (See drawing)
4.2 + 0.3
10.0 (Max)
www.jxlcd.com
www.jxlcd.com
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 25/25
14. Shipping Label Format
23mm
www.jxlcd.com
www.jxlcd.com
Model name
83mm
Hardware
Week code
Firmware
Manufacturing area
Control
code
Model name
83mm
23mm
Hardware
(C) Copyright AU Optronics
Sep., 2003 All Rights Reserved. B170PW02 V0 Spec Ver.6
No Reproduction and Redistribution Allowed. 26/26
Week code
Firmware
Manufacturing area
Control
code
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.