0.6 2001/8/13 8 Signal connector: JAE FI-Signal connector: JAE FI- XB30SR- Connector type
(C) Copyright AU Optronics, Inc.
July, 2001 All Rights Reserved. B150PN01 Ver.06
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SEB20P- HF13 HF11 change from 20
pin to 30 pin.
0.6 2001/8/13 18 Update mechanical drawing
1.0 Handing Precautions
1) Since front polar izer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration or
spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard
surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure human
earth when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) In case if a Module has to be put back into the packing container slot after once it was
taken out from the container, do not press the center of the CCFL Reflector edge. Instead,
press at the far ends of the CFL Reflector edge softly. Otherwise the TFT Module may be
damaged.
10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt
the Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure (Notebook PC Bezel, for example),
do not twist nor bend the TFT Module even momentary. At designing the enclosure, it
should be taken into consideration that no bending/twisting forces are applied to the TFT
Module from outside. Otherwise the TFT Module may be damaged.
12) Cold cathode fluorescent lamp in LCD contains a small amount of mercury. Please follow local
ordinances or regulations for disposal.
13) Small amount of materials having no flammability grade is used in the LCD module. The LCD
module should be supplied by power complied with requirements of Limited Power Source(2.11,
IEC60950 or UL1950), or be applied exemption.
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14) The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit(2.4,
IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.
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2.0 General Description
This specification applies to the 15.0 inch Color TFT/LCD Module B150PN01.
This module is designed for a display unit of notebook style personal computer.
The screen format is intended to support the SXGA+ (1400(H) x 1050(V)) screen and 262k colors
(RGB 6-bits data driver).
All input signals are LVDS interface compatible.
This module does not contain an inverter card for backlight.
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2.1 Display Characteristics
The following items are characteristics summary on the table under 25 ℃ condition:
ITEMS Unit SPECIFICATIONS
Screen Diagonal [mm] 381
Active Area [mm] 304.5 X 228.375
Pixels H x V 1400(x3) x 1050
Pixel Pitch [mm] 0.2175X0.2175
Pixel Arrangement R.G.B. Vertical Stripe
Display Mode Normally White
Typical White Luminance (ICFL=5.5mA) [cd/m2] 150 (5 point average)
Contrast Ratio 250
Optical Rise Time/Fall Time [msec] 15/35
Nominal Input Voltage VDD [Volt] +3.3 Typ.
Typical Power Consumption
(VDD line + VCFL line)
Weight [Grams] 550g typ.
Physical Siz e [mm] 315.8 x 240.6 x 5.9 typ.
Electrical Interface 2 channel LVDS
Support Color Native 262K colors ( RGB 6-bit data
Temperature Range
Operating
Storage (Shipping)
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[Watt]
[oC]
[oC]
5.5W
0 to +50
-20 to +60
(C) Copyright AU Optronics, Inc.
July, 2001 All Rights Reserved. B150PN01 Ver.06
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Controller
Lamp Connector(2pin)
2.2 Functional Block Diagram
The following diagram shows the functional block of the 15.0 inches Color TFT/LCD Module:
X-Driver
( 8 pairs LVDS)
Ro/eIN0+/Ro/eIN1+/Ro/eIN2+/Ro/eCLKIN+/-
VDD
GND
Mating JAE FI-X30M or FI -X30H
JAE FI-XB30SR-HF11
FI -C3-A1
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LCD DRIVE
CARD
LCD
DC-DC
Converter
Ref circuit
TFT ARRAY/CELL
1400(R/G/B) x 3
Y -Driver
1050
Backlight Unit
JST BHSR-02VS-1
Mating Type SM02B-BHSS -1-TB
(C) Copyright AU Optronics, Inc.
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3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as following:
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 +4.0 [Volt]
Input Voltage of Signal Vin -0.3 VDD+0.3 [Volt]
CCFL Current ICFL - 7 [mA]
rms
CCFL Ignition Voltage Vs - 1150 Vrms
Operating Temperature TOP 0 +50 [oC] Note 1
Operating Humidity HOP 8 95 [%RH] Note 1
Storage Temperature TST -20 +6 0 [oC] Note 1
Storage Humidity HST 5 95 [%RH] Note 1
Vibration 1.5 10-500
(random)
Shock 220 , 2 G ms Half sine wave
Note 1 : Maximum Wet -Bulb should be 39℃ and No condensation.
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G Hz 2hr/axis, X,Y,Z
(C) Copyright AU Optronics, Inc.
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4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25℃ condition :
Item Conditions Typ. Note
Viewing Angle
K: Contrast Ratio
Contrast ratio
Response Time [msec] Rising
(Room Temp.) [msec] Falling
Color Red x
Chromaticity Red
Coordinates (CIE) Green x
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[degree]
[degree]
[degree]
[degree]
Horizontal (Right)
K = 10 (Left)
Vertical (Upper)
K = 10 (Lower)
y TBD TBD
Green
Blue x
Blue
White x
White
y TBD TBD
y TBD TBD
y 0.329 TBD
40
40
10
30
250
15 45(Max.)
35 45(Max.)
TBD TBD
TBD TBD
TBD TBD
0.313 TBD
— —
—
—
—
White Luminance
(CCFL 5.5 mA)
[cd/m2]
150 ( 5 points average)
(C) Copyright AU Optronics, Inc.
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5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following
components.
Connector Name / Designation For Signal Connector
Manufacturer JAE
Type / Part Number FI-XB30SR-HF11
Mating Housing/Part Number FI-X30M or FI-X30H
Mating Contact/Part Number FI-C3-A1
Connector Name / Designation For Lamp Connector
Manufacturer JST
Type / Part Number BHSR-02VS-1
Mating Type / Part Number SM02B- BHSS-1-TB
5.2 Signal Pin
Pin# Signal Name Pin# Signal Name
(C) Copyright AU Optronics, Inc.
July, 2001 All Rights Reserved. B150PN01 Ver.06
The module using a LVDS receiver. LVDS is a differential signal technology for LCD interface
and high speed data transfer device. Transmitter shall be SN75LVDS84 (negative edge
sampling) or compatible.
Signal Name
Description
RoIN0-, RoIN0+
RoIN1-, RoIN1+
RoIN2-, RoIN2+
RoCLKIN-, RoCLKIN0+ LVDS Odd differential clock inpu t
ReIN0-, ReIN0+
ReIN1-, ReIN1+
ReIN2-, ReIN2+
ReCLKIN-, ReCLKIN0+ LVDS Even differen tial clock input
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VDD
GND
LVDS differential Odd data input(Red0- Red5, Green0)
LVDS differential Odd data input(Green1-Green5, Blue0-Blue1)
LVDS differential Odd data input(Blue2 -Blue5, Hsync, Vsync,
DSPTMG)
LVDS differential Even data input(Red0 -Red5, Green0)
LVDS differential Even data input(Green1-Green5, Blue0-Blue1)
LVDS differential Even data input(Only Blue2 -Blue5)
+3.3V Power Supply
Ground
Note: Input signals shall be low or Hi-Z state when VDD is off.
Internal circuit of LVDS inputs are as following.
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18. ReIN2+19. ReCLKIN-
20. ReCLKIN+
Signal Input
5. RoIN0-
6. RoIN0+
7. RoIN1-
8. RoIN1+
9. RoIN2-
10. RoIN2+
11. RoCLKIN-
12. RoCLKIN+
SN75LVDS86 OR Compatible
13. ReIN0-
14. ReIN0+
15. ReIN1-
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16. ReIN1+
17. ReIN2-
The module uses a 100ohm resistor between positive and negative data lines of each
receiver input
(C) Copyright AU Optronics, Inc.
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Signal Name Description
+RED5
+RED4
+RED3
+RED2
+RED1
+RED0
-DTCLK Data Clock The typical frequency is 54.0 MHZ.. The signal is
DSPTMG Display Timing This signal is strobed at the falling edge of
VSYNC Vertical Sync The signal is synchronized to -DTCLK .
HSYNC Horizontal Sync The signal is synchronized to -DTCLK .
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
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Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
Red-pixel Data
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
Green -pixel Data
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data
Red-pixel Data
Each red pixel's brightness data consist s of these
6 bits pixel data.
Green -pixel Data
Each green pixel's brightness data consists of
these 6 bits pixel data.
Blue-pixel Data
Each blue pixel's brightness data consists of
these 6 bits pixel data.
used to strobe the pixel data and DSPTMG
signals. All pixel data shall be valid at the falling
edge when the DSPTMG signal is high.
-DTCLK. When the signal is high, the pixel data
shall be valid to be displayed.
5.4 Signal Electrical Characteristics
Input signals shall be low or Hi-Z state when VDD is off.
It is recommended to refer the specifications of SN75LVDS86DGG(Texas Instruments) in detail.
Signal electrical characteristics are as follows;
(C) Copyright AU Optronics, Inc.
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Parameter Condition Min Max Unit
Vth
Differential Input High
Voltage(Vcm=+1.2V)
100
[mV]
Vtl
LVDS Macro AC characteristics are as follows:
Clock Frequency (T) TBD TBD
Data Setup Time (Tsu) TBD
Data Hold Time (Thd) TBD
Input Clock
Input Data
Differential Input Low
Voltage(Vcm=+1.2V)
Min. Max.
T
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- 100
[mV]
ThdTsu
5.5 Signal for Lamp connector
2
6.0 Pixel Format Image
Following figure shows the relation ship of the input signals and LCD pixel format.
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1050th
1st Line
1(Odd) 2(Even)
R G B R G B
R G B R G B
1399 1400
R G B R G B
R G B R G B
7.0 Parameter guide line for CFL Inverter
Parameter Min DP- 1 Max Units Condition
White Luminance
5 points average
CCFL current(ICFL) 3.0 5.5 7.0 [mA] rms
CCFL Frequency(FCFL) 50 60 70 [KHz]
CCFL Ignition Voltage(Vs)
CCFL Voltage (Reference)
(VCFL)
CCFL Power consumption
(PCFL)
Note 1: DP-1 are ADT recommended Design Points.
*1 All of characteristics listed are measured under the condition using the ADT Test inverter.
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-
700
3.9
150
1,150
[cd/m2 ]
[Volt]
rms
[Volt]
rms
[Watt]
(Ta=25℃)
(Ta=25℃)
Note 2
(Ta=25℃)
Note 3
(Ta= 0℃)
Note 4
(Ta=25℃)
Note 5
(Ta=25℃)
Note 5
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*2 In case of using an inverter other than listed, it is recommended to check the inverter carefully.
Sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker
at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit ver carefully. Impedance of CFL,
for instance, becomes more than 1 [M ohm] when CFL is damaged.
*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is
recommended to keep on applying kick -off voltage for 1 [Sec] until discharge.
*5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise
stripes on the screen.
*6 Reducing CFL current increases CFL discharge voltage and generally increases CFL
discharge frequency. So all the parameters of an inverter should be carefully designed so as not
to produce too much leakage current from high-voltage output of the inverter.
Note 2: It should be emplyed the inverter which has “Duty Dimming”, if ICFL is less than 4mA.
Note 3: CFL discharge frequency shouldbe carefully determined to avoid interference between
inverter and TFT LCD.
Note 4: CFL inverter should be able to give out a power that has a generating capacity of over
1,400 voltage. Lamp units need 1,400 voltage minimum for ignition.
Note 5: Calculator value for reference (ICFL×VCFL=PCFL)
8.0 Interface Timings
Basically, interface timings should match the VESA 1024x768 /60Hz (VG901101) manufacturing
guide line timing.
8.1 Timing Characteristics
Symbol Description Min Typ Max Unit
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fdck DTCLK Frequency
tck DTCLK cycle time
tx X total time TBD 844 TBD [tck]
tacx X active time TBD 700
tbkx X blank time 144
Hsync H frequency
Hsw H-Sync width TBD 56
Hbp H back porch TBD 64
Hfp H front porch TBD 24
t y Y total time TBD 1066 TBD [tx]
tacy Y active time
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54.00
18.5
63.98
1050
[MHz]
[nsec]
[tck]
[tck]
[KHz]
[tck]
[tck]
[tck]
[tx]
Vsync Frame rate (55) 60 61 [Hz]
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DSPTM
Voltage
Vw V-sync Width 1 3
[tx]
Vfp V-sync front porch 1 1
Vbp V-sync back porch 7 12 63 [tx]
Note: Hsw(H -sync width) + Hbp(H-sync back porch) should be less than 515 tck.
8.2 Timing Definition
1688 dot
H-Sync
112 dot
V-Sync
128 dot48 dot
1400 dot
[tx]
DSPTMG
1H
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3H
16H
12H
1050H
9.0 Power Consumption
Input power specifications are as follows;
Symble Parameter Min Typ Max Units Condition
VDD Logic/LCD Drive
PDD VDD Power
PDD Max VDD Power max
IDD IDD Current
IDD Max IDD Current max
VDDrp Allowable
(C) Copyright AU Optronics, Inc.
July, 2001 All Rights Reserved. B150PN01 Ver.06
3.0 3.3 3.6 [Volt] Load Capacitance 20uF
TBD [Watt] All Black Pattern
TBD
TBD [Watt] Max Pattern Note
mA
TBD mA
100 [mV]
All Black Pattern
Max Pattern Note
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0 V
VDD
180ms min.
0 min.
Lamp On
Logic/LCD Drive
Ripple Voltage
VDDns Allowable
Logic/LCD Drive
Ripple Noise
Note : VDD=3.3V
100 [mV]
p-p
p-p
10. Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the
chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
5. Package instruction
150ms min.
10%
90%
10ms max.
0 min.
90%
10%10%
0 min.
Signals
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0 V
0 V
10%10%
10%10%
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11. Mechanical Characteristics
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