2.0 General Description...............................................................................................................................5
5.0 Signal Interface ....................................................................................................................................10
5.2 Signal Pin........................................................................................................................................................................ 10
5.3 Signal Description .......................................................................................................................................................... 10
5.4 Signal Electrical Characteristics..................................................................................................................................... 12
5.5 Signal for Lamp connector ............................................................................................................................................. 12
6.0 Pixel Format Image..............................................................................................................................13
7.0 Parameter guide line for CCFL Inverter...........................................................................................13
11.1 Reliability Test Conditions...........................................................................................................................................18
13.3 Screw Hole Depth and Center Position........................................................................................................................ 23
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II Record of Revision
Version and Date Page Old description New Description Remark
V.0 2003/12/01 All First Release NA
V.1 2004/3/29 5 Surface tre atment: Haze 25,
8 Cross talk: no this item Add this item 21 LCM outline drawing (front
22 LCM outline drawing (rear
V.3 2004/7/8 9 Crosstalk test pattern:
V.4 2004/9/3 17
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Color Chromaticity: R,G,B is
TBD
view): CCFL cable hasn’t
added a tape
view): CCFL cable hasn’t
added a tape
32-gray level
1ms≦T1≦10ms 0ms<T1≦10ms
Haze 25, hard coating 3H,AG
Update R,G,B color value
LCM outline drawing (front
view): CCFL cable add a tape
LCM outline drawing (rear
view): CCFL cable add a tape
Crosstalk test pattern:
63-gray level
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1.0 Handling Precautions
1) Do not press or scratch the surface harder than a HB pencil lead because the polarizers are very fragile
and could be easily damaged.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water droplets or oil immediately. Long contact with the droplets may cause discoloration or
spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.
6) Protect the module from static electricity and insure proper grounding when handling. Static electricity
may cause damage to the CMOS Gate Array IC.
7) Do not disassemble the module.
8) Do not press the reflector sheet at the back of the module.
9) Avoid damaging the TFT module. Do not press the center of the CCFL Reflector when it was taken out
from the packing container. Instead, press at the edge of the CCFL Reflector softly.
10) Do not rotate or tilt the signal interface connector of the TFT module when you insert or remove other
connector into the signal interface connector.
11) Do not twist or bend the TFT module when installation of the TFT module into an enclosure (Notebook
PC Bezel, for example). It should be taken into consideration that no bending/twisting forces are applied
to the TFT module from outside when designing the enclosure. Otherwise the TFT module may be
damaged.
12) Cold cathode fluorescent lamp in LCD contains a small amount of mercury. Please follow local regulations for
disposal.
13) The LCD module contains a small amount of material that has no flammability grade, so it should be supplied
by power complied with requirements of limited power source (2.11, IEC60950 or UL1950).
14) The CCFL in the LCD module is supplied with Limited Current Circuit (2.4, IEC60950 or UL1950). Do not
connect the CCFL in Hazardous Voltage Circuit.
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2.0 General Description
This specification applies to the 14.0 inch Color TFT/LCD Module B140EW01
This module is designed for a display unit of notebook style personal computer.
The screen format is intended to support the WXGA (1280(H) x 768(V)) screen and 262k colors (RGB 6-bits
data driver).
All input signals are LVDS interface compatible.
This module does not contain an inverter card for backlight.
The following items are characteristics summary on the table under 25 ℃ condition:
ITEMS Unit SPECIFICATIONS
Screen Diagonal [mm] 355.6 (14.0")
Active Area [mm] 305.28(H) x 183.17(V)
Pixels H x V 1280(x3) x 768
Pixel Pitch [mm] 0.2385
Pixel Arrangement R.G.B. Vertical Stripe
Display Mode Normally White
Typical White Luminance (CCFL=6.0mA) [cd/m2] 200 Typ.(5 points average)
Contrast Ratio 250 : 1 Min ,300:1 Typ
Response Time [msec] 25 Typ.
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Nominal Input Voltage VDD [Volt] +3.3 Typ.
Typical Power Consumption
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3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as following:
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 +4.0 [Volt]
Input Voltage of Signal Vin -0.3 VDD+0.3 [Volt]
CCFL Current ICFL 2.5 7 [mA] rms
CCFL Ignition Voltage Vs
Operating Temperature TOP 0 +50 [oC]
Operating Humidity HOP 5 95 [%RH]
Storage Temperature TST -20 +60 [oC]
Storage Humidity HST 5 95 [%RH]
Vibration 1.5Sin 10-500 [G Hz]
Shock 240, 2 [G ms] Half sine wave
Note 1: Duration = 50msec
Note 2: Maximum Wet-Bulb should be 39℃ and No condensation.
1200 Vrms
Note 1
Note 2
Note 2
Note 2
Note 2
Wet bulb temperature chart
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Twb=39°C
Operating Range
Storage Range
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4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25℃ condition:
Item Unit Conditions Min. Typ. Max. Note
Horizontal (Right) 40 45 -
Viewing Angle
(CR = 10)
CR: Contrast Ratio
Uniformity
Contrast ratio (Center)250 300 -
Response Time[msec]
Color Chromaticity
Coordinates (CIE)
(Normal view angle)
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[degrees]
Vertical (Upper)15 20 -
5 Points - 1.2 (1)
13 Points - 1.5 (2)
Rising- 15 20
Falling
Red x0.560 0.590 0.620
Red y
Green x
Green y
Blue x
(Left) 40 45 -
(Lower) 30 35 -
- 10 15
0.300 0.330 0.360
0.290 0.320 0.350
0.510 0.540 0.570
0.120 0.150 0.180
Blue y
White x0.283 0.313 0.343
White Luminance
Cross talk
Note (1): 5 points position (Display area: 305.28 mm x 183.17 mm)
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[cd/m2]
%
White y
5 points average -- 200 - (1)
-- --- 1.4 (3)
0.299 0.329 0.359
0.100 0.130 0.160
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W
W/4W/4W/4W/4
H/4
1
H/4
H
H/4
4
H/4
3
2
5
Note (2): 13 points position
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W/4
10
10
10
1
6
11
H/4
H/4
H
H/4
H/4
Note (3): Definition of Cross Talk (DCT)
D
= | YB – YA | / YA ×100 (%)
CT
Y
Gray Level 63
,YB = (511,127) or (170,383) or (853,383) or (511,639)
A
Where :
Y
= Luminance of measured location without darkest gray pattern (cd/m2)
A
= Luminance of measured location with darkest gray pattern (cd/m2)
Y
B
(0, 0)
VIEW AREA
W/4
4
9
YA
(1023, 767)
W
W/4
2
7
12
Gray Level 0
Gray Level 63
5
10
(0, 0)
W/4
10
3
8
13
VIEW AREA
YB
(1023, 767)
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5.0 Signal Interface
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55..11 CCoonnnneeccttoorrss
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
Connector Name / Designation
Manufacturer
Type / Part Number
Mating Housing/Part Number
Mating Contact/Part Number
Connector Name / Designation
Manufacturer
Type / Part Number
Mating Type / Part Number
55..22 SSiiggnnaall PPiinn
Pin# Signal Name Pin# Signal Name
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For Signal Connector
JAE
FI-XB30S-HF10
FI-X30H
FI-XC3-1-15000
For Lamp Connector
JST
BHSR-02VS-1
SM02B-BHSS-1-TB
(C) Copyright AU Optronics
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10/23
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The module uses a LVDS receiver embedded in AUO’s ASIC. LVDS is a differential signal technology for LCD
interface and high-speed data transfer device.
Signal NameDescription
V
+3.3V EDID Power
EDID
CLK
DATA
RxIN0-, RxIN0+LVDS differential data input(Red0-Red5, Green0)
RxIN1-, RxIN1+LVDS differential data input(Green1-Green5, Blue0-Blue1)
RxIN2-, RxIN2+LVDS differential data input(Blue2-Blue5, Hsync, Vsync, DSPTMG)
RxCLKIN-, RxCLKIN0+LVDS differential clock input
VDD+3.3V Power Supply
GNDGround
Note: Input signals shall be in low status when VDD is off.
Internal circuit of LVDS inputs are as following.
Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
(Red-pixel Data)
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Green Data 5 (MSB)
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Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
(Green-pixel Data)
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
(Blue-pixel Data)
Data Clock
Display Timing
Vertical Sync
Horizontal Sync
Red-pixel Data
Each red pixel's brightness data consists of these 6 bits
pixel data.
Green-pixel Data
Each green pixel's brightness data consists of these 6 bits
pixel data.
Blue-pixel Data
Each blue pixel's brightness data consists of these 6 bits
pixel data.
The typical frequency is 71.1 MHz. The signal is used to
strobe the pixel data and DSPTMG signals. All pixel data
shall be valid at the falling edge when the DSPTMG signal
is high.
This signal is stored at the falling edge of -DTCLK. When
the signal is high, the pixel data shall be valid to be
displayed.
The signal is synchronized to -DTCLK .
The signal is synchronized to -DTCLK .
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Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
Input signals shall be in low status when VDD is off.
It is recommended to refer the specifications of SN75LVDS86DGG (Texas Instruments) in detail.
Signal electrical characteristics are as follows;
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6.0 Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format.
0
1
1278 1279
1st Line
768th Line
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R GB R GB
R GB R GB
7.0 Parameter guide line for CCFL Inverter
Parameter Min DP-1 Max Units Condition
R GB R G B
R GB R G B
2
[cd/m
[Volt] rms
[Watt]
White Luminance
5 points average
CCFL current (ICFL) 2.5 6.0 7.0 [mA] rms
CCFL Frequency (FCFL) 50 60 65 [KHz]
CCFL Ignition Voltage (Vs)
CCFL Voltage (Reference)
(VCFL)
CCFL Power consumption
(PCFL)
Note 1: DP-1 are AUO recommended Design Points.
*1 All of characteristics listed are measured under the condition using the AUO Test inverter.
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170
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200
1000 1200 [Volt] rms
650
4.2
]
(Ta=25℃)
(Ta=25℃) (Note 2)
(Ta=25℃) (Note 3)
(Ta= 25℃) (Note 4)
(Ta=25℃) (Note 5)
(Ta=25℃) (Note 5)
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*2 In case of using an inverter other than listed, it is recommended to check the inverter carefully. Sometimes,
interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit ver carefully. Impedance of CCFL, for instance,
becomes more than 1 [M ohm] when CCFL is damaged.
*4 Generally, CCFL has some amount of delay time after applying start-up voltage. It is recommended to keep
on applying start-up voltage for 1 [Sec] until discharge.
*5 The CCFL inverter operating frequency must be carefully chosen so that no interfering noise stripes on the
screen were induced.
*6 Reducing CCFL current increases CCFL discharge voltage and generally increases CCFL discharge
frequency. So all the parameters of an inverter should be carefully designed so as not to produce too much
leakage current from high-voltage output of the inverter.
Note 2: It should be employed the inverter, which has “Duty Dimming”, if ICCFL is less than 4mA.
Note 3: The CCFL inverter operating frequency should be carefully determined to avoid interference between
inverter and TFT LCD.
Note 4: The inverter open voltage should be designed larger than the lamp starting voltage at T=0
backlight may be blinking for a moment after turning on or not be able to turn on. The open voltage should
be measured after ballast capacitor. If an inverter has shutdown function it should keep its open voltage. for
longer than 1 second even if lamp connector is open.
Note 5: Calculator value for reference (ICFL×VCFL=PCFL)
o
C, otherwise
8.0 Interface Timings
Basically, interface timings should match the VESA 1024x768 /60Hz (VG901101) manufacturing guide line timing.
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10. Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in the chart. Signals
from any system shall be Hi-Z state or low level when VDD is off.
Sequence of Power-on/off and signal-on/off
Power Supply VDD
LVDS Interface
Backlight On
Apply the lamp voltage within the LCD operating range. When the backlight turns on before the
LCD operation or the LCD turns off before the backlight turns off, the display may momentarily
become abnormal.
Temperature Humidity Bias
High Temperature Operation
Low Temperature Operation
Continuous Life
On/Off Test ON/30 sec. OFF/30sec., 30,000 cycles
Hot Storage
Cold Storage
Thermal Shock Test
Hot Start Test
Cold Start Test
Shock Test (Non-Operating)
-20℃/30 min ,60℃/30 min 100cycles
50℃/1 Hr min. Power on/off per 5 minutes, 5 times
0℃/1 Hr min. Power on/off per 5 minutes, 5 times
240G, 2ms, Half-sine wave
Sinusoidal vibration, 1.5G zero-to-peak, 10 to 500 Hz,
0.5 octave/minute in each of three mutually
perpendicular axes.
Screw hole maximum depth, from side surface =2.5 mm (See drawing)
Screw hole center location, from front surface = 3.1 ± 0.1mm (See drawing)
Suggestions: Customers’ Screw maximum length = 2.3 mm (See drawing)
Screw Torque: Maximum2.5 kgf-cm
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