AUO T650QVJ02.0 Specification

T650QVJ02.0 Product Specification

Rev 1.0

Model Name: T650QVJ02.0

Issue Date : 2013/04/23

( )Preliminary Specifications

(＊＊＊＊)Final Specifications

Customer Signature Date AUO Date

Approved By

_________________________________

Note

Approval By PM Director

CP Wang

____________________________________

Reviewed By RD Director

Eugene CC Chen

____________________________________

Reviewed By Project Leader

Stanley Lo

__________ __________________________

Prepared By PM

Mick Chen

____________________________________

Contents

T650QVJ02.0 Product Specification

Rev 1.0

No

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATION

3-1 ELECTRIACL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATION

3-4 SIGNAL TIMING WAVEFORM

3-5 COLOR INPUT DATA REFERENCE

3-6 POWER SEQUENCE

3-7 BACKLIGHT SPECIFICATION

4 OPTICAL SPECIFICATION

5 MECHANICAL CHARACTERISTICS

6 RELIABILITY TEST ITEMS

7 INTERNATIONAL STANDARD

7-1 SAFETY

7-2 EMC

8 PACKING

8-1 DEFINITION OF LABEL

8-2 PACKING METHODS

8-3 PALLET AND SHIPMENT INFORMATION

9 PRECAUTION

9-1 MOUNTING PRECAUTIONS

9-2 OPERATING PRECAUTIONS

9-3 ELECTROSTATIC DISCHARGE CONTROL

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

9-5 STORAGE

9-6 HANDLING PRECAUTIONS FOR PROTECT FILM

Record of Revision

T650QVJ02.0 Product Specification

Rev 1.0

Version

0.1 2013/01/14 First release

0.2 2013/01/29 7 Update Part 3 electrical spec

0.3 2013/01/29 20 Update LCD power connector

0.4 2013/01/30 31 Update mechanical drawing

0.5 2013/01/31 7 Update I2C spec

0.6 2013/01/31 7,11 Update DC characteristics & LVDS 51pin assignment

0.7 2013/02/07 11 Change 51pin; pin 7 function decription

0.8 2013/03/26 7 DC/AC characteristics

14 Timing spec

15,16 Timing waveform

18 Update Power sequence

23 Revise Color coordination spec

11 51pin, pin1 change

0.9 2013/04/12 11 51pin, pin3 change

1.0 2013/04/23 34 Revise safety information: E204358E204356

Date Page Description

T650QVJ02.0 Product Specification

Rev 1.0

1. General Description

This specification applies to the 65 inch Color TFT-LCD Module T650QVJ02.0. This LCD module has a TFT active

matrix type liquid crystal panel 3,840x2,160 pixels, and diagonal size of 65 inch. This module supports 3,840x2,160

mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes. Gray

scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.

The T650QVJ02.0 has been designed to apply the 10-bit LVDS interface method. It is intended to support displays

where high brightness, wide viewing angle, high color saturation, and high color depth are very important. Also, 3D

function is also embedded into front glass as pattern retarder.

* General Information

Items Specification Unit Note

Active Screen Size 65 inch

Display Area 1428.48(H) x 803.52(V) mm

Outline Dimension 1454.3(H) x 831.5 (V) x 18(D) mm D: front bezel to back bezel

Driver Element a-Si TFT active matrix

Bezel Opening

Display Colors 10 bit, 16.7M Colors

Number of Pixels 3840x2160 Pixel

Pixel Pitch 0.372 (H) x 0.372(W) mm

Pixel Arrangement RGB vertical stripe

Display Operation Mode Normally Black

Rotate Function Unachievable Note 1

Display Orientation Signal input with “ABC” Note 2

Note 1: Rotate Function refers to LCD display could be able to rotate.

Note 2: LCD display as below illustrated when signal input with “ABC”.

1434.5 (H) x 809.6 (V)

mm

T650QVJ02.0 Product Specification

2. Absolute Maximum Ratings

The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit

Rev 1.0

Item Symbol

Logic/LCD Drive Voltage VDD -0.3 14 [Volt] Note 1

Input Voltage of Signal Vin -0.3 4 [Volt] Note 1

Operating Temperature TOP 0 +50 [oC] Note 2

Operating Humidity HOP 10 90 [%RH] Note 2

Storage Temperature TST -20 +60 [oC] Note 2

Storage Humidity HST 10 90 [%RH] Note 2

Panel Surface Temperature PST 65 [oC] Note 3

Note 1: Duration:50 msec.

Note 2 : Maximum Wet-Bulb should be 39 and No condensation.℃

The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures greater

than 40 , the wet bulb temperature must not exceed 39 .

Note 3: Surface temperature is measured at 50℃ Dry condition

℃ ℃

Min Max Unit Conditions

℃

T650QVJ02.0 Product Specification

Rev 1.0

3. Electrical Specification

The T650QVJ02.0 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT array

and liquid crystal. The other is to power Back Light Unit.

3.0 ASIC feature

 Input resolution FHD120Hz / UHD 30Hz/ 4k1k 30Hz switchable

 MEMC Function with High/Middle/Low level

 2D / 3D switchable

 Video Mute Function

 OSD protection function

3.1 Electrical Characteristics

3.1.1: DC Characteristics

T650QVJ02.0 Product Specification

Rev 1.0

Parameter Symbol

Unit Note

Min. Typ. Max

LCD

Power Supply Input Voltage (for input power=12V) VDD 10.8 12 13.2 VDC

Power Supply Input Current (Define to section:1.1) IDD -- 1.8 3.7 A 1

Value

Inrush Current (Define to section:1.1) I

Permissible Ripple of Power Supply Input Voltage (for input power=12V)

Input Differential Voltage

LVDS

Interface

Differential Input High Threshold Voltage VTH +100 -- +300 mVDC 4

Differential Input Low Threshold Voltage VTL -300 -- -100 mVDC 4

Input Common Mode Voltage V

CMOS

Interface

Input High Threshold Voltage

Input Low Threshold Voltage

-- -- 5 A 2

RUSH

VRP -- --

∣

V

∣

ID

1.1 1.25 1.4 VDC 4

ICM

VIH

(High)

VIL

(Low)

200 400 600 mVDC 4

2.0 -- 3.3 VDC 5

0 -- 0.8 VDC 5

VDD *

5%

mV

pk-pk

3

3.1.2: AC Characteristics

Parameter Symbol

Receiver Clock : Spread Spectrum Modulation range

LVDS Interface

Receiver Clock : Spread Spectrum Modulation frequency

Receiver Data Input Margin Fclk = 150 MHz Fclk = 85 MHz

SCL clock frequency F

I2C clock high level T I2C Interface

I2C clock low level T

I2C data setup time T

I2C data hold time T

SDA and SCL rise time TR -- -- 0.3 us

SDA and SCL fall time TF -- -- 0.3 us

Value

Unit Note

Min. Typ. Max

Fclk_ss

Fss

tRMG

SCL

SCHi

SCLo

SDS

SDH

Fclk

-3%

50

-0.15

-0.4

-- --

--

0.6 -- -- us

1.3 -- -- us

0.1 -- -- us 0 -- 900 us

Fclk

+3%

200

MHz 6

KHz

0.15

0.4

ns

400 KHZ

6

7

3.1.3: Driver Characteristics

s

µ

Item Symbol Min Max Unit condition

T650QVJ02.0 Product Specification

Rev 1.0

Driver Surface Temperature DST 100

Any point on the driver surface must be less than 100

℃℃℃℃

under any condition

Note:

1. Test Condition:

(1) V (2) Fv = Type Timing 120Hz (3) Fclk= Max freq. (4) Temperature = 25 ℃ (5) Typ. Input current : White Pattern

>> refer to “Section:3.3 Signal Timing Specification, Typical timing”

2. Measurement condition : Rising time = 400us

= 12.0V

DD

Max. Input current: Heavy loading pattern defined by AUO

90%

GND

GNDGND

10%

[℃]

Note

VVVV

DD

DDDD

3. Test Condition:

(1) The measure point of V (2) Under Max. Input current spec. condition.

4. V

= 1.25V

ICM

L V D S -

V

IC M

L V D S +

G N D

0 V

is in LCM side after connecting the System Board and LCM.

RP

400

400400

|VID|

V

T H

|VID|

V

T L

|VID|

T650QVJ02.0 Product Specification

5. The measure points of V

6. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures.

7. Receiver Data Input Margin

and V

IH

Fclk

Fclk____ss

FclkFclk

ss((((max

ssss

Fclk

FclkFclk

Fclk

Fclk____ss

FclkFclk

ss((((min

ssss

are in LCM side after connecting the System Board and LCM.

IL

1111////FFFF

SS

SSSS

max))))

maxmax

min))))

minmin

Rev 1.0

Parameter Symbol

Min Type Max

Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz

Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns

Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns

Input Data Position2 tRIP6 2T/7-|tRMG|

Input Data Position3 tRIP5 3T/7-|tRMG|

Input Data Position4 tRIP4 4T/7-|tRMG|

Input Data Position5 tRIP3 5T/7-|tRMG|

Input Data Position6 tRIP2 6T/7-|tRMG|

Rating

Unit

2T/7 2T/7+|tRMG| ns

3T/7 3T/7+|tRMG| ns

4T/7 4T/7+|tRMG| ns

5T/7 5T/7+|tRMG| ns

6T/7 6T/7+|tRMG| ns

tRIP2

tRIP3

tRIP4

tRIP5

Note

T=1/Fclk

tRIP6

tRIP0

tRIP1 LVDS-Rx Input Data

Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Rx2Rx3

LVDS-Rx

VVVV

=

= 0000VVVV

= =

diff

Input Clock

diff diff

1/Fclk=T

3.2 Interface Connections

3.2.1: LVDS connector control and I2C pin description

T650QVJ02.0 Product Specification

Rev 1.0

Note * : Open/High(3.3V)

Note **** : SCL/SDA

Note ** : Open/Low(GND)

Note ***** : WP

3.2.2: LVDS Pin-Assignment



LCD connector: 187059-51221-1 (JAE, LVDS connector)

T650QVJ02.0 Product Specification

Rev 1.0

187060-41221-1 (JAE, LVDS connector)



Mating connector:

1 2 3 4 5 6

7

8 9

10

11 12 13 14 15 16 17 18 19 CH1_CLK- LVDS Channel 1, Clock - 44 20 CH1_CLK+ LVDS Channel 1, Clock + 45 21

22

23

24

25

Symbol Description PIN

N.C AUO Internal Use Only 26 SCL I2C Serial Clock 27 N.C AUO Internal Use Only 28

SDA I2C Serial Data 29

N.C AUO Internal Use Only 30 N.C AUO Internal Use Only 31

SELLVDS

N.C AUO Internal Use Only 33 N.C AUO Internal Use Only 34 N.C AUO Internal Use Only 35

GND Ground 36 CH2_CLK+ LVDS Channel 2, Clock +

CH1_0- LVDS Channel 1, Signal 0- 37

CH1_0+ LVDS Channel 1, Signal 0+ 38

CH1_1- LVDS Channel 1, Signal 1- 39

CH1_1+ LVDS Channel 1, Signal 1+ 40

CH1_2- LVDS Channel 1, Signal 2- 41

CH1_2+ LVDS Channel 1, Signal 2+ 42

GND Ground 43

GND Ground 46

CH1_3- LVDS Channel 1, Signal 3- 47

CH1_3+ LVDS Channel 1, Signal 3+ 48

CH1_4- LVDS Channel 1, Signal 4- 49

CH1_4+ LVDS Channel 1, Signal 4+ 50

LVDS Format Select

Open/High(3.3V) for JEIDA,

Low(GND) for NS

51

32

Symbol Description

GND Ground GND Ground

CH2_0- LVDS Channel 2, Signal 0-

CH2_0+ LVDS Channel 2, Signal 0+

CH2_1- LVDS Channel 2, Signal 1-

CH2_1+ LVDS Channel 2, Signal 1+

CH2_2- LVDS Channel 2, Signal 2-

CH2_2+ LVDS Channel 2, Signal 2+

GND Ground

CH2_CLK- LVDS Channel 2, Clock -

GND Ground

CH2_3- LVDS Channel 2, Signal 3-

CH2_3+ LVDS Channel 2, Signal 3+

CH2_4- LVDS Channel 2, Signal 4-

CH2_4+ LVDS Channel 2, Signal 4+

GND Ground

GND Ground GND Ground GND Ground

N.C.

N.C AUO Internal Use Only

No connection (for AUO test only.

Do not connect)

No connection (for AUO test only.

Do not connect)

No connection (for AUO test only.

Do not connect)

No connection (for AUO test only.

Do not connect)

No connection (for AUO test only.

Do not connect)

Note: N.C. : please leave this pin unoccupied. It can not be connected by any signal (Low/GND/High).

T650QVJ02.0 Product Specification

No connection (for AUO test only. Do

Do

No connection (for AUO test only. Do

. Do

No connection (for AUO test only. Do

only. Do

Rev 1.0

PIN Symbol Description PIN

1

2

3

4

5

6

7

8

9 10 CH3_0- LVDS Channel 3, Signal 0- 30 11 CH3_0+ 12 CH3_1- LVDS Channel 3, Signal 1- 32 13 CH3_1+ 14 CH3_2- LVDS Channel 3, Signal 2- 34 CH4_CLK+ LVDS Channel 4, Clock + 15 CH3_2+ 16 17 CH3_CLK18 CH3_CLK+ 19 20 CH3_3- LVDS Channel 3, Signal 3- 40

N.C.

GND Ground 29

GND Ground 36

GND Ground 39

No connection (for AUO test only.

No connection (for AUO test only

No connection (for AUO test

LVDS Channel 3, Signal 0+ 31

LVDS Channel 3, Signal 1+ 33 CH4_CLK- LVDS Channel 4, Clock -

LVDS Channel 3, Signal 2+ 35

not connect)

LVDS Channel 3, Clock - 37

LVDS Channel 3, Clock + 38

41

21

22

23

24

25

26

27

28

Symbol Description

CH3_3+ LVDS Channel 3, Signal 3+

CH3_4- LVDS Channel 3,Signal 4-

CH3_4+ LVDS Channel 3,Signal 4+

GND Ground

CH4_0- LVDS Channel 4, Signal 0-

CH4_0+ LVDS Channel 4, Signal 0+

CH4_1- LVDS Channel 4, Signal 1-

CH4_1+ LVDS Channel 4, Signal 1+

CH4_2- LVDS Channel 4, Signal 2-

CH4_2+ LVDS Channel 4, Signal 2+

GND Ground

CH4_3- LVDS Channel 4, Signal 3-

CH4_3+ LVDS Channel 4, Signal 3+

CH4_4- LVDS Channel 4,Signal 4-

CH4_4+ LVDS Channel 4,Signal 4+

GND Ground GND Ground

Note: N.C. : please leave this pin unoccupied. It can not be connected by any signal (Low/GND/High).



PI

N

1

2

3

4

5

6

7

8

9

10

11

12

LCD Power connector:

Power CN(12pin)：MSAK242151P12R (STM)

Symbol Description

PWR Power 12V IN PWR Power 12V IN

NC NC Pin

GND Ground

3.2.3: LVDS Option

 LVDS Option = LowNS

P re v i o u s C y cle C u rr e n t C y cle N e x t C y c le

P re v i o u s C y cle C u rr e n t C y cle N e x t C y c le P re v i o u s C y cle C u rr e n t C y cle N e x t C y c le

C lo c k

C lo c kC lo ck

C H x

C H x ____ 0000 ++++

C H xC H x

C H x

C H x ____ 0000 ----

C H xC H x

C H x

C H x ____ 1111 ++++

C H xC H x

C H x

C H x ____ 1111 ----

C H xC H x

C H x

C H x ____ 2222 ++++

C H xC H x

C H x

C H x ____ 2222 ----

C H xC H x

D EBBBB 2222BBBB 3333 BBBB 4444BBBB 5555N A

D ED E

T650QVJ02.0 Product Specification

RRRR 0000RRRR 5555 GGGG 0000GGGG 0000RRRR 0000RRRR 1111 RRRR 2222RRRR 3333RRRR 4444 RRRR 1111

GGGG 1111BBBB 0000 BBBB 1111BBBB 1111GGGG 1111GGGG 2222 GGGG 3333GGGG 4444GGGG 5555 GGGG 2222

N A D E

N AN A

N A BBBB 3333

N AN A

BBBB 2222N A

D ED E

Rev 1.0

C H x

C H x ____ 3333 ++++

C H xC H x

C H x

C H x ____ 3333 ----

C H xC H x

C H x

C H x ____ 4444 ++++

C H xC H x

C H x

C H x ____ 4444 ----

C H xC H x

N ARRRR 6666RRRR 7777 GGGG 6666GGGG 7777BBBB 6666 RRRR 7777

N AN A

N ARRRR 8888RRRR 9999 GGGG 8888GGGG 9999BBBB 8888 RRRR 9999

N AN A

Note: x = 1, 2, 3, 4…

 LVDS Option = High/OpenJEIDA

P re v io u s C yc le C u r r e nt C y c le N e x t C y c le

P re v io u s C yc le C u r r e nt C y c le N e x t C y c le P re vio u s C y c le C urre n t C yc l e N ex t C y c l e

C lo c k

C lo c kC lo c k

C H x

C H x ____ 0000 ++++

C H xC H x C H x

C H x ____ 0000 ----

C H xC H x

C H x

C H x ____ 1111 ++++

C H xC H x C H x

C H x ____ 1111 ----

C H xC H x

C H x

C H x ____ 2222 ++++

C H xC H x C H x

C H x ____ 2222 ----

C H xC H x

D EBBBB 6666BBBB 7777 BBBB 8888BBBB 9999N A

D EDE

N A D E

N ANA

N A BBBB 7777

N AN A

RRRR 6666BBBB 7777 N A

RRRR 8888BBBB 9999 N A

RRRR 4444RRRR 9999 GGGG 4444GGGG 4444RRRR 4444RRRR 5555 RRRR 6666RRRR 7777RRRR 8888 RRRR 5555

GGGG 5555BBBB 4444 BBBB 5555BBBB 5555GGGG 5555GGGG 6666 GGGG 7777GGGG 8888GGGG 9999 GGGG 6666

BBBB 6666N A

N AN A

D ED E

C H x

C H x ____ 3333 ++++

C H xC H x C H x

C H x ____ 3333 ----

C H xC H x

C H x

C H x ____ 4444 ++++

C H xC H x C H x

C H x ____ 4444 ----

C H xC H x

N ARRRR 2222RRRR 3333 GGGG 2222GGGG 3333BBBB 2222 RRRR 3333

N ANA

N ARRRR 0000RRRR 1111 GGGG 0000GGGG 1111BBBB 0000 RRRR 1111

N ANA

RRRR 2222BBBB 3333 N A

RRRR 0000BBBB 1111 N A

N AN A

N ANA

Note: x = 1, 2, 3, 4

T650QVJ02.0 Product Specification

3.3 Signal Timing Specification

UHD (4K2K) 3840x2160 LVDS 4ch Timing Table (960x2160 @30Hz)

Vertical Section Horizontal Section Frequency

Rev 1.0

Input Timing

4K2K30Hz 2160 2250 76 90 104 3840 4400 516 560 604

Active

Tdisp(v)

Period Tv Blanking Tblk(v) Period Th Blanking Tblk(h) Pixel Clock (MHz)

Typ. Min. Typ. Max.

Active

Tdisp(h)

Typ. Min. Typ. Max. Min. Typ. Max.

FHD 1920x1080 LVDS 4ch Timing Table (480x1080 @120Hz)

Vertical Section Horizontal Section Frequency

Input Timing

FHD120Hz 1080 1125 38 45 52 1920 2200 252 280 304

Active

Tdisp(v)

Period Tv Blanking Tblk(v) Period Th Blanking Tblk(h) Pixel Clock (MHz)

Typ. Min. Typ. Max.

Active

Tdisp(h)

Typ. Min. Typ. Max. Min. Typ. Max.

233.8

243.7

292.2

234

243.9

293.5

Frame

Rate (Hz)

- 237.6

- 247.5

- 297.2

- 237.6

- 247.5 100

- 297.2 120

24

25

30

Frame

Rate (Hz)

96

4K1K 3840x1080 LVDS 2ch Timing Table (1920x1080 @30Hz)

Vertical Section Horizontal Section Frequency

Input Timing

4K1K30Hz 1080 1125 38 45 52 3840 4400 516 560 604

Active

Tdisp(v)

Period Tv Blanking Tblk(v) Period Th Blanking Tblk(h) Pixel Clock (MHz)

Typ. Min. Typ. Max.

Active

Tdisp(h)

Typ. Min. Typ. Max. Min. Typ. Max.

116.9

121.8

146.1

- 118.8

- 123.8

- 148.5

Frame

Rate (Hz)

24

25

30

T650QVJ02.0 Product Specification

3.4 Signal Timing Waveforms

- 4K1K 3840x1080 LVDS 2ch Timing Table (1920x1080 @30Hz)

Rev 1.0

T650QVJ02.0 Product Specification

- FHD 1920x1080 LVDS 4ch Timing Table (480x1080 @120Hz)

- QFHD 3840x2160 LVDS 4ch Timing Table (960x2160 @30Hz)

Rev 1.0

Basic

T650QVJ02.0 Product Specification

Rev 1.0

3.5 Color Input Data Reference

The brightness of each primary color (red, green and blue) is based on the 10 bit gray scale data input for the color;

the higher the binary input, the brighter the color. The table below provides a reference for color versus data input.

COLOR DATA REFERENCE

Input Color Data

Color

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

Blue(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Color

Cyan 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Magenta 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RED(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(001) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R

----

RED(1022) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

RED

MSB LSB

GREEN

BLUE

MSB LSB

GREEN(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GREEN(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

G

----

GREEN(1022) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

GREEN(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

BLUE(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

B

----

BLUE(1022) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0

BLUE(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

3.6 Power Sequence for LCD

T650QVJ02.0 Product Specification

Rev 1.0

Values

Parameter

Unit

Min. Type. Max.

t1 0.4 --- 30 ms

t2 0.1 --- 50 ms

t3 2000 --- --- ms

t4 0*1 --- --- ms

t5 0 --- --- ms

t6 --- --- ---*2 ms

t7 500 --- --- ms

t8 10*3 --- 50

ms

t9 0 --- --- ms

t10 2000 --- --- ms t11 150 --- --- ms

Note: (1) t4=0 : concern for residual pattern before BLU turn off. (2) t6 : voltage of VDD must decay smoothly after power-off. (customer system decide this value) (3) When CMOS Interface signal is N.C. (no connection), opened in Transmitted end, t8 timing spec can be

negligible.

3.7 Backlight Specification

The backlight unit contains 8pcs light bar.

3.7.1 Light bar Driven Condition

Item Symbol Condition

T650QVJ02.0 Product Specification

Rev 1.0

Spec

Unit Note

Min Typ Max

1

2

3

4

Input Voltage VDDB - 22.8

Input Current I

Input Power P

Inrush Current I

VDDB=24V

DDB

VDDB=24V

DDB

VDDB=24V

RUSH

Hi 2 - 5.5 -

5 Control signal voltage

V

Signal

VDDB=24V

Low

6 Control signal current

External PWM Duty ratio

7

8

(input duty ratio)

External PWM

Frequency

I

VDDB=24V

Signal

D_EPWM VDDB=24V

F_EPWM VDDB=24V 140 180 240 Hz 4,5

HI Open Collector VDC 6

9

DET status signal DET

VDDB=24V

Lo

10

Input Impedance Rin VDDB=24V 300 Kohm -

Note 1: Dimming ratio= 100%,（Ta=25±5℃, Turn on for 45minutes）

7.23 7.77

173.6 186.5

24 25.2

16.3

VDC -

ADC 1

W 1

Apeak 2

VDC

0 - 0.8

3

- - 1.5 mA -

0 - 100 % 4,5

0 - 0.8 VDC 6

Note 2: MAX input current at all operating mode, measurement condition Rising time = 20ms (VDDB: 10%~90%)

Note 3: When BLU off ( VDDB = 24V , VBLON = 0V) , IDDB (max) = 0.1A

Note 4: Less than 5% dimming control is functional well and no backlight shutdown happened

Note 5: D_EPWM and F_EPWM are available only at 2D mode

Note 6: Normal: 0~0.8V ; Abnormal : Open collector

3.7.2 Input Pin Assignment



LED DB connector: CI0114M1HR0-NH(CviLux) or equivalent

T650QVJ02.0 Product Specification

Rev 1.0

CI0112M1HR0-NH(CviLux) or equivalent

Pin Symbol Description

1 VDDB Operating Voltage Supply, +24V DC regulated

2 VDDB Operating Voltage Supply, +24V DC regulated

3 VDDB Operating Voltage Supply, +24V DC regulated

4 VDDB Operating Voltage Supply, +24V DC regulated

5 VDDB Operating Voltage Supply, +24V DC regulated

6 BLGND Ground and Current Return

7 BLGND Ground and Current Return

8 BLGND Ground and Current Return

9 BLGND Ground and Current Return

10 BLGND Ground and Current Return

BLU status detection:

11 DET

12 VBLON

13 NC NC

14 PDIM(*) External PWM (0%~100% Duty, open for 100%)

Normal : 0~0.8V ; Abnormal : Open collector

(Recommend Pull high R > 10K, VDD = 3.3V)

BLU On-Off control:

High/Open (2~5.5V) : BL On ;

Low (0~0.8V/GND) : BL Off

T650QVJ02.0 Product Specification

Rev 1.0

Pin Symbol Description

1 VDDB Operating Voltage Supply, +24V DC regulated

2 VDDB Operating Voltage Supply, +24V DC regulated

3 VDDB Operating Voltage Supply, +24V DC regulated

4 VDDB Operating Voltage Supply, +24V DC regulated

5 VDDB Operating Voltage Supply, +24V DC regulated

6 BLGND Ground and Current Return

7 BLGND Ground and Current Return

8 BLGND Ground and Current Return

9 BLGND Ground and Current Return

10 BLGND Ground and Current Return

11 NC NC

12 NC NC

(Note*) PWM Dimming range:

IF External PWM function less than 5% dimming ratio, Judge condition as below: (1)Backlight module must be lighted ON normally. (2)All protection function must work normally. (3)Uniformity and flicker could not be guaranteed

Valid Dimming

3.7.3 Power Sequence for Backlight

24V(typ.)

Power Input for BLU

(VDDB)

90% 90%

10%

T650QVJ02.0 Product Specification

Rev 1.0

10%

Control Signal

(V_IPWM,V_EPWM)

BLU On/Off Enable

(VBLON)

Dip condition

Power Input for BLU

(VDDB)

VDDB(typ .)*0.8

T1 T2

T3

T6

T5

T4

Parameter

Value

Min Typ Max

T1 20 - - ms *1

T2 250 - -

T3 200

T4 0 - -

T5 0 - -

T6 - 1000

Units

ms

ms*2

T650QVJ02.0 Product Specification

Rev 1.0

4. Optical Specification

Optical characteristics are determined after the unit has been ‘ON’ and stable for approximately 45 minutes in a

dark environment at 25°C. The values specified are at an approximate distance 50cm from the LCD surface at a

viewing angle of φ and θ equal to 0°.

Fig.1 presents additional information concerning the measurement equipment and method.

SR3 or equivalent

Parameter Symbol

Min. Typ. Max

Contrast Ratio CR 3200 4000 -- 1

L

(2D) 360 450 -- cd/m2 2

Surface Luminance (White)

Luminance Variation δ

Response Time (G to G) Tγ -- 5.5 -- ms 4

Color Gamut NTSC 72 %

Color Coordinates

Red RX 0.640

RY 0.330

Green GX 0.300

GY 0.600

Blue BX 0.150

BY 0.050

White WX 0.280

WH

L

(3D) 180 6

WH

WHITE(9P)

-- -- 1.3 3

Typ.-0.03

Values

Unit Notes

Typ.+0.03

WY

Viewing Angle 5

x axis, right(φ=0°) θr -- 89 -- degree

2D

3D y axis, up + down θu + θd 12 16 degree

3D cross talk (middle)

x axis, left(φ=180°) θl -- 89 -- degree

y axis, up(φ=90°) θu -- 89 -- degree

y axis, down (φ=270°) θ

-- 89 -- degree

d

-- 1

0.290

6

3 % 6

2 3

7

T650QVJ02.0 Product Specification

Rev 1.0

Note:

1. Contrast Ratio (CR) is defined mathematically as:

Surface Luminance of

Contrast Ratio=

Surface Luminance of

2. Surface luminance is luminance value at point 5 across the LCD surface 50cm from the surface with all pixels

displaying white. From more information see FIG 2. When LED current IF = typical value (without driver board),

L

on5

L

off5

LED input VDDB =24V, I

. = Typical value (with driver board), LWH=Lon5 where Lon5 is the luminance with all

DDB

pixels displaying white at center 5 location.

FIG. 2 Luminance

V

H/2

H/6

1

H

V/2 V/6

3. The variation in surface luminance, δWHITE is defined (center of Screen) as:

δ

WHITE(9P)

4. Response time Tγ is the average time required for display transition by switching the input signal for five

= Maximum(L

on1

, L

on2

,…,L

)/ Minimum(L

on9

on1

, L

on2

,…L

on9

)

luminance ratio (0%,25%,50%,75%,100% brightness matrix) and is based on Fv=120Hz to optimize.

Target Measured

Response Time

0%

25%

Start

50%

75%

100%

Tγ is determined by 10% to 90% brightness difference of rising or falling period. (As illustrated)

The response time is defined as the following figure and shall be measured by switching the input signal for “any level of gray(bright) “ and “any level of gray(dark)”.

0% 25% 50% 75% 100%

0% to 25% 0% to 50% 0% to 75% 0% to 100%

25% to 0% 25% to 50% 25% to 75% 25% to 100%

50% to 0% 50% to 25%

75% to 0% 75% to 25% 75% to 50%

100% to 0% 100% to 25% 100% to 50% 100% to 75%

50% to 75% 50% to 100%

75% to 100%

T650QVJ02.0 Product Specification

Any level of gray (Bright) Any level of gray (Dark) Any level of gray (Bright)

Rev 1.0

0% , 25%, 50% , 75%, 100%

100%

90%

0% , 25%, 50% , 75%, 100%

Photodetector

Output

10%

0% , 25%, 50% , 75%, 100%

Time

T

(F)

γγγγ

5. Viewing angle is the angle at which the contrast ratio is greater than 10. The angles are determined for the

horizontal or x axis and the vertical or y axis with respect to the z axis which is normal to the LCD surface. For

more information see FIG3.

T

γγγγ

(R)

FIG.3 Viewing Angle

6. 3D performance specification is expressed by 3D luminance, 3D Crosstalk and 3D viewing angle. 3D

luminance which is defined by average of left and right eye brightness under wearing glasses condition is

measured at panel center point. Also, 3D crosstalk is measured at panel center point.

a. Cross talk (middle) is defined by observation position which is 2.4m distance from panel center point and

human head in 0 degree steady vertical angle from panel mid axis level.

b. Cross talk (in vertical viewing angle) is defined by observation position which is 2.4m distance from panel

T650QVJ02.0 Product Specification

center point and observation range within specified degrees of vertical angle from panel mid axis level, and the

value is limited by 10%.

For more information, refer to 6-5 3D Measurement of 3D view angle.

6-1 Notation of measurement.

Rev 1.0

Glasses type:

R: right eyeglass

L: left eyeglass

C: without

RL (W,K)

Left eye gray level

6-2 Measurement Configuration

4-test patterns (first character refers to Left eye gray level; second one refers to Right eye gray level).

W is defined as brightness gray level; K is defined as dark state where black and white lines are displayed

on even or odd lines.

Measurement Code:

L: Luminance

Right eye gray level

Odd line

Even line

6-3 Measurement of 3D luminance

a. Test pattern WW is displayed, measuring distance is 50cm.

b. Left or right eyeglass are placed in front of SR3 or equivalent equipment (as FIG1 showed)

successively and luminance is measured at panel center point where the notation for luminance

measurement is RL(W,W) and LL(W,W).

2

−

6-4 Measurement of 3D Crosstalk

a. Test patterns KW, WK and KK are displayed, measuring distance is 1.2m.

b. Right or left eyeglass is placed in front of SR3 or equivalent equipment (as FIG1 showed) successively

T650QVJ02.0 Product Specification

Rev 1.0

),(),(

3

LumD

=

+

WWLWWR

LL

and luminance is measured at panel center point

6-5 Measurement of 3D view angle

The angles are determined for the vertical or y axis with respect to the z axis which is normal to the LCD

module surface and measured at panel center position.

Crosstalk

=

R

=

L

Crosstalk+=

LL

−

LL

−

LL

),(),(

KKRWKR

),(),(

KKLWKL

),(),(

KKLKWL

CrosstalkCrosstalk

%100

×

%100

×

LR

),(),(

KKRKWR

T650QVJ02.0 Product Specification

Rev 1.0

5. Mechanical Characteristics

The contents provide general mechanical characteristics for the model T650QVD01.1. In addition the figures in the

next page are detailed mechanical drawing of the LCD.

Item Dimension Unit Note

Horizontal 1455.3 mm

Vertical 832.5 mm

Outline Dimension

Depth (Dmin) 18 mm

Depth (Dmax) 29.3 mm to T-con cover

Weight 27100 g w/o DB

front bezel to back

bezel

Front View

T650QVJ02.0 Product Specification

Rev 1.0

T650QVJ02.0 Product Specification

Rev 1.0

Back View

T650QVJ02.0 Product Specification

Rev 1.0

T650QVJ02.0 Product Specification

Rev 1.0

Reliability Test Items

1 Wet and High Temperature Storage test

2 Low temperature storage test 3

3 High temperature operation test 3

4 Low temperature operation test 3

5 Vibration test (With carton) 5/carton

6 Drop test (With carton) 5/carton

Test Item Q’ty Condition

60℃, Humidity 75% 300hrs

3

-20℃, 300hrs

50℃, 300hrs

-10℃, 300hrs

*Wave form, Random

*Overall average energy level : 1.04Grms

*Bandwidth & Level, 2~200Hz

*Duration, X,Y,Z 20min per axes

Height: 25.4 cm

Direction: Only bottom flat twice

(ASTMD4169-I)

7. International Standard

7.1 Safety

(1) UL 60950-1, UL 60065; Standard for Safety of Information Technology Equipment Including

electrical Business Equipment.

(2) IEC 60950-1 : 2001, IEC 60065:2001 ; Standard for Safety of International Electrotechnical

Commission

(3) EN 60950 : 2001+A11, EN 60065:2002+A1:2006; European Committee for Electrotechnical

Standardization (CENELEC), EUROPEAN STANDARD for Safety of Information Technology

Equipment Including Electrical Business Equipment.

7.2 EMC

(1) ANSI C63.4 “Methods of Measurement of Radio-Noise Emissions from Low-Voltage Electrical and

Electrical Equipment in the Range of 9kHz to 40GHz. “American National standards Institute(ANSI),

T650QVJ02.0 Product Specification

Rev 1.0

1992

(2) C.I.S.P.R “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” International Special committee on Radio Interference.

(3) EN 55022 “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” European Committee for Electrotechnical Standardization. (CENELEC),

1998

QTY :

5

Manufactured

XX/XX

MADE IN

XXXXX

8. Packing

8-1 DEFINITION OF LABEL:

A. Panel Label:

*xxxxxxxxxxxx-xxxx*

T650QVJ02.0 Product Specification

Rev 1.0

Panel Unique ID

XXXXX Model NO: T650QVJ02.0 XXXXXXX

Green mark description

Year

AUO Internal Use

AU Optronics

Week Factory Location AUO Internal Use

AUO Internal Use

(1) For Pb Free Product, AUO will add for identification.

(2) For RoHs compatible products, AUO will add RoHS for identification.

Note: The green Mark will be present only when the green documents have been ready by AUO internal

green team. (definition of green design follows the AUO green design checklist.)

B. Carton Label:

T650QVJ02.0

93.65T23.000

1pcs Mod

1pcs Mod1pcs Mod

1pcs Mod

ule/ESD Bag

ule/ESD Bagule/ESD Bag

ule/ESD Bag

Cushion top

Cushion topCushion top

Cushion top

Module

5

5 5

5

pcs / 1 carton

pcs / 1 cartonpcs / 1 carton

pcs / 1 carton

”

H ” Tape

Cushion down

Cushion downCushion down

Cushion down

Cushion set

Cushion setCushion set

Cushion set

8-2 PACKING METHODS:

T650QVJ02.0 Product Specification

Rev 1.0

8-3 Pallet and Shipment Information

T650QVJ02.0 Product Specification

Rev 1.0

Specification

Item

1 Packing Box 5 pcs/box 1565(L)mm*380(W)mm*978(H)mm 165

2 Pallet 1 1660(L)mm*1150(W)mm*144(H)mm 20

3 Boxes per Pallet 5 boxes/Pallet (By Air) ; 3 Boxes/Pallet (By Sea)

4 Panels per Pallet 25 pcs/pallet(By Air) ; 15 pcs/Pallet (By Sea)

after packing

Qty. Dimension Weight (kg)

15 (by Air) 1660(L)mm*1150(W)mm*1122(H)mm 465(by Air)

30 (by Sea) 1660(L)mm*1150(W)mm*2244(H)mm 930(by Sea) 40ft HQ

Corner angle

Moisture-proof film

Packing

Remark

5 Pallet

Stretch film

Label

PET band

Corner angle

Pallet

9. PRECAUTIONS

Please pay attention to the followings when you use this TFT LCD module.

9-1 MOUNTING PRECAUTIONS

(1) You must mount a module using holes arranged in four corners or four sides.

(2) You should consider the mounting structure so that uneven force (ex. twisted stress) is not applied

to module. And the case on which a module is mounted should have sufficient strength so that

external force is not transmitted directly to the module.

(3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer.

Transparent protective plate should have sufficient strength in order to the resist external force.

(4) You should adopt radiation structure to satisfy the temperature specification.

(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former

T650QVJ02.0 Product Specification

Rev 1.0

generates corrosive gas of attacking the polarizer at high temperature and the latter cause circuit

broken by electro-chemical reaction.

(6) Do not touch, push or rub the exposed polarizer with glass, tweezers or anything harder than HB

pencil lead. And please do not rub with dust clothes with chemical treatment. Do not touch the

surface of polarizer for bare hand or greasy cloth. (Some cosmetics are detrimental to the polarizer.)

(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials

like chamois soaks with petroleum benzene. Normal-hexane is recommended for cleaning the

adhesives used to attach front/ rear polarizer. Do not use acetone, toluene and alcohol because

they cause chemical damage to the polarizer.

(8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes

deformations and color fading.

(9) Do not open the case because inside circuits do not have sufficient strength.

9-2 OPERATING PRECAUTIONS

(1) The device listed in the product specification sheets was designed and manufactured for TV

application

(2) The spike noise causes the mis-operation of circuits. It should be lower than following voltage:

V=±200mV(Over and under shoot voltage)

(3) Response time depends on the temperature. (In lower temperature, it becomes longer..)

(4) Brightness of CCFL depends on the temperature. (In lower temperature, it becomes lower.) And in

lower temperature, response time (required time that brightness is stable after turned on) becomes

longer.

(5) Be careful for condensation at sudden temperature change. Condensation makes damage to

polarizer or electrical contacted parts. And after fading condensation, smear or spot will occur.

(6) When fixed patterns are displayed for a long time, remnant image is likely to occur.

(7) Module has high frequency circuits. Sufficient suppression to the electromagnetic interference shall

be done by system manufacturers. Grounding and shielding methods may be important to minimize

the interface.

9-3 ELECTROSTATIC DISCHARGE CONTROL

Since a module is composed of electronic circuits, it is not strong to electrostatic discharge. Make certain

that treatment persons are connected to ground through wristband etc. And don’t touch interface pin

directly.

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

Strong light exposure causes degradation of polarizer and color filter.

9-5 STORAGE

When storing modules as spares for a long time, the following precautions are necessary.

T650QVJ02.0 Product Specification

Rev 1.0

(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent light. Keep the

temperature between 5 and 35 at normal humidity.

(2) The polarizer surface should not come in contact with any other object. It is recommended that they

be stored in the container in which they were shipped.

℃ ℃

9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

(1) The protection film is attached to the bezel with a small masking tape. When the protection film is

peeled off, static electricity is generated between the film and polarizer. This should be peeled off

slowly and carefully by people who are electrically grounded and with well ion-blown equipment or

in such a condition, etc.

(2) When the module with protection film attached is stored for a long time, sometimes there remains a

very small amount of glue still on the bezel after the protection film is peeled off.

(3) You can remove the glue easily. When the glue remains on the bezel or its vestige is recognized,

please wipe them off with absorbent cotton waste or other soft material like chamois soaked with

normal-hexane.