AUO T650HVD02.0 Specification

T650HVD02.0 Product Specification

Rev.1 0

Model Name: T650HVD02.0

Issue Date : 2013/02/21

() Preliminary Specifications

(＊＊＊＊)Final Specifications

Customer Signature Date AUO Date

Approved By

_________________________________

Note

Approval By PM Director

CP Wang

____________________________________

Reviewed By RD Director

Eugene CC Chen

____________________________________

Reviewed By Project Leader

Jerry Jiang

____________________________________

Prepared By PM

Ale Tee

____________________________________

T650HVD02.0 Product Specification

Rev.1 0

Contents

No

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATION

3-1 ELECTRIACL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATION

3-4 SIGNAL TIMING WAVEFORM

3-5 COLOR INPUT DATA REFERENCE

3-6 POWER SEQUENCE

3-7 BACKLIGHT SPECIFICATION

4 OPTICAL SPECIFICATION

5 MECHANICAL CHARACTERISTICS

6 RELIABILITY TEST ITEMS

7 INTERNATIONAL STANDARD

7-1 SAFETY

7-2 EMC

8 PACKING

8-1 DEFINITION OF LABEL

8-2 PACKING METHODS

8-3 PALLET AND SHIPMENT INFORMATION

9 PRECAUTION

9-1 MOUNTING PRECAUTIONS

/9-2 OPERATING PRECAUTIONS

9-3 ELECTROSTATIC DISCHARGE CONTROL

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

9-5 STORAGE

9-6 HANDLING PRECAUTIONS FOR PROTECT FILM

Record of Revision

T650HVD02.0 Product Specification

Rev.1 0

Version

0.0 2012/10/12 First release

1.0 2012/2/1

2.0 2012/2/20

Date Page Description

5 Absolute Maximum Ratings

6 3.1.1 Update Inrush current

11 3.2 Modified Interface Connections

14 3.3 Modified Signal Timing Specification

22 4. Modified Optical Specification

27~30 5. Mechanical Characteristics

35 8.3. Pallet And Shipment Information

3.7 Backlight Specification (independent driver board): Inrush Current

18

T650HVD02.0 Product Specification

Rev.1 0

1. General Description

This specification applies to the 65.0 inch Color TFT-LCD Module T650HVD02.0. This LCD module has a TFT

active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 65.0 inch. This module supports

1,920x1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical

stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each

dot.

The T650HVD02.0 has been designed to apply the 10-bit 4 channel LVDS interface method. It is intended to

support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very

important. Also, 3D function is also embedded into front glass as pattern retarder.

* General Information

Items Specification Unit Note

Active Screen Size 65 inch

Display Area 1428.48 (H) x 803.52 (V) mm

Outline Dimension 1454.3(H) x 831.5(V) x 31.6(D) mm D: front bezel to T-con cover

Driver Element a-Si TFT active matrix

Bezel Opening 1434.5 (H) x 809.6 (V) mm

Display Colors 10 bit, 1.07B Colors

Number of Pixels 1,920x1,080 Pixel

Pixel Pitch 0.744 mm

Pixel Arrangement RGB vertical stripe

Display Operation Mode Normally Black

Rotate Function Unachievable Note 1

Display Orientation Signal input with “ABC” Note 2

Note 1: Rotate Function refers to LCD display could be able to rotate.

Note 2: LCD display as below illustrated when signal input with “ABC”.

T650HVD02.0 Product Specification

2. Absolute Maximum Ratings

The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit

Item Symbol Min Max Unit Conditions

Logic/LCD Drive Voltage Vcc -0.3 14 VDC Note 1

Input Voltage of Signal Vin -0.3 4 VDC Note 1

BLU Input Voltage VDDB -0.3 28 VDC Note 1

Rev.1 0

BLU on/off Control Voltage V

BLU Brightness Control Voltage Vdim -0.3 7 VDC Note 1

Operating Temperature TOP 0 +50 [oC] Note 2

Operating Humidity HOP 10 90 [%RH] Note 2

Storage Temperature TST -20 +60 [oC] Note 2

Storage Humidity HST 10 90 [%RH] Note 2

Panel Surface Temperature PST 65 [oC] Note 3

Note 1: Duration:50 msec.

Note 2 : Maximum Wet-Bulb should be 39 and No condensation.℃

The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures

greater than 40 , the wet bulb temperature must not exceed 39 .

Note 3: Surface temperature is measured at 50℃ Dry condition

℃ ℃

-0.3 7 VDC Note 1

BLON

℃

T650HVD02.0 Product Specification

Rev.1 0

3. Electrical Specification

The T650HVD02.0 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT

array and liquid crystal. The other is to power Back Light Unit.

3.1 Electrical Characteristics

3.1.1: DC Characteristics

Parameter Symbol

Unit Note

Min. Typ. Max

LCD

Power Supply Input Voltage VDD 10.8 12 13.2 VDC

Power Supply Input Current IDD -- 1.6 2.8 A 1

Power Consumption PC -- 19.2 33.6 Watt 1

Value

Inrush Current I

Input Differential Voltage

LVDS

Interface

Differential Input High Threshold Voltage

Differential Input Low Threshold Voltage

Input Common Mode Voltage V

DIM_IN

DCR

Interface

-- -- 10 A 2

RUSH

∣

V

∣

ID

200 400 600 mVDC 3

VTH +100 -- +300 mVDC 3

VTL -300 -- -100 mVDC 3

1.1 1.25 1.4 VDC 3

ICM

F

110 -- 240 Hz 4

DIM_IN

D

5 -- 100 % 4

DIM_IN

F

-- 180 -- Hz 4

DIM_OUT

D

DIM_OUT

VIH

(High)

VIL

(Low)

CMOS

Interface

Input High Threshold Voltage

Input Low Threshold Voltage

Backlight Power Consumption PBL 142.5

5 -- 100 % 4

2.7 -- 3.3 VDC 5

0 -- 0.6 VDC 5

157 Watt

Life time (MTTF) 30000

Hour 9,10

s

µ

3.1.2: AC Characteristics

T650HVD02.0 Product Specification

Rev.1 0

Parameter Symbol

Input Channel Pair Skew Margin t

Receiver Clock : Spread Spectrum

LVDS Interface

Modulation range

Receiver Clock : Spread Spectrum Modulation frequency

Receiver Data Input Margin Fclk = 85 MHz Fclk = 65 MHz

Note :

1. Test Condition:

(1) V

= 12.0V

DD

(2) Fv = Type Timing, 120Hz (3) Fclk= Max freq. (4) Temperature = 25 ℃ (5) Typ. Input current : White Pattern

Max. Input current: Heavy loading pattern defined by AUO

>> refer to “Section:3.3 Signal Timing Specification, Typical timing”

2. Measurement condition : Rising time = 400us

SKEW (CP)

Fclk_ss

Fss

tRMG

Value

Min. Typ. Max

-500 -- +500 ps 6

Fclk

-3%

30

-0.4

-0.5

--

Fclk

+3%

200

0.4

0.5

Unit Note

MHz

7

KHz

7

ns

8

GND

GNDGND

10%

3. Test Condition:

(1) The measure point of V

is in LCM side after connecting the System Board and LCM.

RP

(2) Under Max. Input current spec. condition.

4. V

= 1.25V

ICM

L V D S -

L V D S +

V

IC M

G N D

0 V

|VID|

400

400400

90%

VVVV

DD

DDDD

V

T H

|VID|

V

T L

|VID|

5. DCR Interface: Function Table

T650HVD02.0 Product Specification

Rev.1 0

Input Output

DCR_Enable

High PWM Input DCR Dimming Out

Low PWM Input PWM Input

NC NC Keep High

Note.(4-1) : During the deep duty control, partial darkness or center darkness might happen

due to insufficient LED current.

Note.(4-2): At low temperature, more warm up time may be needed.

6. The measure points of V

7. Input Channel Pair Skew Margin

and V

IH

DIM_IN DIM_OUT

are in LCM side after connecting the System Board and LCM.

IL

Note: x = 0, 1, 2, 3, 4

8. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures

1111////FFFF

SS

SSSS

Fclk

Fclk____ss

FclkFclk

ss((((max

ssss

Fclk

FclkFclk

Fclk

Fclk____ss

FclkFclk

ss((((min

ssss

max))))

maxmax

min))))

minmin

9. Receiver Data Input Margin

T650HVD02.0 Product Specification

Rev.1 0

Parameter Symbol

Min Type Max

Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz

Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns

Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns

Input Data Position2 tRIP6 2T/7-|tRMG|

Input Data Position3 tRIP5 3T/7-|tRMG|

Input Data Position4 tRIP4 4T/7-|tRMG|

Input Data Position5 tRIP3 5T/7-|tRMG|

Input Data Position6 tRIP2 6T/7-|tRMG|

Rating

Unit

2T/7 2T/7+|tRMG| ns

3T/7 3T/7+|tRMG| ns

4T/7 4T/7+|tRMG| ns

5T/7 5T/7+|tRMG| ns

6T/7 6T/7+|tRMG| ns

tRIP2

tRIP3

tRIP4

tRIP5

Note

T=1/Fclk

tRIP6

tRIP0

tRIP1 LVDS-Rx Input Data

Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Rx2Rx3

LVDS-Rx

VVVV

=

= 0000VVVV

= =

diff

Input Clock

diff diff

1/Fclk=T

10. The relative humidity must not exceed 80% non-condensing at temperatures of 40℃ or less. At

temperatures greater than 40℃, the wet bulb temperature must not exceed 39℃. When operate at low

temperatures, the brightness of LED will drop and the life time of LED will be reduced.

11. The lifetime (MTTF) is defined as the time which luminance of LED is 50% compared to its original value.

[Operating condition: Continuous operating at Ta = 25±2℃]

3.2 Interface Connections



LCD connector: FI-RE51S-HF ( Manufactured by JAE)

T650HVD02.0 Product Specification

Rev.1 0

1

2

3

4

5

6

7

8

9

10

11

12

Symbol Description PIN

3D Function Enable

3D_EN

NC AUO Internal Use Only 27

NC AUO Internal Use Only 28

NC AUO Internal Use Only 29

LVDS 8/10bit Input Selection

BITSEL

NC AUO Internal Use Only 31

LVDS_SEL

NC AUO Internal Use Only 33

NC AUO Internal Use Only 34

NC

GND Ground 36

CH1_0- LVDS Channel 1, Signal 0-

High(3.3V):3D

Open/Low(GND):2D

Open/Low(GND) : 8bits

High(3.3V) : 10bits

Open/High(3.3V) for NS,

Low(GND) for JEIDA

AUO Internal Use Only

Symbol Description

26

30

32

35

37

NC AUO Internal Use Only

CH2_0- LVDS Channel 2, Signal 0-

CH2_0+ LVDS Channel 2, Signal 0+

CH 2_1- LVDS Channel 2, Signal 1-

CH2_1+ LVDS Channel 2, Signal 1+

CH2_2- LVDS Channel 2, Signal 2-

CH2_2+ LVDS Channel 2, Signal 2+

GND Ground

CH2_CLK- LVDS Channel 2, Clock -

CH2_CLK+ LVDS Channel 2, Clock +

GND Ground

13

14

15

16

17

18

19

20

21

22

23

24

25

CH1_0+ LVDS Channel 1, Signal 0+

CH1_1- LVDS Channel 1, Signal 1-

CH1_1+ LVDS Channel 1, Signal 1+

CH1_2- LVDS Channel 1, Signal 2-

CH1_2+ LVDS Channel 1, Signal 2+

GND Ground

CH1_CLK- LVDS Channel 1, Clock -

CH1_CLK+ LVDS Channel 1, Clock +

GND Ground

CH1_3- LVDS Channel 1, Signal 3-

CH1_3+ LVDS Channel 1, Signal 3+

CH1_4- LVDS Channel 1, Signal 4-

CH1_4+ LVDS Channel 1, Signal 4+

51

38

39

40

41

42

43

44

45

46

47

48

49

50

CH2_3- LVDS Channel 2, Signal 3-

CH2_3+ LVDS Channel 2, Signal 3+

CH2_4- LVDS Channel 2, Signal 4-

CH2_4+ LVDS Channel 2, Signal 4+

NC AUO Internal Use Only

GND Ground

NC AUO Internal Use Only

V

DD

V

DD

V

DD

V

DD

Power Supply, +12V DC

Regulated

Power Supply, +12V DC

Regulated

Power Supply, +12V DC

Regulated

Power Supply, +12V DC

Regulated

T650HVD02.0 Product Specification



LCD connector: FI-RE41S-HF ( Manufactured by JAE)

PIN Symbol Description PIN Symbol Description

Rev.1 0

10

11

12

13

14

15

16

1

2

3

4

5

6

7

8

9

NC AUO Internal Use Only 21

NC AUO Internal Use Only 22

NC AUO Internal Use Only 23

NC AUO Internal Use Only 24

NC AUO Internal Use Only 25

NC AUO Internal Use Only 26

NC AUO Internal Use Only 27

NC AUO Internal Use Only 28

GND Ground 29

CH3_0-

CH3_0+

CH3_1-

CH3_1+

CH3_2-

CH3_2+

GND

LVDS Channel 3, Signal 0- 30

LVDS Channel 3, Signal 0+ 31

LVDS Channel 3, Signal 1- 32

LVDS Channel 3, Signal 1+ 33

LVDS Channel 3, Signal 2- 34

LVDS Channel 3, Signal 2+ 35

Ground 36

CH3_3+

CH3_4- LVDS Channel 3,Signal 4-

CH3_4+

GND

CH4_0-

CH4_0+

CH4_1-

CH4_1+

CH4_2-

CH4_2+

GND

CH4_CLK-

CH4_CLK+

GND

CH4_3-

LVDS Channel 3, Signal 3+

LVDS Channel 3,Signal 4+

Ground

LVDS Channel 4, Signal 0-

LVDS Channel 4, Signal 0+

LVDS Channel 4, Signal 1-

LVDS Channel 4, Signal 1+

LVDS Channel 4, Signal 2-

LVDS Channel 4, Signal 2+

Ground

LVDS Channel 4, Clock -

LVDS Channel 4, Clock +

Ground

LVDS Channel 4, Signal 3-

17

CH3_CLK+

18

19

20

CH3_CLK-

GND

CH3_3-

LVDS Channel 3, Clock - 37

LVDS Channel 3, Clock + 38

Ground 39

LVDS Channel 3, Signal 3- 40

41

CH4_3+

CH4_4- LVDS Channel 4,Signal 4-

CH4_4+

GND Ground

LVDS Channel 4, Signal 3+

LVDS Channel 4,Signal 4+

Note 1: All GND (ground) pins should be connected together and should also be connected to the LCD’s

metal frame.

Note 2: All VDD (power input) pins should be connected together.

Note 3: NC : please leave this pin unoccupied. It can not be connected by any signal (Low/GND/High).

Note 4: Open / High(3.3V) / Low(GND) described in 3.2.1

Note 5: 3D_EN timing described in 3.2.1

3.2.1: LVDS connector control pin description

T650HVD02.0 Product Specification

Rev.1 0

Note * : Open/High(3.3V)

Note *** : Open/Low(GND)

3D_EN control signal can only “pull high” in the middle of vertical blanking area (Tblk(V))

Note ** : Open/Low(GND)

LVDS Option = High/OpenNS

P re v i o u s C y c le C u r r e n t C y cle N e x t C y c l e

P re v i o u s C y c le C u r r e n t C y cle N e x t C y c l e P re v i o u s C y c le C u r r e n t C y cle N e x t C y c l e

C lo c k

C lo c kC lo c k

C H x

C H x ____ 0000 ++++

C H xC H x C H x

C H x ____ 0000 ----

C H xC H x

C H x

C H x ____ 1111 ++++

C H xC H x C H x

C H x ____ 1111 ----

C H xC H x

C H x

C H x ____ 2222 ++++

C H xC H x C H x

C H x ____ 2222 ----

C H xC H x

D EBBBB 2222BBBB 3333 BBBB 4444BBBB 5555N A

D ED E

T650HVD02.0 Product Specification

RRRR 0000RRRR 5555 GGGG 0000GGGG 0000RRRR 0000RRRR 1111 RRRR 2222RRRR 3333RRRR 4444 RRRR 1111

GGGG 1111BBBB 0000 BBBB 1111BBBB 1111GGGG 1111GGGG 2222 GGGG 3333GGGG 4444GGGG 5555 GGGG 2222

N A D E

N AN A

N A BBBB 3333

N AN A

BBBB 2222N A

D ED E

Rev.1 0

C H x

C H x ____ 3333 ++++

C H xC H x C H x

C H x ____ 3333 ----

C H xC H x

C H x

C H x ____ 4444 ++++

C H xC H x C H x

C H x ____ 4444 ----

C H xC H x

Note: x = 1, 2, 3, 4…

LVDS Option = LowJEIDA

P r e v io u s C y c l e C u r r e n t C y c le N e x t C y c le

P r e v io u s C y c l e C u r r e n t C y c le N e x t C y c le P r e v io u s C y c le C u rr e n t C y c l e N e x t C y c le

C l o c k

C l o c kC l o c k

C H x

C H x ____ 0000 ++++

C H xC H x

C H x

C H x ____ 0000 ----

C H xC H x

C H x

C H x ____ 1111 ++++

C H xC H x

C H x

C H x ____ 1111 ----

C H xC H x

N ARRRR 6666RRRR 7777 GGGG 6666GGGG 7777BBBB 6666 RRRR 7777

N AN A

N ARRRR 8888RRRR 9999 GGGG 8888GGGG 9999BBBB 8888 RRRR 9999

N AN A

RRRR 6666BBBB 7777 N A

RRRR 8888BBBB 9999 N A

RRRR 4444RRRR 9999 GGGG 4444GGGG 4444RRRR 4444RRRR 5555 RRRR 6666RRRR 7777RRRR 8888 RRRR 5555

GGGG 5555BBBB 4444 BBBB 5555BBBB 5555GGGG 5555GGGG 6666 GGGG 7777GGGG 8888GGGG 9999 GGGG 6666

N AN A

C H x

C H x ____ 2222 ++++

C H xC H x

C H x

C H x ____ 2222 ----

C H xC H x

C H x

C H x ____ 3333 ++++

C H xC H x

C H x

C H x ____ 3333 ----

C H xC H x

C H x

C H x ____ 4444 ++++

C H xC H x

C H x

C H x ____ 4444 ----

C H xC H x

D EBBBB 6666BBBB 7777 BBBB 8888BBBB 9999N A

D ED E

N ARRRR 2222RRRR 3333 GGGG 2222GGGG 3333BBBB 2222 RRRR 3333

N AN A

N ARRRR 0000RRRR 1111 GGGG 0000GGGG 1111BBBB 0000 RRRR 1111

N AN A

N A D E

N AN A

N A BBBB 7777

N AN A

BBBB 6666N A

RRRR 2222BBBB 3333 N A

RRRR 0000BBBB 1111 N A

D ED E

N AN A

Note: x = 1, 2, 3, 4…

T650HVD02.0 Product Specification

Rev.1 0

3.3 Signal Timing Specification

This is the signal timing required at the input of the user connector. All of the interface signal timing should be

satisfied with the following specifications for its proper operation.

Timing Table (DE only Mode)

Signal Item Symbol Min. Typ. Max Unit

Period Tv 1100

Vertical Section

Horizontal Section

Clock Frequency Fclk=1/Tclk 64.8

Vertical Frequency Frequency Fv 94

Horizontal Frequency Frequency Fh 120

Notes:

(1) Display position is specific by the rise of DE signal only.

Horizontal display position is specified by the rising edge of 1st DCLK after the rise of 1st DE, is displayed on the

left edge of the screen.

(2)Vertical display position is specified by the rise of DE after a “Low” level period equivalent to eight times of

horizontal period. The 1st data corresponding to one horizontal line after the rise of 1st DE is displayed at the top

Active Tdisp (v) 1080 Th

Blanking Tblk (v) 20

Period Th 520

Active Tdisp (h) 480 Tclk

Blanking Tblk (h) 40

1130

50

570

90

77.29

120

135.6

1392

312

580

100

80.74

122

139.2

Th

Tclk

MHz

Hz

KHz

line of screen.

(3)If a period of DE “High” is less than 1920 DCLK or less than 1080 lines, the rest of the screen displays black.

(4)The display position does not fit to the screen if a period of DE “High” and the effective data period do not

synchronize with each other.

(5) Under 3D mode, signal should be input as following sequence: 1st line: right eye, 2nd line: left eye (when rotate

function is not implemented and T-con position is at panel upper side).

3.4 Signal Timing Waveforms

T650HVD02.0 Product Specification

Rev.1 0

CH4

M-12

Pixel

M-8

Pixel

M-4

Pixel

M

Invalid Data

Pixel

4

Pixel

8

Pixel

12

Pixel

16

Pixel

20

Pixel

24

CH3

M-13

Pixel

M-9

Pixel

M-5

Pixel

M-1

Invalid Data

Pixel

3

Pixel

7

Pixel

11

Pixel

15

Pixel

19

Pixel

23

CH2

M-14

Pixel

M-10

Pixel

M-6

Pixel

M-2

Invalid Data

Pixel

2

Pixel

6

Pixel

10

Pixel

14

Pixel

18

Pixel

22

CH1

M-15

Pixel

M-11

Pixel

M-7

Pixel

M-3

Invalid Data

Pixel

1

Pixel

5

Pixel

9

Pixel

13

Pixel

17

Pixel

21

DE

Tdisp(h) Tblk(h)

CLK

RGB

Data

Line

N

Tclk

Invalid Data Invalid Data

Line

1

Line

2

Th

Line

3

Line

4

DE

Th

Tv

Tdisp(v)Tblk(v)

M-10

Pixel

M-8

Pixel

M-4

Pixel

M

Invalid Data

Pixel

4

Pixel

8

Pixel

M-9

Pixel

M-5

Pixel

M-1

Invalid Data

Pixel

3

Pixel

7

Pixel

M-6

Pixel

M-2

Invalid Data

Pixel

2

Pixel

6

M-11

Pixel

M-7

Pixel

M-3

Invalid Data

Pixel

1

Pixel

5

Line

N

N L in e

N L in eN L in e

M

M p

p

p i

i

x

x e

e

e l

l

Basic

T650HVD02.0 Product Specification

Rev.1 0

3.5 Color Input Data Reference

The brightness of each primary color (red, green and blue) is based on the 10 bit gray scale data input for the color;

the higher the binary input, the brighter the color. The table below provides a reference for color versus data input.

COLOR DATA REFERENCE

Input Color Data

Color

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

Blue(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Color

Cyan 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Magenta 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RED(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(001) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R

----

RED(1022) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

RED

MSB LSB

GREEN

BLUE

MSB LSB

GREEN(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GREEN(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

G

----

GREEN(1022) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

GREEN(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

BLUE(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

B

----

BLUE(1022) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0

BLUE(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Power Sequence for LCD

T650HVD02.0 Product Specification

Rev.1 0

Pow er S u p p ly F or LC D

Pow er S u p p ly F or LC D Pow er S u p p ly F or LC D VD D

VD D (+

(+ 12

(+(+

12 VVVV ))))

121 2

G ND

VD D VDD

In ter face Sig n a l

In ter face Sig n a lIn ter face Sig n a l ((((LV DS D a ta

LV DS D a ta &

LV DS D a ta L V DS D a ta

& C LK

CLK ))))

& &

CLKCLK

G ND

Back lig h t o n

Back lig h t o n ////o ff

Back lig h t o nB a c klight on co n tro l s ig na l

co n tro l s ig na l

co n tro l s ig na lco n tro l s ig na l ((((VBLO N

VBLO N ))))

VBLO NVBLO N

off

offoff

GN D

CM O S In terf ace S ignal

CM O S In terf ace S ignalCM O S In terf ace S ignal

G ND

Parameter

t1 0.4 --- 30 ms

10 %

90 %

t1

t2

Valid D ata

Valid D ataV alid Da ta

t3 t4

t8 t9

Values

Min. Type. Max.

90 %

10 %

t6

t5

10 %

t7

Unit

t2 0.1 --- 50 ms

t3 670 --- --- ms

t4 0*1 --- --- ms

t5 0 --- --- ms

t6 --- --- ---*2 ms

t7 500 --- --- ms t8

10*3

--- 50 ms

t9 0 --- --- ms

Note: (1) t4=0 : concern for residual pattern before BLU turn off. (2) t6 : voltage of VDD must decay smoothly after power-off. (customer system decide this value) (3) When CMOS Interface signal is N.C. (no connection), opened in Transmitted end, t8 timing spec can be

negligible.

3.7 Backlight Specification (independent driver board)

The backlight unit contains 4pcs light bar.

3.7.1 Electrical specification

Item Symbol Condition

T650HVD02.0 Product Specification

Rev.1 0

Spec

Unit Note

Min Typ Max

1

2

3

4

5 Control signal voltage

6 Control signal current

7

8

9

10

Note 1: Dimming ratio= 100%,（Ta=25±5℃, Turn on for 45minutes）

Input Voltage VDDB - 22.8

Input Current I

Input Power P

Inrush Current I

V

Signal

External PWM Duty ratio

(input duty ratio)

External PWM

Frequency

DET status signal DET

Input Impedance Rin VDDB=24V 300 Kohm -

D_EPWM VDDB=24V

F_EPWM VDDB=24V 110 180 240 Hz 4,5

VDDB=24V

DDB

VDDB=24V

DDB

VDDB=24V

RUSH

Hi 2 - 5.5 -

Low

I

VDDB=24V

Signal

HI Open Collector VDC 6

Lo

VDDB=24V

24 25.2

5.94 6.54

142.5 157 W 1

0 - 0.8

- - 1.5 mA -

0 - 100 % 4,5

0 - 0.8 VDC 6

14.7

VDC -

ADC 1

Apeak 2

VDC

3

Note 2: MAX input current at all operating mode, measurement condition Rising time = 20ms (VDDB: 10%~90%)

Note 3: When BLU off ( VDDB = 24V , VBLON = 0V) , IDDB (max) = 0.1A

Note 4: Less than 5% dimming control is functional well and no backlight shutdown happened

Note 5: D_EPWM and F_EPWM are available only at 2D mode

Note 6: Normal: 0~0.8V ; Abnormal : Open collector

3.7.2 Input Pin Assignment

LED driver board connector : CI0114M1HR0-NH (Cvilux) or equivalent

Pin Symbol Description

1 VDDB Operating Voltage Supply, +24V DC regulated

2 VDDB Operating Voltage Supply, +24V DC regulated

3 VDDB Operating Voltage Supply, +24V DC regulated

4 VDDB Operating Voltage Supply, +24V DC regulated

5 VDDB Operating Voltage Supply, +24V DC regulated

6 BLGND Ground and Current Return

7 BLGND Ground and Current Return

8 BLGND Ground and Current Return

9 BLGND Ground and Current Return

T650HVD02.0 Product Specification

Rev.1 0

10 BLGND Ground and Current Return

BLU status detection:

11

12 VBLON

13

14

DET

NC NC

PDIM(*) External PWM (0%~100% Duty, open for 100%)

Normal : 0~0.8V ; Abnormal : Open collector

(Recommend Pull high R > 10K, VDD = 3.3V)

BLU On-Off control:

High/Open (2~5.5V) : BL On ;

Low (0~0.8V/GND) : BL Off

12pin pin assignment

LED driver board Connector: CI0112M1HR0-NH (CviLux) or equivalent

T650HVD02.0 Product Specification

Rev.1 0

1 VDDB Operating Voltage Supply, +24V DC regulated

2

3

4

5

6

7

8

9

10

11

12

(Note*) PWM Dimming range:

Symbol Description

VDDB Operating Voltage Supply, +24V DC regulated

BLGND Ground and Current Return

NC NC

(Note*) IF External PWM function less than 5% dimming ratio, Judge condition as below: (1)Backlight module must be lighted ON normally. (2)All protection function must work normally. (3)Uniformity and flicker could not be guaranteed

3.7.6.3 Power Sequence for Backlight (LED)

24V(typ.)

T3

Power Input for BLU

(VDDB)

Valid Dimming

Control Signal

(V_IPWM,V_EPWM)

90% 90%

10%

T1 T2

T650HVD02.0 Product Specification

10%

T7

T6

T5

T4

Rev.1 0

BLU On/Off Enable

(VBLON)

Dip condition

Power Input for BLU

Parameter

(VDDB)

VDDB(typ.)*0.8

Value

Min Typ Max

T1 20 - - ms *1

T2 500 - -

T3 250 - -

T4 0 - -

T8

Units

ms

T5 1 - -

T6 0 - -

T7 500 - -

T8 - - 10

ms

T650HVD02.0 Product Specification

Rev.1 0

4. Optical Specification

Optical characteristics are determined after the unit has been ‘ON’ and stable for approximately 45 minutes in a

dark environment at 25°C. The values specified are at an approximate distance 50cm from the LCD surface at a

viewing angle of φ and θ equal to 0°.

Fig.1 presents additional information concerning the measurement equipment and method.

SR3 or equivalent

Parameter Symbol

Min. Typ. Max

Contrast Ratio CR 3200 4000 -- 1

L

(2D) 280 350 -- cd/m2 2

Surface Luminance (White)

Luminance Variation δ

Response Time (G to G) Tγ -- 6.5 -- ms 4

Color Gamut NTSC 72 %

Color Coordinates

Red RX 0.640

RY 0.330

Green GX 0.300

GY 0.620

Blue BX 0.150

BY 0.050

White WX 0.280

WH

L

(3D) 80 100 6

WH

WHITE(9P)

-- -- 1.33 3

Typ.-0.03

Values

Unit Notes

Typ.+0.03

WY

Viewing Angle 5

x axis, right(φ=0°) θr -- 89 -- degree

2D

3D

3D cross talk (middle)

x axis, left(φ=180°) θl -- 89 -- degree

y axis, up(φ=90°) θu -- 89 -- degree

y axis, down (φ=270°) θd -- 89 -- degree

y axis, up θu 10 -- degree

y axis, down θd 10

-- 1

0.290

20

6

--

3 % 6

2 3

7

T650HVD02.0 Product Specification

Rev.1 0

Note:

1. Contrast Ratio (CR) is defined mathematically as:

Surface Luminance of

Contrast Ratio=

Surface Luminance of

2. Surface luminance is luminance value at point 5 across the LCD surface 50cm from the surface with all pixels

displaying white. From more information see FIG 2. When LED current IF = typical value (without driver board),

L

on5

off5

LED input VDDB =24V, I

. = Typical value (with driver board), LWH=Lon5 where Lon5 is the luminance with all

DDB

pixels displaying white at center 5 location.

FIG. 2 Luminance

V

H/2

H/9

1

H

V/2 V/9

3. The variation in surface luminance, δWHITE is defined (center of Screen) as:

δ

WHITE(9P)

4. Response time Tγ is the average time required for display transition by switching the input signal for five

= Maximum(L

on1

, L

on2

,…,L

)/ Minimum(L

on9

on1

, L

on2

,…L

on9

)

luminance ratio (0%,25%,50%,75%,100% brightness matrix) and is based on Fv=120Hz to optimize.

Target Measured

Response Time

0%

25%

Start

50%

75%

100%

Tγ is determined by 10% to 90% brightness difference of rising or falling period. (As illustrated)

The response time is defined as the following figure and shall be measured by switching the input signal for “any level of grey(bright) “ and “any level of gray(dark)”.

0% 25% 50% 75% 100%

0% to 25% 0% to 50% 0% to 75% 0% to 100%

25% to 0% 25% to 50% 25% to 75% 25% to 100%

50% to 0% 50% to 25%

75% to 0% 75% to 25% 75% to 50%

100% to 0% 100% to 25% 100% to 50% 100% to 75%

50% to 75% 50% to 100%

75% to 100%

T650HVD02.0 Product Specification

Any level of gray (Bright) Any level of gray (Dark) Any level of gray (Bright)

Rev.1 0

0% , 25%, 50% , 75%, 100%

100%

90%

0% , 25%, 50% , 75%, 10 0%

Photodetector

Output

10%

0% , 25%, 50% , 75%, 100%

Tim e

T

(F)

γγγγ

5. Viewing angle is the angle at which the contrast ratio is greater than 10. The angles are determined for the

horizontal or x axis and the vertical or y axis with respect to the z axis which is normal to the LCD surface. For

more information see FIG3.

T

γγγγ

(R)

FIG.3 Viewing Angle

6. 3D performance specification is expressed by 3D luminance, 3D Crosstalk and 3D viewing angle. 3D

luminance which is defined by summation of left and right eye brightness under wearing glasses condition is

measured at panel center point. Also, 3D crosstalk is measured at panel center point.

a. Cross talk (middle) is defined by observation position which is 2.4m distance from panel center point and

human head in 0 degree steady vertical angle from panel mid axis level.

b. Cross talk (in vertical viewing angle) is defined by observation position which is 2.4m distance from panel

center point and observation range within specified degrees of vertical angle from panel mid axis level, and the

value is limited by 10%.

For more information, refer to 6-5 3D Measurement of 3D view angle.

2

6-1 Notation of measurement.

T650HVD02.0 Product Specification

Rev.1 0

Glasses type:

R: right eyeglass

L: left eyeglass

C: without

RL (W,K)

Left eye gray level

6-2 Measurement Configuration

4-test patterns (first character refers to Left eye gray level; second one refers to Right eye gray level).

W is defined as brightness gray level; K is defined as dark state where black and white lines are displayed

on even or odd lines.

Measurement Code:

L: Luminance

Right eye gray level

Odd line

Even line

6-3 Measurement of 3D luminance

a. Test pattern WW is displayed, measuring distance is 50cm.

b. Left or right eyeglass are placed in front of SR3 or equivalent equipment (as FIG1 showed)

successively and luminance is measured at panel center point where the notation for luminance

measurement is RL(W,W) and LL(W,W).

),(),(

3

LumD

=

+

WWLWWR

LL

6-4 Measurement of 3D Crosstalk

a. Test patterns KW, WK and KK are displayed, measuring distance is 2.4m.

b. Right or left eyeglass is placed in front of SR3 or equivalent equipment (as FIG1 showed) successively

2

−

T650HVD02.0 Product Specification

Rev.1 0

and luminance is measured at panel center point

),(),(

KKRKWR

Crosstalk

=

R

=

L

LL

−

LL

−

LL

),(),(

KKRWKR

),(),(

KKLWKL

),(),(

KKLKWL

%100

×

%100

×

6-5 Measurement of 3D view angle

The angles are determined for the vertical or y axis with respect to the z axis which is normal to the LCD

module surface and measured at panel center position.

Crosstalk+=

CrosstalkCrosstalk

LR

T650HVD02.0 Product Specification

Rev.1 0

5. Mechanical Characteristics

The contents provide general mechanical characteristics for the model T650HVD02.0. In addition the figures in the

next page are detailed mechanical drawing of the LCD.

Item Dimension Unit Note

Horizontal 1454.3 mm

Vertical 831.5 mm

Outline Dimension

Depth (Dmin) 12.8 mm to rear

Depth (Dmax) 30.1 mm to inverter cover

Weight 25,000 g

Front View

T650HVD02.0 Product Specification

Rev.1 0

Back View

T650HVD02.0 Product Specification

Rev.1 0

Back View

T650HVD02.0 Product Specification

Rev.1 0

6. Reliability Test Items

T650HVD02.0 Product Specification

Rev.1 0

1 High temperature storage test 3 60℃, 300hrs

2 Low temperature storage test 3 -20℃, 300hrs

3 High temperature operation test 3 50℃, 300hrs

4 Low temperature operation test 3 -5℃, 300hrs

5 Vibration test (With carton) 1( PKG)

6 Drop test (With carton) 1(PKG)

Test Item Q’ty Condition

Random wave (1.05Grms 10~200Hz)

Duration : X,Y,Z 10min per axes

Height: 25.4 cm

Direction: Only bottom flat twice

(ASTMD4169-I)

7. International Standard

7.1 Safety

(1) UL 60950-1, UL 60065; Standard for Safety of Information Technology Equipment Including

electrical Business Equipment.

(2) IEC 60950-1 : 2001, IEC 60065:2001 ; Standard for Safety of International Electrotechnical

Commission

(3) EN 60950 : 2001+A11, EN 60065:2002+A1:2006; European Committee for Electrotechnical

Standardization (CENELEC), EUROPEAN STANDARD for Safety of Information Technology

Equipment Including Electrical Business Equipment.

7.2 EMC

(1) ANSI C63.4 “Methods of Measurement of Radio-Noise Emissions from Low-Voltage Electrical and

Electrical Equipment in the Range of 9kHz to 40GHz. “American National standards Institute(ANSI),

T650HVD02.0 Product Specification

Rev.1 0

1992

(2) C.I.S.P.R “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” International Special committee on Radio Interference.

(3) EN 55022 “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” European Committee for Electrotechnical Standardization. (CENELEC),

1998

QTY :

5

Manufactured

XX/XX

MADE IN

XXXXX

8. Packing

8-1 DEFINITION OF LABEL:

A. Panel Label:

*xxxxxxxxxxxx-xxxx*

T650HVD02.0 Product Specification

Rev.1 0

Panel Unique ID

XXXXX Model NO: T650HVD02.0 XXXXXXX

Green mark description

Year

AUO Internal Use

AU Optronics

Week Factory Location AUO Internal Use

AUO Internal Use

(1) For Pb Free Product, AUO will add for identification.

(2) For RoHs compatible products, AUO will add RoHS for identification.

Note: The green Mark will be present only when the green documents have been ready by AUO internal green

team. (definition of green design follows the AUO green design checklist.)

B. Carton Label:

T650HVD02.XXX

97.65T11.XXX

1pcs Module/ESD Bag

1pcs Module/ESD Bag1pcs Module/ESD Bag

1pcs Module/ESD Bag

Cushion top

Cushion topCushion top

Cushion top

Module

5 pcs / 1 ca

5 pcs / 1 ca5 pcs / 1 ca

5 pcs / 1 ca

rton

rtonrton

rton

”

H ”

Cushion down

Cushion downCushion down

Cushion down

Cushion set

Cushion setCushion set

Cushion set

8-2 PACKING METHODS:

T650HVD02.0 Product Specification

Rev.1 0

8-3 Pallet and Shipment Information

T650HVD02.0 Product Specification

Rev.1 0

Specification

Item

1 Packing Box 5 pcs/box 1565(L)mm*380(W)mm*978(H)mm 140

2 Pallet 1 1660(L)mm*1150(W)mm*144(H)mm 20

3 Boxes per Pallet 3 boxes/Pallet (By Air) ; 3 Boxes/Pallet (By Sea)

4 Panels per Pallet 15 pcs/pallet(By Air) ; 15 pcs/Pallet (By Sea)

after packing

Qty. Dimension Weight (kg)

15 (by Air) 1660(L)mm*1150(W)mm*1122(H)mm 440(by Air)

30 (by Sea) 1660(L)mm*1150(W)mm*2244(H)mm 880(by Sea) 40ft HQ

Corner angle

Moisture-proof film

Stretch film

Packing

Remark

5 Pallet

Label

PET band

Corner angle

Pallet

9. PRECAUTIONS

Please pay attention to the followings when you use this TFT LCD module.

9-1 MOUNTING PRECAUTIONS

(1) You must mount a module using holes arranged in four corners or four sides.

(2) You should consider the mounting structure so that uneven force (ex. twisted stress) is not applied

to module. And the case on which a module is mounted should have sufficient strength so that

external force is not transmitted directly to the module.

(3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer.

Transparent protective plate should have sufficient strength in order to the resist external force.

(4) You should adopt radiation structure to satisfy the temperature specification.

(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former

T650HVD02.0 Product Specification

Rev.1 0

generates corrosive gas of attacking the polarizer at high temperature and the latter cause circuit

broken by electro-chemical reaction.

(6) Do not touch, push or rub the exposed polarizer with glass, tweezers or anything harder than HB

pencil lead. And please do not rub with dust clothes with chemical treatment. Do not touch the

surface of polarizer for bare hand or greasy cloth. (Some cosmetics are detrimental to the polarizer.)

(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials

like chamois soaks with petroleum benzene. Normal-hexane is recommended for cleaning the

adhesives used to attach front/ rear polarizer. Do not use acetone, toluene and alcohol because

they cause chemical damage to the polarizer.

(8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes

deformations and color fading.

(9) Do not open the case because inside circuits do not have sufficient strength.

9-2 OPERATING PRECAUTIONS

(1) The device listed in the product specification sheets was designed and manufactured for TV

application

(2) The spike noise causes the mis-operation of circuits. It should be lower than following voltage:

V=±200mV(Over and under shoot voltage)

(3) Response time depends on the temperature. (In lower temperature, it becomes longer..)

(4) Brightness of CCFL depends on the temperature. (In lower temperature, it becomes lower.) And in

lower temperature, response time (required time that brightness is stable after turned on) becomes

longer.

(5) Be careful for condensation at sudden temperature change. Condensation makes damage to

polarizer or electrical contacted parts. And after fading condensation, smear or spot will occur.

(6) When fixed patterns are displayed for a long time, remnant image is likely to occur.

(7) Module has high frequency circuits. Sufficient suppression to the electromagnetic interference shall

be done by system manufacturers. Grounding and shielding methods may be important to minimize

the interface.

9-3 ELECTROSTATIC DISCHARGE CONTROL

Since a module is composed of electronic circuits, it is not strong to electrostatic discharge. Make certain

that treatment persons are connected to ground through wristband etc. And don’t touch interface pin

directly.

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

Strong light exposure causes degradation of polarizer and color filter.

9-5 STORAGE

When storing modules as spares for a long time, the following precautions are necessary.

(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent light. Keep the

T650HVD02.0 Product Specification

Rev.1 0

temperature between 5 and 35 at normal humidity.

(2) The polarizer surface should not come in contact with any other object. It is recommended that they

be stored in the container in which they were shipped.

℃ ℃

9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

(1) The protection film is attached to the bezel with a small masking tape. When the protection film is

peeled off, static electricity is generated between the film and polarizer. This should be peeled off

slowly and carefully by people who are electrically grounded and with well ion-blown equipment or

in such a condition, etc.

(2) When the module with protection film attached is stored for a long time, sometimes there remains a

very small amount of glue still on the bezel after the protection film is peeled off.

(3) You can remove the glue easily. When the glue remains on the bezel or its vestige is recognized,

please wipe them off with absorbent cotton waste or other soft material like chamois soaked with

normal-hexane.

AUO T650HVD02.0 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual