T650HVD02.0 Product Specification
Rev.1 0
Model Name: T650HVD02.0
Issue Date : 2013/02/21
() Preliminary Specifications
(＊＊＊＊)Final Specifications
Customer Signature Date AUO Date
Approved By
_________________________________
Note
Approval By PM Director
CP Wang
____________________________________
Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
Jerry Jiang
____________________________________
Prepared By PM
Ale Tee
____________________________________
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 1 / 37
T650HVD02.0 Product Specification
Rev.1 0
Contents
No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORM
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT SPECIFICATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
7-1 SAFETY
7-2 EMC
8 PACKING
8-1 DEFINITION OF LABEL
8-2 PACKING METHODS
8-3 PALLET AND SHIPMENT INFORMATION
9 PRECAUTION
9-1 MOUNTING PRECAUTIONS
/9-2 OPERATING PRECAUTIONS
9-3 ELECTROSTATIC DISCHARGE CONTROL
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5 STORAGE
9-6 HANDLING PRECAUTIONS FOR PROTECT FILM
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 2 / 37
Record of Revision
T650HVD02.0 Product Specification
Rev.1 0
Version
0.0 2012/10/12 First release
1.0 2012/2/1
2.0 2012/2/20
Date Page Description
5 Absolute Maximum Ratings
6 3.1.1 Update Inrush current
11 3.2 Modified Interface Connections
14 3.3 Modified Signal Timing Specification
22 4. Modified Optical Specification
27~30 5. Mechanical Characteristics
35 8.3. Pallet And Shipment Information
3.7 Backlight Specification (independent driver board): Inrush Current
18
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 3 / 37
T650HVD02.0 Product Specification
Rev.1 0
1. General Description
This specification applies to the 65.0 inch Color TFT-LCD Module T650HVD02.0. This LCD module has a TFT
active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 65.0 inch. This module supports
1,920x1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical
stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each
dot.
The T650HVD02.0 has been designed to apply the 10-bit 4 channel LVDS interface method. It is intended to
support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very
important. Also, 3D function is also embedded into front glass as pattern retarder.
* General Information
Items Specification Unit Note
Active Screen Size 65 inch
Display Area 1428.48 (H) x 803.52 (V) mm
Outline Dimension 1454.3(H) x 831.5(V) x 31.6(D) mm D: front bezel to T-con cover
Driver Element a-Si TFT active matrix
Bezel Opening 1434.5 (H) x 809.6 (V) mm
Display Colors 10 bit, 1.07B Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.744 mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Rotate Function Unachievable Note 1
Display Orientation Signal input with “ABC” Note 2
Note 1: Rotate Function refers to LCD display could be able to rotate.
Note 2: LCD display as below illustrated when signal input with “ABC”.
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 4 / 37
T650HVD02.0 Product Specification
2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 VDC Note 1
Input Voltage of Signal Vin -0.3 4 VDC Note 1
BLU Input Voltage VDDB -0.3 28 VDC Note 1
Rev.1 0
BLU on/off Control Voltage V
BLU Brightness Control Voltage Vdim -0.3 7 VDC Note 1
Operating Temperature TOP 0 +50 [oC] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
Storage Temperature TST -20 +60 [oC] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
Panel Surface Temperature PST 65 [oC] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.℃
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures
greater than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50℃ Dry condition
℃ ℃
-0.3 7 VDC Note 1
BLON
℃
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 5 / 37
T650HVD02.0 Product Specification
Rev.1 0
3. Electrical Specification
The T650HVD02.0 requires two power inputs. One is employed to power the LCD electronics and to drive the TFT
array and liquid crystal. The other is to power Back Light Unit.
3.1 Electrical Characteristics
3.1.1: DC Characteristics
Parameter Symbol
Unit Note
Min. Typ. Max
LCD
Power Supply Input Voltage VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD -- 1.6 2.8 A 1
Power Consumption PC -- 19.2 33.6 Watt 1
Value
Inrush Current I
Input Differential Voltage
LVDS
Interface
Differential Input High Threshold Voltage
Differential Input Low Threshold Voltage
Input Common Mode Voltage V
DIM_IN
DCR
Interface
-- -- 10 A 2
RUSH
∣
V
∣
ID
200 400 600 mVDC 3
VTH +100 -- +300 mVDC 3
VTL -300 -- -100 mVDC 3
1.1 1.25 1.4 VDC 3
ICM
F
110 -- 240 Hz 4
DIM_IN
D
5 -- 100 % 4
DIM_IN
F
-- 180 -- Hz 4
DIM_OUT
DIM_OUT
D
DIM_OUT
VIH
(High)
VIL
(Low)
CMOS
Interface
Input High Threshold Voltage
Input Low Threshold Voltage
Backlight Power Consumption PBL 142.5
5 -- 100 % 4
2.7 -- 3.3 VDC 5
0 -- 0.6 VDC 5
157 Watt
Life time (MTTF) 30000
Hour 9,10
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 6 / 37
s
µ
3.1.2: AC Characteristics
T650HVD02.0 Product Specification
Rev.1 0
Parameter Symbol
Input Channel Pair Skew Margin t
Receiver Clock : Spread Spectrum
LVDS
Interface
Modulation range
Receiver Clock : Spread Spectrum
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz
Fclk = 65 MHz
Note :
1. Test Condition:
(1) V
= 12.0V
DD
(2) Fv = Type Timing, 120Hz
(3) Fclk= Max freq.
(4) Temperature = 25 ℃
(5) Typ. Input current : White Pattern
Max. Input current: Heavy loading pattern defined by AUO
>> refer to “Section:3.3 Signal Timing Specification, Typical timing”
2. Measurement condition : Rising time = 400us
SKEW (CP)
Fclk_ss
Fss
tRMG
Value
Min. Typ. Max
-500 -- +500 ps 6
Fclk
-3%
30
-0.4
-0.5
--
--
--
--
Fclk
+3%
200
0.4
0.5
Unit Note
MHz
7
KHz
7
ns
8
GND
GND
GNDGND
10%
3. Test Condition:
(1) The measure point of V
is in LCM side after connecting the System Board and LCM.
RP
(2) Under Max. Input current spec. condition.
4. V
= 1.25V
ICM
L V D S -
L V D S +
V
IC M
G N D
0 V
|VID|
400
400
400400
90%
VVVV
DD
DD
DDDD
V
T H
|VID|
V
T L
|VID|
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 7 / 37
5. DCR Interface: Function Table
T650HVD02.0 Product Specification
Rev.1 0
Input Output
DCR_Enable
High PWM Input DCR Dimming Out
Low PWM Input PWM Input
NC NC Keep High
Note.(4-1) : During the deep duty control, partial darkness or center darkness might happen
due to insufficient LED current.
Note.(4-2): At low temperature, more warm up time may be needed.
6. The measure points of V
7. Input Channel Pair Skew Margin
and V
IH
DIM_IN DIM_OUT
are in LCM side after connecting the System Board and LCM.
IL
Note: x = 0, 1, 2, 3, 4
8. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
1111////FFFF
SS
SS
SSSS
Fclk
Fclk____ss
FclkFclk
ss((((max
ssss
Fclk
Fclk
FclkFclk
Fclk
Fclk____ss
FclkFclk
ss((((min
ssss
max))))
maxmax
min))))
minmin
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 8 / 37
9. Receiver Data Input Margin
T650HVD02.0 Product Specification
Rev.1 0
Parameter Symbol
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG|
Input Data Position3 tRIP5 3T/7-|tRMG|
Input Data Position4 tRIP4 4T/7-|tRMG|
Input Data Position5 tRIP3 5T/7-|tRMG|
Input Data Position6 tRIP2 6T/7-|tRMG|
Rating
Unit
2T/7 2T/7+|tRMG| ns
3T/7 3T/7+|tRMG| ns
4T/7 4T/7+|tRMG| ns
5T/7 5T/7+|tRMG| ns
6T/7 6T/7+|tRMG| ns
tRIP2
tRIP3
tRIP4
tRIP5
Note
T=1/Fclk
tRIP6
tRIP0
tRIP1
LVDS-Rx
Input Data
Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Rx2Rx3
LVDS-Rx
VVVV
=
= 0000VVVV
= =
diff
diff
Input Clock
diff diff
1/Fclk=T
10. The relative humidity must not exceed 80% non-condensing at temperatures of 40℃ or less. At
temperatures greater than 40℃, the wet bulb temperature must not exceed 39℃. When operate at low
temperatures, the brightness of LED will drop and the life time of LED will be reduced.
11. The lifetime (MTTF) is defined as the time which luminance of LED is 50% compared to its original value.
[Operating condition: Continuous operating at Ta = 25±2℃]
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 9 / 37
3.2 Interface Connections
LCD connector: FI-RE51S-HF ( Manufactured by JAE)
T650HVD02.0 Product Specification
Rev.1 0
PIN
1
2
3
4
5
6
7
8
9
10
11
12
Symbol Description PIN
3D Function Enable
3D_EN
NC AUO Internal Use Only 27
NC AUO Internal Use Only 28
NC AUO Internal Use Only 29
LVDS 8/10bit Input Selection
BITSEL
NC AUO Internal Use Only 31
LVDS_SEL
NC AUO Internal Use Only 33
NC AUO Internal Use Only 34
NC
GND Ground 36
CH1_0- LVDS Channel 1, Signal 0-
High(3.3V):3D
Open/Low(GND):2D
Open/Low(GND) : 8bits
High(3.3V) : 10bits
Open/High(3.3V) for NS,
Low(GND) for JEIDA
AUO Internal Use Only
Symbol Description
26
30
32
35
37
NC AUO Internal Use Only
NC AUO Internal Use Only
CH2_0- LVDS Channel 2, Signal 0-
CH2_0+ LVDS Channel 2, Signal 0+
CH 2_1- LVDS Channel 2, Signal 1-
CH2_1+ LVDS Channel 2, Signal 1+
CH2_2- LVDS Channel 2, Signal 2-
CH2_2+ LVDS Channel 2, Signal 2+
GND Ground
CH2_CLK- LVDS Channel 2, Clock -
CH2_CLK+ LVDS Channel 2, Clock +
GND Ground
13
14
15
16
17
18
19
20
21
22
23
24
25
CH1_0+ LVDS Channel 1, Signal 0+
CH1_1- LVDS Channel 1, Signal 1-
CH1_1+ LVDS Channel 1, Signal 1+
CH1_2- LVDS Channel 1, Signal 2-
CH1_2+ LVDS Channel 1, Signal 2+
GND Ground
CH1_CLK- LVDS Channel 1, Clock -
CH1_CLK+ LVDS Channel 1, Clock +
GND Ground
CH1_3- LVDS Channel 1, Signal 3-
CH1_3+ LVDS Channel 1, Signal 3+
CH1_4- LVDS Channel 1, Signal 4-
CH1_4+ LVDS Channel 1, Signal 4+
51
38
39
40
41
42
43
44
45
46
47
48
49
50
CH2_3- LVDS Channel 2, Signal 3-
CH2_3+ LVDS Channel 2, Signal 3+
CH2_4- LVDS Channel 2, Signal 4-
CH2_4+ LVDS Channel 2, Signal 4+
NC AUO Internal Use Only
NC AUO Internal Use Only
GND Ground
GND Ground
GND Ground
NC AUO Internal Use Only
V
DD
V
DD
V
DD
V
DD
Power Supply, +12V DC
Regulated
Power Supply, +12V DC
Regulated
Power Supply, +12V DC
Regulated
Power Supply, +12V DC
Regulated
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 10 / 37
T650HVD02.0 Product Specification
LCD connector: FI-RE41S-HF ( Manufactured by JAE)
PIN Symbol Description PIN Symbol Description
Rev.1 0
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
NC AUO Internal Use Only 21
NC AUO Internal Use Only 22
NC AUO Internal Use Only 23
NC AUO Internal Use Only 24
NC AUO Internal Use Only 25
NC AUO Internal Use Only 26
NC AUO Internal Use Only 27
NC AUO Internal Use Only 28
GND Ground 29
CH3_0-
CH3_0+
CH3_1-
CH3_1+
CH3_2-
CH3_2+
GND
LVDS Channel 3, Signal 0- 30
LVDS Channel 3, Signal 0+ 31
LVDS Channel 3, Signal 1- 32
LVDS Channel 3, Signal 1+ 33
LVDS Channel 3, Signal 2- 34
LVDS Channel 3, Signal 2+ 35
Ground 36
CH3_3+
CH3_4- LVDS Channel 3,Signal 4-
CH3_4+
GND
GND
CH4_0-
CH4_0+
CH4_1-
CH4_1+
CH4_2-
CH4_2+
GND
CH4_CLK-
CH4_CLK+
GND
CH4_3-
LVDS Channel 3, Signal 3+
LVDS Channel 3,Signal 4+
Ground
Ground
LVDS Channel 4, Signal 0-
LVDS Channel 4, Signal 0+
LVDS Channel 4, Signal 1-
LVDS Channel 4, Signal 1+
LVDS Channel 4, Signal 2-
LVDS Channel 4, Signal 2+
Ground
LVDS Channel 4, Clock -
LVDS Channel 4, Clock +
Ground
LVDS Channel 4, Signal 3-
17
CH3_CLK+
18
19
20
CH3_CLK-
GND
CH3_3-
LVDS Channel 3, Clock - 37
LVDS Channel 3, Clock + 38
Ground 39
LVDS Channel 3, Signal 3- 40
41
CH4_3+
CH4_4- LVDS Channel 4,Signal 4-
CH4_4+
GND Ground
GND Ground
LVDS Channel 4, Signal 3+
LVDS Channel 4,Signal 4+
Note 1: All GND (ground) pins should be connected together and should also be connected to the LCD’s
metal frame.
Note 2: All VDD (power input) pins should be connected together.
Note 3: NC : please leave this pin unoccupied. It can not be connected by any signal (Low/GND/High).
Note 4: Open / High(3.3V) / Low(GND) described in 3.2.1
Note 5: 3D_EN timing described in 3.2.1
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 11 / 37
3.2.1: LVDS connector control pin description
T650HVD02.0 Product Specification
Rev.1 0
Note * : Open/High(3.3V)
Note *** : Open/Low(GND)
3D_EN control signal can only “pull high” in the middle of vertical blanking area (Tblk(V))
Note ** : Open/Low(GND)
© Copyright AUO Optronics Corp. 2012 All Rights Reserved. Page 12 / 37
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