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T500HVD02.0 SKD Product Specification
Rev.0 0
Model Name: T500HVD02.0
Issue Date: 2012/07/24
(****)Preliminary Specifications
( )Final Specifications
Customer Signature Date AUO Date
Approved By
_________________________________
Note
Approval By PM Director
CP Wang
____________________________________
Reviewed By RD Director
Eugene Chen
____________________________________
Reviewed By Project Leader
Solon Hung
____________________________________
Prepared By PM
ChihYang Wang
____________________________________
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T500HVD02.0 SKD Product Specification
Rev.0 0
Contents
No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORM
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT SPECIFICATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 PACKING
7-1 DEFINITION OF LABELS
7-2 PACKING METHODS
7-3 PALLET AND SHIPMENT INFORMATION
8 PRECAUTION
8-1 MOUNTING PRECAUTIONS
8-2 OPERATING PRECAUTIONS
8-3 ELECTROSTATIC DISCHARGE CONTROL
8-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE
8-5 STORAGE
8-6 HANDLING PRECAUTIONS FOR PROTECT FILM
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Record of Revision
T500HVD02.0 SKD Product Specification
Rev.0 0
Version
0.0 2012/07/24 First release
Date Page Description
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T500HVD02.0 SKD Product Specification
Rev.0 0
1. General Description
This specification applies to the 50 inch Color TFT-LCD SKD model T500HVD02.0. This LCD Open Cell Unit
has a TFT active matrix type liquid crystal panel 1,920x 1,080 pixels, and diagonal size of 50 inch. This Open Cell
Unit supports 1,920 x 1,080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are
arranged in vertical stripes. Gray scale or the brightness of the sub-pixel color is determined with a 8-bit gray scale
signal for each dot.
* General Information
Items Specification Unit Note
Active Screen Size 50 inch
Display Area 1095.84 (H) x 616.41(V) mm
Outline Dimension 1105.8(H) x 665 (V) x 1.4(D) mm D: cell thickness
Driver Element a-Si TFT active matrix
Bezel Opening 1097.8 (H) x 618.4 (V) mm Recommend
Display Colors 8 bit Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.19 (H) x 0.57(W) mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment Anti-Glare, 3H Haze=2%
Rotate Function Unachievable Note 1
Weight Typ. (2100) g
Display Orientation Signal input with “ABC” Note 2
Note 1: Rotate Function refers to LCD display could NOT be able to rotate.
Note 2: LCD display as below illustrated when signal input with “A”.
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T500HVD02.0 SKD Product Specification
2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 4 [Volt] Note 1
Operating Temperature TOP 0 +50 [oC] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
Storage Temperature TST -20 +60 [oC] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
Panel Surface Temperature PST 65 [oC] Note 3
Note 1: Duration: 50 msec.
Note 2 : Maximum Wet-Bulb should be 39 and No condensation.℃
Rev.0 0
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures
greater than 40 , the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50℃ Dry condition
℃ ℃
℃
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T500HVD02.0 SKD Product Specification
Rev.0 0
3. Electrical Specification
The T500HVD02.0 Open Cell Unit requires power input which is employed to power the LCD electronics and to
drive the TFT array and liquid crystal.
3.1 Electrical Characteristics
3.1.1: DC Characteristics
Parameter Symbol
LCD
Power Supply Input Voltage VDD 10.8 12 13.2 VDC
Power Supply Input Current IDD -- 1.03 1.24 A 1
Power Consumption PC -- 12.36
Inrush Current I
Permissible Ripple of Power Supply Input Voltage
Input Differential Voltage
LVDS
Interface
CMOS
Interface
Differential Input High Threshold Voltage
Differential Input Low Threshold Voltage
Input Common Mode Voltage V
Input High Threshold Voltage
Input Low Threshold Voltage
RUSH
VRP -- -- VDD * 5% mV
∣
V
∣
ID
VTH +100 -- +300 mVDC 4
VTL -300 -- -100 mVDC 4
ICM
VIH
(High)
VIL
(Low)
Min. Typ. Max
-- -- 4 A 2
200 400 600 mVDC 4
1.1 1.25 1.4 VDC 4
2.7 -- 3.3 VDC 5
0 -- 0.6 VDC 5
Value
Unit Note
16.4 Watt 1
pk-pk
3
3.1.2: AC Characteristics
Value
--
--
--
--
Fclk
+3%
200
0.4
0.5
Unit Note
MHz
6
KHz
6
ns
7
LVDS
Interface
Parameter Symbol
Receiver Clock : Spread Spectrum
Modulation range
Receiver Clock : Spread Spectrum
Modulation frequency
Receiver Data Input Margin
Fclk = 85 MHz
Fclk = 65 MHz
Fclk_ss
Fss
tRMG
Min. Typ. Max
Fclk
-3%
30
-0.4
-0.5
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Note :
T500HVD02.0 SKD Product Specification
Rev.0 0
1. V
2. Measurement condition : Rising time = 400us
3. Test Condition:
4. V
= 12.0V, Fv = 60Hz, Fclk= Max freq., 25 , Test Pattern : White Pattern℃
DD
GND
GND
GNDGND
(1) The measure point of V
(2) Under Max. Input current spec. condition.
= 1.25V
ICM
L V D S -
V
IC M
L V D S +
RP
10%
400
400
400400
is in LCM side after connecting the System Board and LCM.
90%
VVVV
DD
DD
DDDD
V
T H
|VID|
V
T L
G N D
|VID|
0 V
|VID|
5. The measure points of V
6. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
Fclk
Fclk____ss
FclkFclk
and V
IH
ss((((max
max))))
ssss
maxmax
are in LCM side after connecting the System Board and LCM.
IL
1111////FFFF
SS
SS
SSSS
Fclk
Fclk
FclkFclk
Fclk
Fclk____ss
FclkFclk
ss((((min
min))))
ssss
minmin
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7. Receiver Data Input Margin
T500HVD02.0 SKD Product Specification
Rev.0 0
Parameter Symbol
Min Type Max
Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz
Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns
Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns
Input Data Position2 tRIP6 2T/7-|tRMG|
Input Data Position3 tRIP5 3T/7-|tRMG|
Input Data Position4 tRIP4 4T/7-|tRMG|
Input Data Position5 tRIP3 5T/7-|tRMG|
Input Data Position6 tRIP2 6T/7-|tRMG|
Rating
Unit
2T/7 2T/7+|tRMG| ns
3T/7 3T/7+|tRMG| ns
4T/7 4T/7+|tRMG| ns
5T/7 5T/7+|tRMG| ns
6T/7 6T/7+|tRMG| ns
tRIP2
tRIP3
tRIP4
tRIP5
tRIP6
Note
T=1/Fclk
LVDS-Rx
Input Data
LVDS-Rx
Input Clock
tRIP0
tRIP1
Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Rx2Rx3
VVVV
=
= 0000VVVV
= =
diff
diff
diff diff
1/Fclk=T
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3.2 Interface Connections
LCD connector: 187059-5122 (P-TWO, LVDS connector)
Mating connector:
T500HVD02.0 SKD Product Specification
Rev.0 0
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 CH1_CLK- LVDS Channel 1, Clock - 44
20 CH1_CLK+ LVDS Channel 1, Clock + 45
21
22
23
24
25
Symbol Description PIN
N.C. AUO Internal Use Only 26
N.C.
N.C. AUO Internal Use Only 28
N.C.
BITSEL
N.C.
LVDS_SEL
N.C. No connection 33
N.C.
N.C.
GND Ground 36 CH2_CLK+ LVDS Channel 2, Clock +
CH1_0- LVDS Channel 1, Signal 0- 37
CH1_0+ LVDS Channel 1, Signal 0+ 38
CH1_1- LVDS Channel 1, Signal 1- 39
CH1_1+ LVDS Channel 1, Signal 1+ 40
CH1_2- LVDS Channel 1, Signal 2- 41
CH1_2+ LVDS Channel 1, Signal 2+ 42
GND Ground 43
GND Ground 46
CH1_3- LVDS Channel 1, Signal 3- 47
CH1_3+ LVDS Channel 1, Signal 3+ 48
CH1_4-
CH1_4+
AUO Internal Use Only 27
AUO Internal Use Only 29
LVDS 8/10bit Input Selection
Open/Low(GND) : 8bits
High(3.3V) : 10bits
AUO Internal Use Only 31
Open/High(3.3V) for NS,
Low(GND) for JEIDA
AUO Internal Use Only 34
AUO Internal Use Only 35 CH2_CLK- LVDS Channel 2, Clock -
LVDS Channel 1, Signal 4-
(for 10-bit input)
LVDS Channel 1, Signal 4+
(for 10-bit input)
51
30
32
49
50
Symbol Description
N.C. AUO Internal Use Only
N.C.
CH2_0- LVDS Channel 2, Signal 0-
CH2_0+ LVDS Channel 2, Signal 0+
CH2_1- LVDS Channel 2, Signal 1-
CH2_1+ LVDS Channel 2, Signal 1+
CH2_2- LVDS Channel 2, Signal 2-
CH2_2+ LVDS Channel 2, Signal 2+
GND Ground
GND Ground
CH2_3- LVDS Channel 2, Signal 3-
CH2_3+ LVDS Channel 2, Signal 3+
CH2_4-
CH2_4+
N.C. AUO Internal Use Only
N.C. AUO Internal Use Only
GND Ground
GND Ground
GND Ground
N.C. No connection
V
DD
V
DD
V
DD
V
DD
AUO Internal Use Only
LVDS Channel 2, Signal 4-
(for 10-bit input)
LVDS Channel 2, Signal 4+
(for 10-bit input)
Power Supply, +12V DC Regulated
Power Supply, +12V DC Regulated
Power Supply, +12V DC Regulated
Power Supply, +12V DC Regulated
Note: N.C.: please leave this pin unoccupied. It can not be connected by any signal
(Low/GND/High).
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