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Electrical Specification
3.
e T420XW01 requires two power inputs. One is employed to power the LCD electronics and to drive
Th
the TFT array and liquid crystal. The second input which powers the CCFL, is typically generated by
an inverter.
-1 Electrical Characteristics
3
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Para
meterSymbol
MinTypMax
LCD:
er Supply Input VoltageVdd10.81213.2Vdc
Pow
er Supply Input CurrentIdd-TBD-A1
Pow
er ConsumptionPc-TBD-Watt1
Pow
sh Current I
Inru
DS
LV
Interface
CM
OS
Interface
acklight Power Consumption-(170)-Watt2
B
fferential Input
Di
High Threshold
ol
tage
Dif
ferential Input
Low Threshold
Voltage
Common Input
Voltage
Inp
ut High
Threshold Voltage
Input Low Threshold
Voltage
USH
R
VTH+100mV
VTL-100mV
VICM1.101.251.40V
VIH
(High)
VIL
(Low)
2.43.3Vdc
V
alues
--
00.7Vdc
TBDA1
UnitNotes
4
4
e Time5000060000Hours3
Lif
Th
e performance of the Lamp in LCM, for example life time or brightness, is extremely influenced
by the characteristics of the DC-AC Inverter. So all the parameters of an inverter should be
carefully designed so as not to produce too much leakage current from high-voltage output of the
inverter. When you design or order the inverter, please make sure unwanted lighting caused by
the mismatch of the lamp and the inverter (no lighting, flicker, etc) never occurs. When you
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s
μ
c
onfirm it, the LCD Assembly should be operated in the same condition as installed in your
instrument.
Do not attach a conducting tape to lamp connecting wire. If the lamp wire attach to conducting
tape, TFT-LCD Module have a low luminance and the inverter has abnormal action because
leakage current occurs between lamp wire and conducting tape.
The relative humidity must not exceed 80% non-condensing at temperatures of 40or less. At
temperatures greater than 40 , the wet bulb temperature must not exceed 39 . When operate
at low temperatures, the brightness of CCFL wi ll drop and the lifetime of CCFL will be reduced.
Note :
1. Vdd=12.0V, fv=60Hz, f
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CLK=
81.5 Mhz , 25, Vdd Duration time= 400
,
Test pattern : white
pattern
2. The lamp power consumption shown above does include loss of external inverter at 25.The
used lamp current is the lamp typical current
3. The life is determined as the time at which luminance of the lamp is 50% compared to that of
initial value at the typical lamp current on condition of continuous operating at 25 2.
4. VICM = 1.2V
VTH
VCI
M
VTL
0V
gure : LVDS Differential Voltage
Fi
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3
-2 Interface Connections
-L
CD connector (CN1): FI-X30SSL-HF (JAE) or equivalent
-
M
ating connector: FI-30C2L (JAE) or equivalent
Pin NoSymbolDescriptionNote
1
2
3
4VCC+12V, DC, Regulated
5
6
7
8
9
10ReservedOpen or HighAUO internal test
1GNDGround and Signal Return for LVDS
1
12
13
14
15
16
17
18
19
20GNDGround and Signal Return for LVDS
21
22
23
24
25
26GNDGround and Signal Return for LVDS
27
28
29
30
VCC+12V, DC, Regulated
VCC+12V, DC, Regulated
VCC+12V, DC, Regulated
GNDGround and Signal Return
GNDGround and Signal Return
GNDGround and Signal Return
GNDGround and Signal Return
LVDS OptionLow/Open for Normal (NS), High for JEIDADefault : NS mode
RXIN0-LVDS Channel 0 negative
RXIN0+LVDS Channel 0 positive
GNDGround and Signal Return for LVDS
RXIN1-LVDS Channel 1 negative
RXIN1+LVDS Channel 1 positive
GNDGround and Signal Return for LVDS
RXIN2-LVDS Channel 2 negative
RXIN2+LVDS Channel 2 positive
RXCLKIN-LVDS Clock negative
RXCLKIN+LVDS Clock positive
GNDGround and Signal Return for LVDS
RXIN3-LVDS Channel 3 negative
RXIN3+LVDS Channel 3 positive
ReservedOpen or HighAUO internal test
ReservedOpen or HighAUO internal test
GNDGround and Signal Return
GNDGround and Signal Return
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Î
Î
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VDS Option = HighÎ
L
Pre
vious Cycle
Clock
RIN0+
RIN0-
RIN1+
RIN1-
RIN2+
RIN2-
IN3+
R
RIN3-
L
VDS Option = Low/OPEN
JEIDA
NS
C
urrent Cycle
N
ext Cycle
R2R7G2G2R2R3R4R5R6R3
G3B2B3B3G3G4G5G6G6G4
B4NADEDEB4B5B6B7NAB5
R0B1NANAR0R1G0G1B0R1
Clock
RIN0+
RIN0-
RIN1+
RIN1-
RIN2+
RIN2-
R
IN3+
RIN3-
Previous CycleCurrent CycleNext Cycle
R0R5G0G0R0R1R2R3R4R1
G1B0B1B1G1G2G3G4G5G2
B2NADEDEB2B3B4B5NAB4
R6B7NANAR6R7G6G7B6R7
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Backlight Connector Pin Configuration
1
. Electrical specification
NoITEMSYMBOLCONDITIONMIN TYP MAX UNITNote
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Input Voltage V
1
2
Input Current I
Input Power P
3
Input inrush currentI
4
5
Output Frequency F
/OFF Control
ON
6
Voltage
ON
/OFF Control
7
Current
xternal PWM
E
8
Control Voltage
E
xternal PWM
9
Control Current
xternal PWM Duty
E
10
Ratio
V
EV
EI
DDB
DDB
DDB
RUSH
V
BL
LON
B
OF
V
I
BLON
M
PWM
M
Max. Brightness
V
ON
FV
AX---2.0---3.3V
IN---0---0.7V
MAXPWM=100%TBD------ mA
PW
M
MINPWM=100%TBD------ mA
ED
PW
M
---
4V
V
=2
DDB
4V
V
=2
DDB
22.8 24.0 26.4 V
TBD TBD TBDA
---(170) TBDW1
Dimming Max.
V
=24V
DDB
------(12)A
Dimming Max.
=
24V---58---kHz
DDB
4V2.0---3.3V
=2
DDB
24V0.0---0.7V
=
DDB
=
24VTBD---TBD mA
DDB
-
--30---100%
DC
DC
DC
DC
DC
DC
DC
1
2
DC
DC
DC
xternal PWM
E
11
Frequency
EF
PWM
Note 1 : VDIM/Open = 1.6V; PDIM = Open/High
Note 2 : Duration = 20 ms
---
120180300Hz
Ta
=255, Turn on for 45minutes
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Input specification
2.
Master Board:
nnector 1: JST_S14B-PH-SM3-TB or equivalent
Co
Pin NoSymbolDescription
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
BLGNDGround and Current Return
BLGNDGround and Current Return
BLGNDGround and Current Return
BLGNDGround and Current Return
BLGNDGround and Current Return
V
DIM
(ADIM)
VBLONBL On-Off: Open/High (3.3V) for BL On as default
(2
PDIM
DIM
P
Selection
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GND:
)
(1
)
)
(3
80%; Open/1.6V: 100%; High (3.3V) 120%, Luminance
External PWM/Analog Dimming Control input;
Open/High (3.3V, 100% Duty) for 100%
GND:
External PWM dimming;
Open/High: Analog dimming.
Note (1) VDIM is control signal for Inverter ’s output Power to Back Light Lamp Bulb. Input Signal
should be able to control Amplitude of Inverter Output voltage. From 0V to 3.3V, Inverter
Output Voltage should be able to vary to control Brightness of Lamp from 80% to 120%
Luminescence variation. Approx. 1.6V might be 100% Luminance control point.
Note (2) PDIM is PWM duty control Input for +3.3V TTL Level Signal. This Input Signal is Continuous
Pulse Signal with +3.3V, TTL Level Signal Spec. If this is Open or +3.3V, 100% Duty (i.e.
+3.3V, DC level), Back Light should perform 100% Luminance. Duty Ratio of this Input
signal should be proportional relationship in certain range of control without any kind of
inherent side effect like Waterfall effect on Screen. Guaranteed Duty Range and Dimming
Ratio should be specified with supplementary measurement result.
Note (3) 14 Pin is selection pin for PWM control method; if this pin is connected to GND, PDIM input
th
of 13
Open, 13
Wave Generator to generate internal PWM signal. Default setting is “Analog”, means when it
is “Not Connected”, 13
P
in should have Logic Level Duty Signal for PWM control. If this is set to High or
th
Pi
n should have DC level signal therefore the Inverter should have Saw Tooth
th
in of PWM control should be have DC Level signal for PWM.
p
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Slav
e Board:
nnector 2: JST_S12B-PH-SM3-TB or equivalent
Co
Pin NoSymbolDescription
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1
2
3
4
5
6BLGNDGround and Current Return
7
8
9
1
0BLGNDGround and Current Return
11
12
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
VDDBOperating Voltage Supply, +24V DC regulated
BLGNDGround and Current Return
BLGNDGround and Current Return
BLGNDGround and Current Return
NC
NC
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Signal Timing Specifications
3-3
is is the signal timing required at the input of the User connector. All of the interface signal timing
Th
should be satisfied with the following specifications for it ’s proper operation.
Timing Table (DE only Mode)
SignalItemSymbolMinTypeMaxUnit
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Period
A
ctiveTdisp (v)—768—Th
ertical Section
V
zontal Section
Hori
Cl
ock
ertical Frequency
V
zntal Frequency
Hori
ertical Frequency
V
Hori
zntal Frequency
LK signal input must be valid while power supply is applied.
*1) DC
*2) Display position is specific by the rise of ENAB signal only.
Horizontal display position is specified by the falling edge of 1
displayed on the left edge of the screen.
Vertical display position is specified by the rise of ENAB after a “Low” level period equivalent to eight
times of horizontal period. The 1
is displayed at the top line of screen.
3.) If a period of ENAB “High” is less than 1366 DCLK or less than 768 lines, the rest of the screen
displays black.
4.) The display position does not fit to the screen if a period of ENAB “High” and the effective data
period do not synchronize with each other.
BlankingTblk (v)2154Th
Period
A
ctiveTdisp (h)—1366—Tc l k
BlankingTblk (h)48356Tclk
Period
FrequencyFreq5588MHz
equency
Fr
equency
Fr
equency
Fr
Fr
equency
st
ta corresponding to one horizontal line after the rise the of ENAB
da
Tv789822Th
Th14141722Tclk
CLK——18.18ns
Vs586062Hz
Hs4
Vs485052Hz
Hs3
7.34
9.45
st
DCLK
right after the rise of ENAB, is
49.3
4
1.1
2
KHz
KHz
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3-4 Signal Timing Waveforms
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RGB Dat a
1366
Invalid Data
1
2
3
4
5
6
Tc
DE
Pixel
Pixel
Pi xel
Pixel
Pixel
Pix el
Pixel
Tdisp(h)
CLK
Tcl k
Th
RG
Data
B
Line
768
Invalid DataInvalid Data
Line
1
Line
2
Line
3
Li ne
4
DE
Th
Tv
Td
isp(v)
1366
Pix el
Line
768
Invalid Data
Pix el
1
Pixel
2
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3-5 Color Input Data Reference
Th
e brightness of each primary color (red, green and blue) is based on the 8 bit gray scale data input
for the color; the higher the binary input, the brighter the color. The table below provides a reference for