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T400HW02 V5
Specification
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AUO T400HW02 V5 Specification

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Product Description: T400HW02 TFT-LCD PANEL with RoHS guarantee
AUO Model Name: T400HW02 V5
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Customer Part No/Project Name:
Customer Signature Date AUO Date
Approved By: PM Director / Frank Hsu
Reviewed By: RD Director / Hong Jye Hong
Reviewed By: Project Leader /Bruce Liu
Prepared By: PM /Cynthia Hung
---------------------------------------------
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Document Version: 0.0
Date:2008/09/30
Product Specifications
40” Full HD Color TFT-LCD Module
Model Name: T400HW02 V5
(*) Preliminary Specifications
() Final Specifications
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No
CONTENTS
RECORD OF REVISIONS
1 GENERAL DESCRIPTION
2 ABSOLUTE MAXIMUM RATINGS
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Contents
3 ELECTRICAL SPECIFICATION
3-1 ELECTRIACL CHARACTERISTICS
3-2 INTERFACE CONNECTIONS
3-3 SIGNAL TIMING SPECIFICATION
3-4 SIGNAL TIMING WAVEFORM
3-5 COLOR INPUT DATA REFERENCE
3-6 POWER SEQUENCE
3-7 BACKLIGHT CONNECTOR PIN CONFIGURATION
4 OPTICAL SPECIFICATION
5 MECHANICAL CHARACTERISTICS
6 RELIABILITY TEST ITEMS
7 INTERNATIONAL STANDARD
7-1 Safety
7-2 EMC
8 PACKING
9 PRECAUTION
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Record of Revision
Version Data No Old Description New Decription Remark
0.0 2008/09/30 First release N/A
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1. General Description
This specification applies to the 40.0 inch Color TFT-LCD Module T400HW02 V5. This LCD
module has a TFT active matrix type liquid crystal panel 1,920x1,080 pixels, and diagonal size of 40.0
inch. This module supports 1,920x1,080 mode. Each pixel is divided into Red, Green and Blue
sub-pixels or dots which are arranged in vertical stripes. Gray scale or the brightness of the sub-pixel
color is determined with a 10-bit gray scale signal for each dot.
The T400HW02 V5 has been designed to apply the 10-bit 2 channel LVDS interface method. It is
intended to support displays where high brightness, wide viewing angle, high color saturation, and
high color depth are very important.
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* General Information
Items Specification Unit Note
Active Screen Size 40.00 inch
Display Area 885.6(H) x 498.15(V) mm
Outline Dimension 952.0(H) x 551.0 (V) x 49.6(D) mm With T-con cover
Driver Element a-Si TFT active matrix
Display Colors 10 bit, 1073.7M Colors
Number of Pixels 1,920x1,080 Pixel
Pixel Pitch 0.46125 (H) x 0.46125(W) mm
Pixel Arrangement RGB vertical stripe
Display Operation Mode Normally Black
Surface Treatment
Super Clear
(Anti-reflection coating)
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2. Absolute Maximum Ratings
The followings are maximum values which, if exceeded, may cause faulty operation or damage to the
unit
Item Symbol Min Max Unit Condition
Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1
Input Voltage of Signal Vin -0.3 3.6 [Volt] Note 1
Operating Temperature TOP 0 +50 [oC] Note 2
Operating Humidity HOP 10 90 [%RH] Note 2
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s
Storage Temperature TST -20 +60 [oC] Note 2
Storage Humidity HST 10 90 [%RH] Note 2
Panel Surface Temperature PST 65 [oC] Note 3
Note 1: Duration:50 msec.
Note 2 : Maximum Wet-Bulb should be 39and No condensation.
The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At
temperatures greater than 40, the wet bulb temperature must not exceed 39 .
Note 3: Surface temperature is measured at 50 Dry condition
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3. Electrical Specification
The T400HW02 V5 requires two power inputs. One is employed to power the LCD electronics and to
drive the TFT array and liquid crystal. The second input, which powers the CCFL, is typically
generated by an integrate power (I/P) system.
3.1 Electrical Characteristics
Parameter Symbol
LCD
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Value
Unit Note
Min. Typ . Max
Power Supply Input Voltage V
Power Supply Input Current I
Power Consumption P
Inrush Current I
DD
DD
C
RUSH
10.8 12 13.2 V
DC
-- 1.14 1.25 A 2
-- 13.68 15.0 Watt 2
-- -- 4.5 A 3
Differential Input High Threshold
-- -- +100 mV
-100 -- -- mV
0.6 1.2 1.8 V
2.4 -- 3.3 V
0 -- 0.7 V
DC
DC
DC
DC
DC
LVDS
Interface
CMOS
Interface
Voltage
Differential Input Low Threshold
Voltage
Input Common Mode Voltage V
Input High Threshold Voltage
Input Low Threshold Voltage
V
TH
V
TL
ICM
V
IH
(High)
V
IL
(Low)
Life Time 50000 -- Hours
1
4
4
4
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s
μ
Note :
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1. The ripple voltage should be controlled under 10% of V
2. Vcc=12.0V, =
3. Measurement condition :
4. VCIM = 1.2V
5. The performance of the Lamp in LCD panel, for example life time or brightness, is extremely
f 60Hz, fCLK=81.5Mhz , 25, Test Pattern : White Pattern
v
0.9 Vdd
GND
VTH
VCIM
VTL
0.1 Vdd
400
0V
CC
Vdd
influenced by the characteristics of balanced board and I/P board. All the parameters should
be carefully designed as not to produce too much leakage current from high-voltage output.
While you design or order the balance board, please make sure unwanted lighting caused by
the mismatch of the lamp and the balanced board (no lighting, flicker, etc) never occurs. After
confirmation, the LCD panel should be operated in the same condition as installed in your
instrument
6. Do not attach a conducting tape to lamp connecting wire. If the lamp wire attach to conducting
tape, TFT-LCD Module have a low luminance and the inverter has abnormal action because
leakage current occurs between lamp wire and conducting tape.
7. The relative humidity must not exceed 80% non-condensing at temperatures of 40  or less.
At temperatures greater than 40, the wet bulb temperature must not exceed 39 .When
operate at low temperatures, the brightness of CCFL will drop and the life time of CCFL will be
reduced.
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3.2 Interface Connections
LCD connector: FI-RE51S-HF (JAE)
Mating connector: FI-RE51S-HL (JAE)
PIN # Signal Name Description
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1 V
2 V
3 V
4 V
5 V
DD
DD
DD
DD
DD
Operating Voltage Supply, +12V DC Regulated
Operating Voltage Supply, +12V DC Regulated
Operating Voltage Supply, +12V DC Regulated
Operating Voltage Supply, +12V DC Regulated
Operating Voltage Supply, +12V DC Regulated
6 GND Ground
7 GND Ground
8 GND Ground
9 GND Ground
10 RO_0- LVDS Channel Odd, Signal 0-
11 RO_0+ LVDS Channel Odd, Signal 0+
12 RO_1- LVDS Channel Odd, Signal 1-
13 RO_1+ LVDS Channel Odd, Signal 1+
14 RO_2- LVDS Channel Odd, Signal 2-
15 RO_2+ LVDS Channel Odd, Signal 2+
16 GND Ground
17 RO_CLK- LVDS Channel Odd, Clock -
18 RO_CLK+ LVDS Channel Odd, Clock +
19 GND Ground
20 RO_3- LVDS Channel Odd, Signal 3-
21 RO_3+ LVDS Channel Odd, Signal 3+
22 NC No Connect (Reserved for 10-bit)
23 NC No Connect (Reserved for 10-bit)
24 GND Ground
25 RE_0- LVDS Channel Even, Signal 0-
26 RE_0+ LVDS Channel Even, Signal 0+
27 RE_1- LVDS Channel Even, Signal 1-
28 RE_1+ LVDS Channel Even, Signal 1+
29 RE_2- LVDS Channel Even, Signal 2-
30 RE_2+ LVDS Channel Even, Signal 2+
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31 GND Ground
32 RE_CLK- LVDS Channel Even, Clock -
33 RE_CLK+ LVDS Channel Even, Clock +
34 GND Ground
35 RE_3- LVDS Channel Even, Signal 3-
36 RE_3+ LVDS Channel Even, Signal 3+
37 NC No Connect (Reserved for 10-bit)
38 NC No Connect (Reserved for 10-bit)
39 GND Ground
40 SCL_TCON Please leave it open
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41 SDA_TCON Please leave it open
42 NC Please leave it open
43 B_INT
44 Hsync_OUT H-Sync Output for Inverter/IPB
45 LVDS_SEL Open/High(3.3V) for NS, Low(GND) for JEIDA
46 SCL_FRC EEPROM Serial Clock for FRC
47 Reset_FRC Reset for FRC Chip
48 SDA_FRC EEPROM Serial Data for FRC
49 PVCC_SW Panel VCC Sequence Control
50 SYS_DET
51 NC Please leave it open
B_INT(same as WP);EEPROM Write Protection
High(3.3V) for Writable, Low(GND) for Protection
Detection Pin to Check if System Board Connected
(GND if connected)
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