AUO P650HVN02.5 Specification

P650HVN02.5 Product Specification

Rev. 0.0

Model Name: P650HVN02.5

Issue Date: 2013/03/28

(＊＊＊＊)Preliminary Specifications

()Final Specifications

Customer Signature Date AUO Date

Approved By

_________________________________

Note

Reviewed By PM Director

Paley Fang

____________________________________

Reviewed By RD Director

Eugene CC Chen

____________________________________

Reviewed By Project Leader

Dalon Tseng

____________________________________

Prepared By PM

Antonio Kuo

____________________________________

P650HVN02.5 Product Specification

Rev. 0.0

Contents

Record of Revision .................................................................................................................. 3

1. General Description .......................................................................................................... 4

2. Absolute Maximum Ratings ............................................................................................. 5

3. Electrical Specification ........................................................................................................ 6

3.1.1 Electrical Characteristics ........................................................................................ 6

3.1.2 AC Characteristics ................................................................................................... 6

3.3 Signal Timing Specification ..................................................................................... 13

3.4 Signal Timing Waveforms ........................................................................................ 14

3.5 Color Input Data Reference...................................................................................... 15

3.6 Power Sequence ....................................................................................................... 16

3.7 Backlight Specification............................................................................................. 17

3.7.1 Electrical specification .................................................................................. 17

3.7.2 Input Pin Assignment ..................................................................................... 18

4. Optical Specification.......................................................................................................... 20

5. Mechanical Characteristics ............................................................................................... 23

5.1 Placement suggestions:........................................................................................... 23

Front View................................................................................................................. 24

Back View ................................................................................................................. 25

6. Reliability Test Items.......................................................................................................... 26

7. International Standard ....................................................................................................... 27

8. Packing ............................................................................................................................... 28

8-1 DEFINITION OF LABEL: ........................................................................................... 28

8-2 PACKING METHODS: ............................................................................................... 29

8-3 Pallet and Shipment Information ............................................................................. 30

9. PRECAUTIONS ................................................................................................................... 31

9-1 MOUNTING PRECAUTIONS ..................................................................................... 31

9-2 OPERATING PRECAUTIONS.................................................................................... 31

9-3 ELECTROSTATIC DISCHARGE CONTROL ............................................................. 32

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE ................................................ 32

9-5 STORAGE .................................................................................................................. 32

9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM............................................ 32

9-7 OPERATING CONDITION in PID APPLICATION...................................................... 32

Record of Revision

P650HVN02.5 Product Specification

Rev. 0.0

Version

0.0 2013/03/28

Date Page Description

First release

P650HVN02.5 Product Specification

Rev. 0.0

1. General Description

This specification applies to the 64.5 inch Color TFT-LCD Module P650HVN02.5. This LCD module has a TFT

active matrix type liquid crystal panel 1920 x 1080 pixels, and diagonal size of 64.5 inch. This module supports

1920 x 1080 mode. Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical

stripes. Gray scale or the brightness of the sub-pixel color is determined with a 10-bit gray scale signal for each

dot.

The P650HVN02.5 has been designed to apply the 10-bit 2 channel LVDS interface method. It is intended to

support displays where high brightness, wide viewing angle, high color saturation, and high color depth are very

important.

* General Information

Items Specification Unit Note

Active Screen Size 64.53 inch

Display Area 1428.48 (H) x 803.52 (V) mm

Outline Dimension 1508.0(H) x 878.0(V) x 12.8(D) mm

Driver Element a-Si TFT active matrix

Display Colors 10 bit, 1.07B Colors

Number of Pixels 1920 x 1080 Pixel

Pixel Pitch 0.744 mm

Pixel Arrangement RGB vertical stripe

Display Operation Mode Normally Black

Surface Treatment Anti-Glare, 3H Haze 11%

Display Orientation Portrait/Landscape Enable

Note:

[1] Please refer to 5.1 Placement Suggestions.

[1]

P650HVN02.5 Product Specification

2. Absolute Maximum Ratings

The followings are maximum values which, if exceeded, may cause faulty operation or damage to the unit

Item Symbol Min Max Unit Conditions

Logic/LCD Drive Voltage Vcc -0.3 14 [Volt] Note 1

Input Voltage of Signal Vin -0.3 4 [Volt] Note 1

Operating Temperature TOP 0 +50 [oC] Note 2

Operating Humidity HOP 10 90 [%RH] Note 2

Storage Temperature TST -20 +60 [oC] Note 2

Storage Humidity HST 10 90 [%RH] Note 2

Panel Surface Temperature PST 65 [oC] Note 3

Note 1: Duration:50 msec.

Note 2 : Maximum Wet-Bulb should be 39 and No condensation.℃

Rev. 0.0

The relative humidity must not exceed 90% non-condensing at temperatures of 40 or less. At temperatures

greater than 40 , the wet℃ bulb temperature must not exceed 39 .℃

Note 3: Surface temperature is measured at 50℃ Dry condition

℃

P650HVN02.5 Product Specification

Rev. 0.0

3. Electrical Specification

The P650HVN02.5 requires two power inputs. One is employed to power the LCD electronics and to drive the

TFT array and liquid crystal. The second is employed for LED driver.

3.1.1 Electrical Characteristics

Parameter Symbol

LCD

Power Supply Input Voltage VDD 10.8 12 13.2 VDC

Power Supply Input Current IDD --

Power Consumption PC -- 6.96 13.2 Watt 1

Inrush Current I

Permissible Ripple of Power Supply Input Voltage (for input power=12V)

Input Differential Voltage

Differential Input High Threshold

LVDS

Interface

Voltage

Differential Input Low Threshold

Voltage

Input Common Mode Voltage

RUSH

VRP -- -- VDD * 5%

∣

V

∣

ID

VTH +100 -- +300 mVDC 4

V

TL

V

ICM

Min. Typ. Max

- -- 7.5 A 2

200 400 600 mVDC 4

-300 -- -100 mV

1.1

Value

0.58 1.1

1.25

1.4

Unit Note

A 1

mV

V

pk-pk

DC

3

4

CMOS

Input High Threshold Voltage

Interface

Input Low Threshold Voltage

Backlight Power Consumption PBL -- 206.4 216.1 W

Life Time(MTTF) 50,000

VIH

2.7 -- 3.3 VDC

(High)

VIL

0 -- 0.6 VDC

(Low)

-- -- -- 6, 7

3.1.2 AC Characteristics

Value

--

Fclk

+3%

200

0.4

0.5

Unit Note

MHz

KHz

ns

10

LVDS Interface

Parameter Symbol

Input Channel Pair Skew Margin t

Receiver Clock : Spread Spectrum Modulation range

Receiver Clock : Spread Spectrum Modulation frequency

Receiver Data Input Margin Fclk = 85 MHz Fclk = 65 MHz

SKEW (CP)

Fclk_ss

Fss

tRMG

Min. Typ. Max

-500 -- +500 ps 8

Fclk

-3%

30

-0.4

-0.5

5

9

s

µ

Note :

P650HVN02.5 Product Specification

Rev. 0.0

1. T V

= 12.0V, Fv = 60Hz, Fclk= Max freq. , 25 ℃, Test Pattern : White Pattern

DD

>> refer to “Section:3.3 Signal Timing Specification, Typical timing”

2. Measurement condition : Rising time = 400us

GND

GNDGND

10%

400

400400

3. Test Condition:

(1) The measure point of V

is in LCM side after connecting the System Board and LCM.

RP

(2) Under Max. Input current spec. condition.

4. V

= 1.25V

ICM

L V D S -

V

IC M

L V D S +

90%

VVVV

DD

DDDD

V

T H

|VID|

V

T L

G N D

|VID|

0 V

|VID|

5. The measure points of V

6. The relative humidity must not exceed 80% non-condensing at temperatures of 40 or less. At

temperatures greater than 40 , the wet bulb temperature must not exceed 39 . When operat

temperatures, the brightness of LED will drop and the life time of LED will be reduced.

7. The lifetime (MTTF) is defined as the time which luminance of LED is 50% compared to its original value.

[Operating condition: Continuous operating at Ta = 25±2℃]

8.

Input Channel Pair Skew Margin

and V

IH

are in LCM side after connecting the System Board and LCM.

IL

℃ ℃

℃

img at low

P650HVN02.5 Product Specification

Note: x = 0, 1, 2, 3, 4

9. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures

1111////FFFF

SS

SSSS

Fclk

Fclk____ss

FclkFclk

ss((((max

max))))

ssss

maxmax

Rev. 0.0

Fclk

FclkFclk

Fclk

Fclk____ss

FclkFclk

ss((((min

min))))

ssss

minmin

10. Receiver Data Input Margin

Parameter Symbol

Min Type Max

Input Clock Frequency Fclk Fclk (min) -- Fclk (max) MHz

Input Data Position0 tRIP1 -|tRMG| 0 |tRMG| ns

Input Data Position1 tRIP0 T/7-|tRMG| T/7 T/7+|tRMG| ns

Input Data Position2 tRIP6 2T/7-|tRMG|

Input Data Position3 tRIP5 3T/7-|tRMG|

Input Data Position4 tRIP4 4T/7-|tRMG|

Input Data Position5 tRIP3 5T/7-|tRMG|

Input Data Position6 tRIP2 6T/7-|tRMG|

Rating

Unit

2T/7 2T/7+|tRMG| ns

3T/7 3T/7+|tRMG| ns

4T/7 4T/7+|tRMG| ns

5T/7 5T/7+|tRMG| ns

6T/7 6T/7+|tRMG| ns

Note

T=1/Fclk

LVDS-Rx Input Data

LVDS-Rx Input Clock

tRIP2

tRIP3

tRIP4

tRIP5

tRIP6

tRIP0

tRIP1

P650HVN02.5 Product Specification

Rev. 0.0

Rx1 Rx0 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 Rx6Rx2Rx3

VVVV

=

= 0000VVVV

= =

diff

diff diff

1/Fclk=T

3.2 Interface Connections

 LCD connector : FI-RE51S-HF (Manufactured by JAE);  Mating connector: FI- RE51S-HL (Manufactured by JAE)

P650HVN02.5 Product Specification

Rev. 0.0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Symbol Description PIN

Reserve AUO Internal Use Only 26

Reserve AUO Internal Use Only 27

Reserve AUO Internal Use Only 28

Reserve AUO Internal Use Only 29

Open/High(3.3V) for 10bit,

BITSEL

Low(GND) for 8bit

Reserve AUO Internal Use Only 31

Open/High(3.3V) for NS,

LVDS_SEL

Low(GND) for JEIDA

Reserve AUO Internal Use Only 33

Reserve AUO Internal Use Only 34

Reserve AUO Internal Use Only 35

GND Ground 36

CH1_0-

CH1_0+

CH1_1-

LVDS Channel 1, Signal 0- 37

LVDS Channel 1, Signal 0+ 38

LVDS Channel 1, Signal 1- 39

30

32

Symbol Description

GND Ground

CH2_0-

CH2_0+

CH2_1-

CH2_1+

CH2_2-

CH2_2+

LVDS Channel 2, Signal 0-

LVDS Channel 2, Signal 0+

LVDS Channel 2, Signal 1-

LVDS Channel 2, Signal 1+

LVDS Channel 2, Signal 2-

LVDS Channel 2, Signal 2+

GND Ground

CH2_CLK-

CH2_CLK+

LVDS Channel 2, Clock -

LVDS Channel 2, Clock +

GND Ground

CH2_3-

CH2_3+

LVDS Channel 2, Signal 3-

LVDS Channel 2, Signal 3+

15

16

17

18

19

20

21

22

23

24

25

CH1_1+

CH1_2-

CH1_2+

LVDS Channel 1, Signal 1+ 40

LVDS Channel 1, Signal 2- 41

LVDS Channel 1, Signal 2+ 42

GND Ground 43

CH1_CLK-

CH1_CLK+

LVDS Channel 1, Clock - 44

LVDS Channel 1, Clock + 45

GND Ground 46

CH1_3-

CH1_3+

CH1_4-

CH1_4+

LVDS Channel 1, Signal 3- 47

LVDS Channel 1, Signal 3+ 48

LVDS Channel 1, Signal 4- 49

LVDS Channel 1, Signal 4+ 50

51

CH2_4-

CH2_4+

LVDS Channel 2, Signal 4-

LVDS Channel 2, Signal 4+

GND Ground

Reserve AUO Internal Use Only

VDD Power Supply, +12V DC Regulated

Note 1: All GND (ground) pins should be connected together and should also be connected to the LCD’s

metal frame.

Note 2: All VDD (power input) pins should be connected together.

Note 3: All Reserved pins should be open without voltage input.

P650HVN02.5 Product Specification

Rev. 0.0

Note * : Open/High(3.3V)

LVDS Option = High/OpenNS

Previous C ycle Current Cycle Next Cycle

Previous C ycle Current Cycle Next Cycle Previous C ycle Current Cycle Next Cycle

Note ** : Open/Low(GND)

Clock

ClockClock

CHx

CHx____0000++++

CHxCH x CHx

CHx____0000----

CHxCH x

CHx

CHx____1111++++

CHxCH x CHx

CHx____1111----

CHxCH x

CHx

CHx____2222++++

CHxCH x CHx

CHx____2222----

CHxCH x

CHx

CHx____3333++++

CHxCH x CHx

CHx____3333----

CHxCH x

CHx

CHx____4444++++

CHxCH x CHx

CHx____4444----

CHxCH x

DEBBBB2222BBBB3333 BBBB4444BBBB5555NA

DEDE

NARRRR6666RRRR7777 GGGG6666GGGG7777BBBB6666 RRRR7777

NANA

NARRRR8888RRRR9999 GGGG8888GGGG9999BBBB8888 RRRR9999

NANA

NA DE

NANA

NA BBBB3333

NANA

RRRR0000RRRR5555 GGGG0000GGGG0000RRRR0000RRRR1111 RRRR2222RRRR3333RRRR4444 RRRR1111

GGGG1111BBBB0000 BBBB1111BBBB1111GGGG1111GGGG2222 GGGG3333GGGG4444GGGG5555 GGGG2222

BBBB2222NA

RRRR6666BBBB7777 NA

RRRR8888BBBB9999 NA

DEDE

NANA

Note: x = 1, 2, 3, 4…

LVDS Option = LowJEIDA

Previous Cycle Current Cycle Next Cycle

Previous Cycle Current Cycle Next Cycle Previous Cycle Current Cycle Next Cycle

Clock

ClockClock

CHx

CHx____0000++++

CHxCHx CHx

CHx____0000----

CHxCHx

CHx

CHx____1111++++

CHxCHx CHx

CHx____1111----

CHxCHx

P650HVN02.5 Product Specification

Rev. 0.0

RRRR4444RRRR9999 GGGG4444GGGG4444RRRR4444RRRR5555 RRRR6666RRRR7777RRRR8888 RRRR5555

GGGG5555BBBB4444 BBBB5555BBBB5555GGGG5555GGGG6666 GGGG7777GGGG8888GGGG9999 GGGG6666

CHx

CHx____2222++++

CHxCHx CHx

CHx____2222----

CHxCHx

CHx

CHx____3333++++

CHxCHx CHx

CHx____3333----

CHxCHx

CHx

CHx____4444++++

CHxCHx CHx

CHx____4444----

CHxCHx

Note: x = 1, 2, 3, 4…

DEBBBB6666BBBB7777 BBBB8888BBBB9999NA

DEDE

NARRRR2222RRRR3333 GGGG2222GGGG3333BBBB2222 RRRR3333

NANA

NARRRR0000RRRR1111 GGGG0000GGGG1111BBBB0000 RRRR1111

NANA

NA DE

NANA

NA BBBB7777

NANA

BBBB6666NA

RRRR2222BBBB3333 NA

RRRR0000BBBB1111 NA

DEDE

NANA

P650HVN02.5 Product Specification

Rev. 0.0

3.3 Signal Timing Specification

This is the signal timing required at the input of the user connector. All of the interface signal timing should be

satisfied with the following specifications for its proper operation.

Timing Table (DE only Mode)

Vertical Frequency Range (60Hz)

Signal Item Symbol Min. Typ. Max Unit

Period Tv

Vertical Section

Horizontal Section

Clock Frequency Fclk=1/Tclk 50 74.25 82 MHz

Vertical Frequency Frequency Fv 47 60 63 Hz

Horizontal Frequency

Notes:

(1) Horizontal Blanking must be even number

(2) Display position is specific by the rise of DE signal only.

Horizontal display position is specified by the rising edge of 1st DCLK after the rise of 1st DE, is displayed on the

left edge of the screen.

Active Tdisp (v) 1080 Th

Blanking Tblk (v)

Period Th 1040 1100 1328 Tclk

Active Tdisp (h) 960 Tclk

Blanking Tblk (h) 80 140 368 Tclk

Frequency Fh 60 67.5 73 KHz

1100

20

1125 1480

45 400

Th

(3)Vertical display position is specified by the rise of DE after a “Low” level period equivalent to eight times of

horizontal period. The 1st data corresponding to one horizontal line after the rise of 1st DE is displayed at the top

line of screen.

(4)If a period of DE “High” is less than 1920 DCLK or less than 1080 lines, the rest of the screen displays black.

(5)The display position does not fit to the screen if a period of DE “High” and the effective data period do not

synchronize with each other.

3.4 Signal Timing Waveforms

P650HVN02.5 Product Specification

Rev. 0.0

CH2

Pixel

M-6

Pixel

M-4

Pixel

M-2

Pixel

M

Invalid Data

Pixel

2

Pixel

4

Pixel

6

CH1

Pixel

M-7

Pixel

M-5

Pixel

M-3

Pixel

M-1

Invalid Data

Pixel

1

Pixel

3

Pixel

5

DE

CLK

RGB

Data

Line

N

Tclk

Invalid Data Invalid Data

Line

1

Line

2

DE

Th

Tv

Pixel

8

Pixel

10

Pixel

12

Pixel

M-4

Pixel

M-2

Pixel

M

Invalid Data

Pixel

2

Pixel

7

Tdisp(h) Tblk(h)

Pixel

9

Pixel

11

Pixel

M-5

Pixel

M-3

Pixel

M-1

Invalid Data

Pixel

1

Th

Line

3

Line

4

Line

N

N Line

N LineN Line

Tdisp(v)Tblk(v)

M

M p

p

p i

i

x

x e

e

e l

l

Pixel

4

Pixel

3

Basic

P650HVN02.5 Product Specification

Rev. 0.0

3.5 Color Input Data Reference

The brightness of each primary color (red, green and blue) is based on the 10 bit gray scale data input for the

color; the higher the binary input, the brighter the color. The table below provides a reference for color versus data

input.

COLOR DATA REFERENCE

Input Color Data

Color

Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Red(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Green(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

Blue(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Color

Cyan 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Magenta 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RED(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(001) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

R

----

RED(1022) 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RED(1023) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB LSB

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

RED

MSB LSB

GREEN

BLUE

MSB LSB

GREEN(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GREEN(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0

G

----

GREEN(1022) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

GREEN(1023) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0

BLUE(000) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BLUE(001) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

B

----

BLUE(1022) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0

BLUE(1023) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

3.6 Power Sequence

 Power Sequence of LCD

P650HVN02.5 Product Specification

Rev. 0.0

Pow er Sup p ly For LCD

Pow er Sup p ly For LCD Pow er Sup p ly For LCD VD D

VD D (+

(+ 12

VD D VD D

In ter fa c e Sig n a l

In ter fa c e Sig n a lIn ter fa c e Sig n a l ((((LV DS D a ta

12 VVVV ))))

(+(+

121 2

LV DS D a ta &

LV DS D a ta LV DS D a ta

& C LK

& &

G ND

CLK ))))

CLKCLK

G ND

Back lig h t o n

Back lig h t o n ////o ff

Back lig h t o nBack lig h t o n co n tro l sig n a l

co n tro l sig n a l

co n tro l sig n a lco n tro l sig n a l ((((VBLO N

VBLO N ))))

VBLO NVBLO N

off

offoff

GN D

CM O S In terface S ignal

CM O S In terface S ignalCM O S In terface S ignal

G ND

Parameter

t1 0.4 --- 30 ms

t2 0.1 --- 50 ms

10 %

90 %

t1

t2

Valid D ata

Valid D ataV a lid Da ta

t3 t4

t8 t9

Values

Min. Type. Max.

90 %

10 %

t6

t5

10 %

t7

Unit

t3 450 --- --- ms

t4 0*1 --- --- ms

t5 0 --- --- ms

t6 --- --- ---*2 ms

t7 500 --- --- ms t8 10 --- 50 ms

t9 0 --- --- ms

Note: (1) t4=0 : concern for residual pattern before BLU turn off. (2) t6 : voltage of VDD must decay smoothly after power-off. (customer system decide this value) (3) When CMOS Interface signal is N.C. (no connection), opened in Transmitted end, t8 timing spec can be

negligible.

3.7 Backlight Specification

The backlight unit contains 8pcs LED lightbar.

3.7.1 Electrical specification

Item Symbol Condition

P650HVN02.5 Product Specification

Rev. 0.0

Spec

Unit Note

Min Typ Max

1

2

3

4

Input Voltage VDDB - 22.8

Input Current I

Input Power P

Inrush Current I

VDDB=24V

DDB

VDDB=24V

DDB

VDDB=24V

RUSH

Hi 2 - 5.5 -

5 Control signal voltage

V

Signal

VDDB=24V

Low

6 Control signal current

External PWM Duty ratio

7

8

(input duty ratio)

External PWM

Frequency

I

VDDB=24V

Signal

D_EPWM VDDB=24V

F_EPWM VDDB=24V 110 180 240 Hz 4,5

HI Open Collector VDC 6

9

DET status signal DET

VDDB=24V

Lo

10

Input Impedance Rin VDDB=24V 300 Kohm -

Note 1: Dimming ratio= 100%,（Ta=25±5℃, Turn on for 45minutes）

--

206.4 216.1

--

24 25.2

8.6 9

VDC -

ADC 1

W 1

- 16 Apeak 2

VDC

0 - 0.8

3

- - 1.5 mA -

0 - 100 % 4,5

0 - 0.8 VDC 6

Note 2: MAX input current at all operating mode, measurement condition Rising time = 20ms (VDDB: 10%~90%)

Note 3: When BLU off ( VDDB = 24V , VBLON = 0V) , IDDB (max) = 0.1A

Note 4: Less than 5% dimming control is functional well and no backlight shutdown happened

Note 5: D_EPWM and F_EPWM are available only at 2D mode

Note 6: Normal: 0~0.8V ; Abnormal : Open collector

3.7.2 Input Pin Assignment

14pin pin assignment

Connector: CI0114M1HR0-NH(CviLux) or equivalent

P650HVN02.5 Product Specification

Rev. 0.0

Pin NO. Symbol

1 VDDB Operating Voltage Supply, +24V DC regulated 2 VDDB Operating Voltage Supply, +24V DC regulated 3 VDDB Operating Voltage Supply, +24V DC regulated 4 VDDB Operating Voltage Supply, +24V DC regulated 5 VDDB Operating Voltage Supply, +24V DC regulated 6 BLGND Ground and Current Return 7 BLGND Ground and Current Return 8 BLGND Ground and Current Return 9 BLGND Ground and Current Return

10 BLGND Ground and Current Return

11 DET

12 VBLON

13 NC NC

14 PDIM (*) External PWM (5%~100% Duty, open for 100%)

12pin pin assignment

Pin Configuration (function)

BLU status detection:

Normal : 0~0.8V ; Abnormal : Open collector

(Recommend Pull high R > 10K, VDD = 3.3V)

BL On-Off control

High/Open (2.0V~5.5V) for BL On,

Low (0~0.8V/GND) for BL off

Connector: CI0112M1HR0-NH(CviLux) or equivalent

Pin NO. Symbol

1 VDDB Operating Voltage Supply, +24V DC regulated 2 VDDB Operating Voltage Supply, +24V DC regulated 3 VDDB Operating Voltage Supply, +24V DC regulated 4 VDDB Operating Voltage Supply, +24V DC regulated 5 VDDB Operating Voltage Supply, +24V DC regulated 6 BLGND Ground and Current Return 7 BLGND Ground and Current Return 8 BLGND Ground and Current Return 9 BLGND Ground and Current Return

10 BLGND Ground and Current Return

11 NC 12 NC NC

Pin Configuration (function)

NC

(Note*) If External PWM function is less than 5% dimming ratio. Judge condition as below:

(1) Backlight module must be lighted ON normally. (2) All protection function must work normally. (3) Uniformity and flicker could NOT be guaranteed

3.7.3 Power Sequence for Backlight

24V(typ.)

T3

Power Input for BLU

(VDDB)

Valid Dimming

Control Signal

(V_IPWM,V_EPWM)

90% 90%

10%

T1 T2

P650HVN02.5 Product Specification

Rev. 0.0

10%

T7

T5

T4

T6

T7

BLU On/Off Enable

(VBLON)

Dip condition for LED Backlight

Power Input for BLU

(VDDB)

VDDB(typ.)*0.8

T8

Parameter

Min Typ Max

T1 20 - - ms *1

T2 500 - - ms

T3 250 - - ms

T4 0 - - ms

T5 1 - - ms

T6 - - ms

T7 500 - - ms

T8 - - 10 ms

Value

Units

Note: 1. T1 describes rising time of 0V to 24V and this parameter does not applied at restarting time. Even though T1 is over the specified value, there is no problem if I2t spec of fuse is satisfied.

P650HVN02.5 Product Specification

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4. Optical Specification

Optical characteristics are determined after the unit has been ‘ON’ and stable for approximately 45 minutes in a

dark environment at 25°C while panel is placed in the default position. The default position is T-con side as the top

side of panel. The value specified is at an approximate distance 50cm from the LCD surface at a viewing angle of φ

and θ equal to 0°.

Fig.1 presents additional information concerning the measurement equipment and method.

SR3 or equivalent

Parameter Symbol

Min. Typ. Max

Contrast Ratio CR 3200 4000 -- 1

Surface Luminance (White) LWH 560 700 -- cd/m2 2

Luminance Variation δ

Response Time (G to G) Tγ -- 6.5 -- Ms 4

Color Gamut NTSC 72 %

Color Coordinates

Red RX 0.630

RY 0.330

Green GX 0.320

GY 0.620

Blue BX 0.150

BY 0.040

White WX 0.280

WY

WHITE(9P)

-- -- 1.33 3

Typ.-0.03

Values

0.290

Unit Notes

Typ.+0.03

Viewing Angle 5

x axis, right(φ=0°) θr -- 89 -- degree

x axis, left(φ=180°) θl -- 89 -- degree

y axis, up(φ=90°) θu -- 89 -- degree

y axis, down (φ=270°) θ

-- 89 -- degree

d

2 3

7

P650HVN02.5 Product Specification

Rev. 0.0

Note:

1. Contrast Ratio (CR) is defined mathematically as:

Surface Luminance of

Contrast Ratio=

Surface Luminance of

2. Surface luminance is luminance value at point 5 across the LCD surface 50cm from the surface with all pixels

displaying white. From more information see FIG 2. When lamp current IH = 11mA. LWH=Lon5 where Lon5 is

the luminance with all pixels displaying white at center 5 location.

3. The variation in surface luminance, δWHITE is defined (center of Screen) as:

L

on5

L

off5

δ

WHITE(9P)

= Maximum(L

on1

, L

on2

,…,L

)/ Minimum(L

on9

on1

, L

on2

,…L

on9

)

4. Response time Tγ is the average time required for display transition by switching the input signal for five

luminance ratio (0%,25%,50%,75%,100% brightness matrix) and is based on Fv=60Hz to optimize.

Target Measured

Response Time

0%

25%

Start

50%

75%

100%

Tγ is determined by 10% to 90% brightness difference of rising or falling period. (As illustrated)

5. Viewing angle is the angle at which the contrast ratio is greater than 10. The angles are determined for the

horizontal or x axis and the vertical or y axis with respect to the z axis which is normal to the LCD surface. For

more information see FIG4.

FIG. 2 Luminance

0% 25% 50% 75% 100%

0% to 25% 0% to 50% 0% to 75% 0% to 100%

25% to 0% 25% to 50% 25% to 75% 25% to 100%

50% to 0% 50% to 25%

75% to 0% 75% to 25% 75% to 50%

100% to 0% 100% to 25% 100% to 50% 100% to 75%

50% to 75% 50% to 100%

75% to 100%

V

H/2

H/6

1

H

V/2 V/6

P650HVN02.5 Product Specification

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FIG.3 Response Time

The response time is defined as the following figure and shall be measured by switching the input signal for “any level of gray(bright) “ and “any level of gray(dark)”.

Any level of gray (Bright) Any level of gray (Dark) Any level of gray (Bright)

0% , 25%, 50% , 75%, 1 00%

Photodetector

Output

FIG.4 Viewing Angle

T

γγγγ

(F)

0% , 25%, 50% , 75%, 1 00%

0% , 25%, 50% , 75%, 100%

Time

T

(R)

γγγγ

P650HVN02.5 Product Specification

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5. Mechanical Characteristics

The contents provide general mechanical characteristics for the model P650HVN02.5. In addition the figures in

the next page are detailed mechanical drawing of the LCD.

Horizontal (typ.) 1508.0mm

Outline Dimension

Bezel Opening Area

Active Display Area

Weight 13500g

Surface Treatment AG, 3H

5.1 Placement suggestions:

1. Landscape Mode: The default placement is T-Con Side on the upper side and the image is shown

upright via viewing from the front.

2. Portrait Mode: The default placement is that T-Con side has to be placed on the right side via viewing

from the front.

Vertical (typ.) 878.0mm

Depth (typ.) 12.8mm (thinnest)

Horizontal (typ.) 1440.6 mm

Vertical (typ.) 814.6 mm

Horizontal 1428.48 mm

Vertical 803.52 mm

Landscape (

Front view

) Portrait (

Front view

)

-

T-Con

A

Front View

P650HVN02.5 Product Specification

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Back View

P650HVN02.5 Product Specification

Rev. 0.0

6. Reliability Test Items

P650HVN02.5 Product Specification

Rev. 0.0

1 High temperature storage test 3

2 Low temperature storage test 3

3 High temperature operation test 3

4 Low temperature operation test 3

5 Vibration test (With carton)

6 Drop test (With carton)

Test Item Q’ty Condition

1

(PKG)

1

(PKG)

60℃, 500hrs

-20℃, 500hrs

50℃, 500hrs

-5℃, 500hrs

Random wave (1.05G RMS, 10-200Hz)

10mins/ Per each X,Y,Z axes

Height: 25.4 cm

Direction: Only bottom flat twice

(ASTMD4169-I)

7. International Standard

7.1 Safety

(1) UL 60950-1; Standard for Safety of Information Technology Equipment Including electrical Business

Equipment.

(2) IEC 60950-1 : 2001; Standard for Safety of International Electrotechnical Commission

(3) EN 60950 : 2001+A11; European Committee for Electrotechnical Standardization (CENELEC),

EUROPEAN STANDARD for Safety of Information Technology Equipment Including Electrical

Business Equipment.

7.2 EMC

(1) ANSI C63.4 “Methods of Measurement of Radio-Noise Emissions from Low-Voltage Electrical and

Electrical Equipment in the Range of 9kHz to 40GHz. “American National standards Institute(ANSI),

1992

P650HVN02.5 Product Specification

Rev. 0.0

(2) C.I.S.P.R “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” International Special committee on Radio Interference.

(3) EN 55022 “Limits and Methods of Measurement of Radio Interface Characteristics of Information

Technology Equipment.” European Committee for Electrotechnical Standardization. (CENELEC),

1998

QTY :

4

Manufactured

XX/XX

MADE IN

XXXXX

8. Packing

8-1 DEFINITION OF LABEL:

A. Panel Label:

*xxxxxxxxxxxx-xxxx*

P650HVN02.5 Product Specification

Rev. 0.0

Panel Unique ID

AUO Internal Use

XXXXX Model NO: P650HVN02.5 XXXXXXX

Year

Week

AUO Internal Use

Green mark description

AU Optronics

Factory Location AUO Internal Use

(1) For Pb Free Product, AUO will add for identification.

(2) For RoHs compatible products, AUO will add RoHS for identification.

Note: The green Mark will be present only when the green documents have been ready by AUO internal green

team. (definition of green design follows the AUO green design checklist.)

B. Carton Label: (TBD)

P650HVN02.5

97.65P02.5xx

X

1pcs Module

4pcs Modules

1pcs Module/ESD Bag

Cushion top

Module

4 pcs / 1 carton

”

H ”

Cushion down

Cushion set

8-2 PACKING METHODS:

P650HVN02.5 Product Specification

Rev. 0.0

8-3 Pallet and Shipment Information

P650HVN02.5 Product Specification

Rev. 0.0

Specification

Item

1 Packing Box 4pcs/box 1605(L)mm*375(W)mm*1025(H)mm 138

2 Pallet 1 1660(L)mm*1150(W)mm*138(H)mm 20

3 Boxes per Pallet 3 boxes/Pallet (By Air) ; 3 Boxes/Pallet (By Sea)

4 Panels per Pallet 12 pcs/pallet(By Air) ; 12 pcs/Pallet (By Sea)

after packing

Qty. Dimension Weight (kg)

12 (by Air) 1660(L)mm*1150(W)mm*1173(H)mm 434(by Air)

24 (by Sea) 1660(L)mm*1150(W)mm*2346(H)mm 868(by Sea) 40ft HQ

Packing

Remark

5 Pallet

9. PRECAUTIONS

Please pay attention to the followings when you use this TFT LCD module.

9-1 MOUNTING PRECAUTIONS

(1) You must mount a module using holes arranged in four corners or four sides.

(2) You should consider the mounting structure so that uneven force (ex. twisted stress) is not applied

to module. And the case on which a module is mounted should have sufficient strength so that

external force is not transmitted directly to the module.

(3) Please attach the surface transparent protective plate to the surface in order to protect the polarizer.

Transparent protective plate should have sufficient strength in order to the resist external force.

(4) You should adopt radiation structure to satisfy the temperature specification.

(5) Acetic acid type and chlorine type materials for the cover case are not desirable because the former

P650HVN02.5 Product Specification

Rev. 0.0

generates corrosive gas of attacking the polarizer at high temperature and the latter cause circuit

broken by electro-chemical reaction.

(6) Do not touch, push or rub the exposed polarizer with glass, tweezers or anything harder than HB

pencil lead. And please do not rub with dust clothes with chemical treatment. Do not touch the

surface of polarizer for bare hand or greasy cloth. (Some cosmetics are detrimental to the polarizer.)

(7) When the surface becomes dusty, please wipe gently with absorbent cotton or other soft materials

like chamois soaks with petroleum benzene. Normal-hexane is recommended for cleaning the

adhesives used to attach front/ rear polarizer. Do not use acetone, toluene and alcohol because

they cause chemical damage to the polarizer.

(8) Wipe off saliva or water drops as soon as possible. Their long time contact with polarizer causes

deformations and color fading.

(9) Do not open the case because inside circuits do not have sufficient strength.

9-2 OPERATING PRECAUTIONS

(1) The device listed in the product specification sheets was designed and manufactured for public

information display application.

(2) The spike noise causes the mis-operation of circuits. It should be lower than following voltage:

V=±200mV(Over and under shoot voltage)

(3) Response time depends on the temperature. (In lower temperature, it becomes longer..)

(4) Brightness of LED depends on the temperature. (In lower temperature, it becomes lower.) And in

lower temperature, response time (required time that brightness is stable after turned on) becomes

longer.

(5) Be careful for condensation at sudden temperature change. Condensation makes damage to

polarizer or electrical contacted parts. And after fading condensation, smear or spot will occur.

(6) When fixed patterns are displayed for a long time, remnant image is likely to occur.

(7) Module has high frequency circuits. Sufficient suppression to the electromagnetic interference shall

be done by system manufacturers. Grounding and shielding methods may be important to minimize

the interface.

9-3 ELECTROSTATIC DISCHARGE CONTROL

Since a module is composed of electronic circuits, it is not strong to electrostatic discharge. Make certain

that treatment persons are connected to ground through wristband etc. And don’t touch interface pin

directly.

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

Strong light exposure causes degradation of polarizer and color filter.

9-5 STORAGE

When storing modules as spares for a long time, the following precautions are necessary.

(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent light. Keep the

P650HVN02.5 Product Specification

Rev. 0.0

temperature between 5 and 35 at normal humidity.

(2) The polarizer surface should not come in contact with any other object. It is recommended that they

be stored in the container in which they were shipped.

℃ ℃

9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

(1) The protection film is attached to the bezel with a small masking tape. When the protection film is

peeled off, static electricity is generated between the film and polarizer. This should be peeled off

slowly and carefully by people who are electrically grounded and with well ion-blown equipment or

in such a condition, etc.

(2) When the module with protection film attached is stored for a long time, sometimes there remains a

very small amount of glue still on the bezel after the protection film is peeled off.

(3) You can remove the glue easily. When the glue remains on the bezel or its vestige is recognized,

please wipe them off with absorbent cotton waste or other soft material like chamois soaked with

normal-hexane.

9-7 OPERATING CONDITION in PID APPLICATION

(1) If the continuous static display is required, periodically inserting a motion picture is strongly

recommended.

(2) Recommend to periodically change the background color and background image.

(3) Recommend not to continuously operate over 18 hours a day.

(4) Recommend to adopt one of the following actions after long time display.

I. Running the screen saver (motion picture or black pattern)

II. Power off the system for a while

(5) Try not to run the LCD in a closed environment. Suitable venting on the system cover would be

helpful for cooling.

(6) It is better to adapt active cooling with fans for long time displaying, especially for high luminance

LCD model.