Global LCD Panel Exchange Center
www.panelook.com
Document Version: 8
Date: 2005/3/4
Product Functional Specification
15 inch XGA Color TFT LCD Module
Model Name : B150XG02 V.3
( ) Preliminary Specification
(
Note: This Specification is subject to change without notice.
) Final Specification
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
1/1
www.panelook.com
Global LCD Panel Exchange Center
I. Contents
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
5.0 Signal Interface
5.1 Connectors
5.2 Signal Pin
www.panelook.com
5.3 Signal Description
5.4 Signal Electrical Characteristics
5.5 Signal for Lamp Connector
5.6 Inverter Characteristic
6.0 Pixel Format Image
7.0 Parameter Guide Line for CCFL Inverter
8.0 Interface Timings
8.1 Timing Characteristics
8.2 Timing Definition
9.0 Power Consumption
10.0 Power ON/OFF Sequence
11.0 Mechanical Characteristics
12.0 EDID Table
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
2/2
www.panelook.com
Global LCD Panel Exchange Center
II Record of Revision
www.panelook.com
Version and
Date
0.1. 2004/8/16 All First Edition for Customer All
0.2. 2004/10/13 15 Update inverter spec.
0.2. 2004/10/13 6 Luminance average (5pts)
0.2. 2004/10/13 6 Add luminance min (5pts)
0.3. 2005/1/17 15 Update inverter output current
0.3. 2005/1/17 16 Min. ICFL 3.0mA Min. ICFL 2.0mA
0.4 2005/2/25 6 -20 to +60 -25 to +65 Storage
0.4 2005/2/25 8 -20 to +60 -25 to +65 Storage
0.4 2005/2/25 9 N/A 150 min
0.4 2005/2/25 11 LVDS differential data input
0.4 2005/2/25 15 549 (min), 610 (typ),
0.4 2005/2/25 16 N/A 150 min White
0.4 2005/2/25 17 With Hsync, Hsw, Hbp,Hfp,
0.4 2005/2/25 18 With Hsync & Vsync Deleted Hsync & Vsync Timing
0.4 2005/2/25 18 With VDDrp & VDDns Deleted VDDrp & VDDns Power
0.4 2005/3/1 23 Add EDID Table
Page Old description New Description Remark
170nit
(Blue2-Blue5, Hsync, Vsync,
DSPTMG)
671(max)
Vw, Vfp and Vbp
Luminance average (5pts)
180nit
150nit
LVDS differential data input
(Blue2-Blue5, DSPTMG)
585 (min), 650 (typ), 715(max) Output voltage
Deleted Hsync, Hsw, Hbp,Hfp,
Vw, Vfp and Vbp
Temperature
Temperature
White
Luminance
(CCFL 6.0 mA)
Signal
Description
Luminance
5 points
average
Timing
Characteristics
Definition
Consumption
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
3/3
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
1.0 Handing Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration or
spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard
surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure
human earth when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) In case if a Module has to be put back into the packing container slot after once it was
taken out from the container, do not press the center of the CCFL Reflector edge.
Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT
Module may be damaged.
10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor
tilt the Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure (Notebook PC Bezel, for
example), do not twist nor bend the TFT Module even momentary. At designing the
enclosure, it should be taken into consideration that no bending/twisting forces are
applied to the TFT Module from outside. Otherwise the TFT Module may be damaged.
12) Cold cathode fluorescent lamp in LCD contains a small amount of mercury. Please follow
local ordinances or regulations for disposal.
13) Small amount of materials having no flammability grade is used in the LCD module. The
LCD module should be supplied by power complied with requirements of Limited Power
Source(2.11, IEC60950 or UL1950), or be applied exemption.
14) The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit(2.4,
IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
4/4
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
2.0 General Description
This specification applies to the 15.0 inch Color TFT/LCD Module B150XG02 V.3.
This module is designed for a display unit of notebook style personal computer.
The screen format is intended to support the XGA (1024(H) x 768(V)) screen and 262k
colors (RGB 6-bits data driver).
All input signals are LVDS interface compatible.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
5/5
www.panelook.com
Global LCD Panel Exchange Center
Storage (Shipping)
[oC]
www.panelook.com
2.1 Display Characteristics
The following items are characteristics summary on the table under 25 к condition:
ITEMS Unit SPECIFICATIONS
Screen Diagonal [mm] 381
Active Area [mm] 304.1 X 228.1
Pixels H x V 1024(x3) x 768
Pixel Pitch [mm] 0.297X0.297
Pixel Arrangement R.G.B. Vertical Stripe
Display Mode Normally White
Typical White Luminance
(ICFL=6.0mA)
[cd/m2] 180 (5 point average)
150 (5 point min.)
Luminance Uniformity 1.25 max. (5 pts)
1.65 max. (13pts)
Contrast Ratio 300 typ.
Optical Rise Time/Fall Time [msec] 16/9
Nominal Input Voltage VDD [Volt] +3.3 typ.
Typical Power Consumption
(VDD line + VCFL line)
[Watt]
6.3W Max (w/o Inverter, All black
pattern)@LCM circuit 2.1 (Max.),B/L
input 4.2 (Max.)
Weight (Panel+Inverter) [Grams] 600g max.
Physical Size [mm] 317.3 x 242.0 x 6.5 max.
Electrical Interface 1 channel LVDS
Support Color Native 262K colors ( RGB 6-bit data
driver )
Temperature Range
Operating
[oC]
0 to +50
-25 to +65
Surface Treatment 3H min
Color Gamut NTSC 42% min
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
6/6
www.panelook.com
Global LCD Panel Exchange Center
Y
ype SM0
2.2 Functional Block Diagram
The following diagram shows the functional block of the 15.0 inches Color TFT/LCD
Module:
www.panelook.com
LCD DRIVE
CARD
6bit color data
for R/G/B
DSPTMG
Vsync
Hsync
(3 pairs LVDS)
DTCLK
(1 pair LVDS)
VDD
GND
LCD
Controller
DC-DC
Converter
Ref circuit
LCD Connector
JAE JAE FI-XB30SL-HF10
Mating Type JAE FI-S30M
Backlight Unit
TFT ARRAY/CELL
1024(R/G/B) x 3
-Driver
X-Driver
JST BHSR-02VS-1
Mating T
Lamp Connector
2B-BHSS-1
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
7/7
www.panelook.com
Global LCD Panel Exchange Center
3.0 Absolute Maximum Ratings
www.panelook.com
Absolute maximum ratings of the module is as following:
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 +4.0 [Volt]
Input Voltage of Signal Vin -0.3 VDD+0.3 [Volt]
LVDS Input Voltage V
CCFL Current ICFL - 7 [mA]
LVDS in
-0.3 +2.6 [Volt]
rms
CCFL Ignition Voltage Vs - 1150 Vrms
Operating Temperature TOP 0 +50 [oC] Note 1
Operating Humidity HOP 8 95 [%RH] Note 1
Storage Temperature TST -25 +65 [oC] Note 1
Storage Humidity HST 5 95 [%RH] Note 1
Vibration 1.5 10-500
G Hz 2hr/axis, X,Y,Z
(random)
Shock 220 , 2 G ms Half sine wave
Note 1 : Maximum Wet-Bulb should be 39к and No condensation.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
8/8
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25к
condition:
Item Conditions Typ. Note
Viewing Angle
K: Contrast Ratio
Contrast ratio
Luminance
[degree]
[degree]
[degree]
[degree]
Horizontal (Right)
K = 10 (Left)
Vertical (Upper)
K = 10 (Lower)
300 typ. 200 min.
1.25 max. (5 pts)
Uniformity
Response Time [msec] Rising
(Room Temp.) [msec] Falling
Color Red x
Chromaticity Red
y 0.340+-0.02
Coordinates (CIE) Green x
Green
Blue x
y 0.550+-0.02
40 min.
40 min.
10 min.
30 min.
1.65 max. (13pts)
16 typ. 24 Max.
9 typ. 11Max.
0.580+-0.02
0.310+-0.02
0.155+-0.02
——
—
—
White Luminance
[cd/m2] 180 typ. (5 points
Blue
White x
White
(CCFL 6.0 mA)
y 0.155+-0.02
0.313+-0.02
y 0.329+-0.02
150 min
average)
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
9/9
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following
components.
Connector Name / Designation For Signal Connector
Manufacturer JAE or compatible
Type / Part Number JAE FI-XB30SL-HF10
Mating Housing/Part Number FI-X30M, FI-X30C or FI-X30H
Mating Contact/Part Number FI-C3-A1
www.panelook.com
Connector Name / Designation For Lamp Connector
Manufacturer JST
Type / Part Number BHSR-02VS-1
Mating Type / Part Number SM02B-BHSS-1-TB
5.2 Signal Pin
Pin# Signal Name Pin# Signal Name
1 GND 2 VDD
3 VDD 4 VEDID
5 BIST Test 6 CLKEDID
7 DATAEDID 8 RxIN0-
9 RxIN0+ 10 GND
11 RxlN1- 12 RxlN1+
13 GND 14 RxIN215 RxIN2+ 16 GND
17 RxCLKIN- 18 RxCLKIN+
19 GND 20 NC
21 NC 22 NC
23 NC 24 NC
25 NC 26 NC
27 NC 28 NC
29 NC 30 NC
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
10/10
www.panelook.com
Global LCD Panel Exchange Center
5.3 Signal Description
The module using a LVDS receiver. LVDS is a differential signal technology for LCD interface
and high speed data transfer device. Transmitter shall be SN75LVDS84 (negative edge
sampling) or compatible.
Signal Name Description
RxIN0-, RxIN0+ LVDS differential data input(Red0-Red5, Green0)
RxIN1-, RxIN1+ LVDS differential data input(Green1-Green5, Blue0-Blue1)
RxIN2-, RxIN2+ LVDS differential data input(Blue2-Blue5, DSPTMG)
RxCLKIN-, RxCLKIN0+ LVDS differential clock input
www.panelook.com
VDD +3.3V Power Supply
GND Ground
Note: Input signals shall be low or Hi-Z state when VDD is off.
Internal circuit of LVDS inputs are as following.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
11/11
www.panelook.com
Global LCD Panel Exchange Center
Signal Input
Pin No.
www.panelook.com
SN75LVDS86 or Compatible
8
9
11
12
14
15
17
18
RxIN0-
RxIN0+
RxIN1-
RxIN1+
RxIN2-
RxIN2+
RxCLKIN-
RxCLKIN+
R
R
R
R
The module uses a 100ohm resistor between positive and negative data lines of
each receiver input
Signal Name Description
RED5
RED4
RED3
RED2
RED1
RED0
Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
Red-pixel Data
Each red pixel's brightness data consists of
these 6 bits pixel data.
Red-pixel Data
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
12/12
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
GREEN 5
GREEN 4
GREEN 3
GREEN 2
GREEN 1
GREEN 0
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
Green-pixel Data
Each green pixel's brightness data consists of
these 6 bits pixel data.
Green-pixel Data
BLUE 5
BLUE 4
BLUE 3
BLUE 2
BLUE 1
BLUE 0
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data
Each blue pixel's brightness data consists of
these 6 bits pixel data.
Blue-pixel Data
DTCLK Data Clock The typical frequency is 65.0 MHZ.. The signal
is used to strobe the pixel data and DSPTMG
signals. All pixel data shall be valid at the falling
edge when the DSPTMG signal is high.
DSPTMG Display Timing This signal is strobed at the falling edge of
-DTCLK. When the signal is high, the pixel data
shall be valid to be displayed.
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
5.4 Signal Electrical Characteristics
Input signals shall be low or Hi-Z state when VDD is off.
It is recommended to refer the specifications of SN75LVDS86DGG(Texas Instruments) in
detail.
Signal electrical characteristics are as follows;
Symbol Parameter Condition Min Max Unit
VTH
VTL
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
Differential Input High
Threshold
Differential Input Low
Threshold
Vcm=+1.2V
Vcm=+1.2V
-100
100
[mV]
[mV]
13/13
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
g
p
p
LVDS Macro AC characteristics are as follows:
Min. Max.
Clock Frequency (T) 50MHZ 68MHZ
Data Setup Time (Tsu) 600ps
Data Hold Time (Thd) 600ps
Input Clock
Input Data
www.panelook.com
T
5.5 Signal for Lamp connector
Pin #
1
2
Lam
Lam
nal Name
Si
High Voltage
Low Voltage
ThdTsu
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
14/14
www.panelook.com
Global LCD Panel Exchange Center
g
www.panelook.com
5.6 Inverter Characteristic
. Item Symbol Condition Min. Typ. Max. Uint
1 Input Voltage Vin 7.5 14.4 21 V
2 Input Current Iin Vin=7.5V,SMData=00H 590 650 710 mA
3 Input Power Pin Vin=7.5V,SMData=00H 5.25 W
Input Signal Level for
4
5
5VSUS,5VALW
Backlight ON FPVEE=Hi 2.0 - 5.25 V
ON/OFF Control OFF FPVEE=Lo -0.3 - 0.8 V
4.85 5 5.2 V
6
7 Output Voltage Vout SMData=00H 585 650 715 V(rms)
8 Output Current
9 Frequency Freq Vin=7.5~21V 45 55 65 KHz
10 Output Power Pout Vin=21V,SMData=00H --- 4.4 4.6 W
11 Open Lamp Voltage Vopen No Load 1400 - 1800 V(rms)
12 Striking Time Ts Vin=7.5V~21V 0.6 1 1.4 Sec
13 Efficiency η
Current Control)
SMData Control by SMBus FFH - 00H -
Duty cycle
Iout (Max)
Vin(7.5V~21V)SMData=FFH Ta=25
к, after running 30 min.
Vin(7.5V~21V)SMData=00H Ta=25
к, after running 30 min.
Vin=7.5V, Iout=Max.
Load=110Kohm//15 p farad
6 10 14
5.7 6.0 6.3 mA(rms)
80 --- --- %
% duty
cycle
htness Adjust (Lamp
Bri
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
15/15
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
6.0 Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format.
7.0 Parameter guide line for CCFL Inverter
Parameter Min DP-1 Max Units Condition
White Luminance
5 points average
150
180
⎯
[cd/m2 ]
CCFL current(ICFL) 2.0 6.0 7.0 [mA]
rms
CCFL Frequency(FCFL) 40 50 60 [KHz]
(Ta=25к)
(Ta=25к)
Note 2
(Ta=25к)
Note 3
CCFL Ignition Voltage(Vs)
CCFL Voltage (Reference)
⎯
(VCFL)
CCFL Power consumption
⎯
(PCFL)
⎯
700
4.6
1,150 [Volt]
rms
⎯
[Volt]
rms
⎯
[Watt]
(Ta= 0к)
Note 4
(Ta=25к)
Note 5
(Ta=25к)
Note 5
Note 1: DP-1 are AUO recommended Design Points.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
16/16
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
*1 All of characteristics listed are measured under the condition using the AUO Test inverter.
*2 In case of using an inverter other than listed, it is recommended to check the inverter
carefully. Sometimes, interfering noise stripes appear on the screen, and substandard
luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit ver carefully. Impedance of
CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged.
*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is
recommended to keep on applying kick-off voltage for 1 [Sec] until discharge.
*5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise
stripes on the screen.
*6 Reducing CFL current increases CFL discharge voltage and generally increases CFL
discharge frequency. So all the parameters of an inverter should be carefully designed so as
not to produce too much leakage current from high-voltage output of the inverter.
Note 2: It should be emplyed the inverter which has “Duty Dimming”, if ICFL is less than 4mA.
Note 3: CFL discharge frequency should
be carefully determined to avoid interference between inverter and TFT LCD.
Note 4: CFL inverter should be able to give out a power that has a generating capacity of over
1,400 voltage. Lamp units need 1,400 voltage minimum for ignition.
Note 5: Calculator value for reference (ICFL×VCFL=PCFL)
8.0 Interface Timings
Basically, interface timings should match the VESA 1024x768 /60Hz (VG901101) manufacturing
guide line timing.
8.1 Timing Characteristics
Symbol Description Min Typ Max Unit
fdck DTCLK Frequency 50 65.00 68 [MHz]
tck DTCLK cycle time
tx X total time 1206 1344 1648 [tck]
tacx X active time
tbkx X blank time 90 320
ty Y total time 771 806 895 [tx]
Vsync Frame rate (55) 60 61 [Hz]
tacy Y active time
15.38
1024
768
[nsec]
[tck]
[tck]
[tx]
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
17/17
www.panelook.com
Global LCD Panel Exchange Center
8.2 Timing Definition
9.0 Power Consumption
www.panelook.com
Input power specifications are as follows;
Symbol Parameter Min Typ Max Units Condition
VDD Logic/LCD Drive
3.0 3.3 3.6 [Volt] Load Capacitance 20uF
Voltage
PDD VDD Power
PDD Max VDD Power max
IDD IDD Current
IDD Max IDD Current max
1.26 [Watt] All Black Pattern
380 mA
2.1 [Watt] Max Pattern Note
All Black Pattern
580 mA
Max Pattern Note
Note : VDD=3.3V
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
18/18
www.panelook.com
Global LCD Panel Exchange Center
n
www.panelook.com
10.0 Power ON/OFF Sequence
VDD power and lamp on/off sequence is as follows. Interface signals are also shown in
the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
0-50 ms
min
90%
10%
10%
90%
VDD
0 V
Signals
0 V
Lamp O
0 V
10%
10ms max.
0-50 ms
10%
200ms
200ms
mi n
10%
400ms min.
10%
10%
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
19/19
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
11.0 Mechanical Characteristics
www.panelook.com
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
20/20
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
21/21
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
Fig. Screw hole depth and suggested screw penetration
Suggested torque is 2.0+/- 0.2kgf-cm, also shown in the module drawing.
Fig. Gap between films and glass
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
22/22
www.panelook.com
Global LCD Panel Exchange Center
12.0 EDID Table
ʳ
Header
Vendor / Product
Byte Value Value
(hex)
0 Header
1 Header
2 Header
3 Header
4 Header
5 Header
6 Header
7 Header
8 EISA manufacture code = 3 Character ID
9 EISA manufacture code (Compressed ASCII)
0A Panel Supplier Reserved – Product Code
0B Panel Supplier Reserved – Product Code
0C LCD module Serial No - Preferred but Optional (“0” if not used)
0D LCD module Serial No - Preferred but Optional (“0” if not used)
0E LCD module Serial No - Preferred but Optional (“0” if not used)
EDID Version
0F LCD module Serial No - Preferred but Optional (“0” if not used)
10 Week of manufacture
11 Year of manufacture
12 EDID structure version # = 1
13 EDID revision # = 3
www.panelook.com
Field Name and Comments
(hex) (binary)
00
FF
FF
FF
FF
FF
FF
00
06
AF
07
0F
01
01
01
01
01
0E
01
03
0
11111111
11111111
11111111
11111111
11111111
11111111
0
110
10101111
111
1111
1
1
1
1
1
1110
1
11
Display
Parameters
Panel Color
Coordinates
Timings
Established
Ti
rd
da
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
14 Video I/P definition = Digital I/P (80h)
15 Max H image size = (Rounded to cm)
16 Max V image size = (Rounded to cm)
Display gamma = (gamma ×100)-100 = Example: ( 2.2100 ) – 100 = 120
17
18 Feature support ( no DPMS, Active off, RGB, timing BLK 1)
19 Red/Green Low bit (RxRy/GxGy)
1A Blue/White Low bit (BxBy/WxWy)
1B Red X Rx = 0.xxx
1C Red Y Ry = 0.xxx
1D Green X Gx = 0.xxx
1E Green Y Gy = 0.xxx
1F Blue X Bx = 0.xxx
20 Blue Y By = 0.xxx
21 White X Wx = 0.xxx
22 White Y Wy = 0.xxx
23 Established timings 1 (00h if not used)
24 Established timings 2 (00h if not used)
25 Manufacturer’s timings (00h if not used)
26 Standard timing ID1 (01h if not used)
mi
80
1E
17
78
0A
87
F5
94
57
4F
8C
27
27
50
54
00
00
00
01
10000000
11110
10111
1111000
1010
10000111
11110101
10010100
1010111
1001111
10001100
100111
100111
1010000
1010100
0
0
0
1
23/23
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
Timing Descripter #1
Timing Descripter #2
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
27 Standard timing ID1 (01h if not used)
28 Standard timing ID2 (01h if not used)
29 Standard timing ID2 (01h if not used)
2A Standard timing ID3 (01h if not used)
2B Standard timing ID3 (01h if not used)
2C Standard timing ID4 (01h if not used)
2D Standard timing ID4 (01h if not used)
2E Standard timing ID5 (01h if not used)
2F Standard timing ID5 (01h if not used)
30 Standard timing ID6 (01h if not used)
31 Standard timing ID6 (01h if not used)
32 Standard timing ID7 (01h if not used)
33 Standard timing ID7 (01h if not used)
34 Standard timing ID8 (01h if not used)
35 Standard timing ID8 (01h if not used)
36 Pixel Clock/10,000 (LSB)
37 Pixel Clock/10,000 (MSB)
38 Horizontal Active = xxxx pixels (lower 8 bits)
39 Horizontal Blanking (Thbp) = xxxx pixels (lower 8 bits)
3A Horizontal Active/Horizontal blanking (Thbp) (upper4:4 bits)
3B Vertical Active = xxxx lines
3C Vertical Blanking (Tvbp) = xxxx lines (DE Blanking typ. for DE only panels)
3D Vertical Active : Vertical Blanking (Tvbp) (upper4:4 bits)
3E Horizontal Sync, Offset (Thfp) = xxxx pixels
3F Horizontal Sync, Pulse Width = xxxx pixels
40 Vertical Sync, Offset (Tvfp) = xx lines Sync Width = xx lines
41 Horizontal Vertical Sync Offset/Width upper 2 bits
42 Horizontal Image Size =xxx mm
43 Vertical image Size = xxx mm
44 Horizontal Image Size / Vertical image size
45 Horizontal Border = 0 (Zero for Notebook LCD)
46 Vertical Border = 0 (Zero for Notebook LCD)
Non-interlaced, Normal, no stereo, Separate sync, H/V pol Negatives, DE only
47
note: LSB is set to “1” if panel is DE-timing only. H/V can be ignored. 18
48 Pixel Clock/10,000 (LSB)
49 Pixel Clock/10,000 (MSB)
4A Horizontal Active = xxxx pixels (lower 8 bits)
4B Horizontal Blanking (Thbp) = xxxx pixels (lower 8 bits)
4C Horizontal Active/Horizontal blanking (Thbp) (upper4:4 bits)
4D Vertical Active = xxxx lines
4E Vertical Blanking (Tvbp) = xxxx lines (DE Blanking typ. for DE only panels)
4F Vertical Active : Vertical Blanking (Tvbp) (upper4:4 bits)
50 Horizontal Sync, Offset (Thfp) = xxxx pixels
51 Horizontal Sync, Pulse Width = xxxx pixels
52 Vertical Sync, Offset (Tvfp) = xx lines Sync Width = xx lines
53 Horizontal Vertical Sync Offset/Width upper 2 bits
54 Horizontal Image Size =xxx mm
www.panelook.com
01
01
01
01
01
01
01
01
01
01
01
01
01
01
01
64
19
00
40
41
00
26
30
18
88
36
00
30
E4
10
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1100100
11001
0
1000000
1000001
0
100110
110000
11000
10001000
110110
0
110000
11100100
10000
0
0
11000
0
0
0
0
0
0
0
0
0
0
0
0
0
24/24
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
Timing Descripter #3
Dell specific information
Timing Descripter #4
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
55 Vertical image Size = xxx mm
56 Horizontal Image Size / Vertical image size
57 Horizontal Border = 0 (Zero for Notebook LCD)
58 Vertical Border = 0 (Zero for Notebook LCD)
59 Module “A” Revision = Example: 00, 01, 02, 03, etc.
5A Flag
5B Flag
5C Flag
5D Dummy Descriptor
5E Flag
5F Dell P/N 1st Character
60 Dell P/N 2nd Character
61 Dell P/N 3rd Character
62 Dell P/N 4th Character
63 Dell P/N 5th Character
64 LCD Supplier EEDID Revision #
65 Manufacturer P/N
66 Manufacturer P/N
67 Manufacturer P/N
68 Manufacturer P/N
69 Manufacturer P/N
6A Manufacturer P/N
Manufacturer P/N (If <13 char, then terminate with ASCII code 0Ah, set remaining
6B
char = 20h)
6C Flag
6D Flag
6E Flag
6F Data Type Tag:
70 Flag
71 SMBUS Value = 10 nits
72 SMBUS Value = 17 nits
73 SMBUS Value = 24 nits
74 SMBUS Value = 30 nits
75 SMBUS Value = 60 nits
76 SMBUS Value = 110 nits
77 SMBUS Value = 150 nits
78 SMBUS Value = max nits (Typically = 00h, XXX nits)
79 Number of LVDS receiver chips = ‘01’ or ‘02’
7A BIST Enable: Yes = ‘01’ No = ‘00’
7B (If <13 char, then terminate with ASCII code 0Ah, set remaining char = 20h)
www.panelook.com
00
00
00
00
00
00
00
00
FE
00
44
38
33
38
31
00
42
31
35
30
58
47
32
00
00
00
FE
00
D0
C0
B0
A8
88
60
40
00
01
01
0A
0
0
0
0
0
0
0
0
11111110
0
1000100
111000
110011
111000
110001
0
1000010
110001
110101
110000
1011000
1000111
110010
0
0
0
11111110
0
11010000
11000000
10110000
10101000
10001000
1100000
1000000
0
1
1
1010
25/25
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
7C (If <13 char, then terminate with ASCII code 0Ah, set remaining char = 20h)
7D (If <13 char, then terminate with ASCII code 0Ah, set remaining char = 20h)
20
20
100000
100000
7E Extension flag (# of optional 128 EDID extension blocks to follow, Typ = 0)
Checksum
7F Checksum (The 1-byte sum of all 128 bytes in this EDID block shall = 0)
00
2A
0
101010
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
No Reproduction and Redistribution Allowed.
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
26/26
www.panelook.com
Loading...