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B140XTN02.4
Specification
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AUO B140XTN02.4 Specification

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Product Specification
AU OPTRONICS CORPORATION
( ) Preliminary Specifications ( V ) Final Specifications
Module 14.0”(13.97”) HD 16:9 Color TFT-LCD
with LED Backlight design
Model Name
Note ( )
B140XTN02.4 (H/W:0A)
LED Backlight with driving circuit design
Customer Date
ACER 10/09/2012
Checked &
Date
Approved by
Note: This Specification is subject to change without notice.
Approved by Date
Jonken Fan
10/09/2012
Prepared by Date
William Lu
NBBU Marketing Division
AU Optronics corporation
10/09/2012
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Contents
1. Handling Precautions....................................................................................... 4
2. General Description.......................................................................................... 5
2.1 General Specification......................................................................................................... 5
2.2 Optical Characteristics....................................................................................................... 6
3. Functional Block Diagram.............................................................................. 11
4. Absolute Maximum Ratings........................................................................... 12
4.1 Absolute Ratings of TFT LCD Module ............................................................................. 12
4.2 Absolute Ratings of Environment..................................................................................... 12
5. Electrical Characteristics............................................................................... 13
5.1 TFT LCD Module ............................................................................................................. 13
5.2 Backlight Unit................................................................................................................... 16
6. Signal Interface Characteristic ...................................................................... 17
6.1 Pixel Format Image.......................................................................................................... 17
6.2 Integration Interface Requirement ................................................................................... 18
6.3 Interface Timing............................................................................................................... 21
6.4 Power ON/OFF Sequence............................................................................................... 22
7. Panel Reliability Test...................................................................................... 25
7.1 Vibration Test ................................................................................................................... 25
7.2 Shock Test ....................................................................................................................... 25
7.3 Reliability Test.................................................................................................................. 25
8. Mechanical Characteristics ........................................................................... 26
8.1 LCM Outline Dimension................................................................................................... 26
9. Shipping and Package ................................................................................... 28
9.1 Shipping Label Format..................................................................................................... 28
9.2 Carton Package ............................................................................................................... 29
9.3 Shipping Package of Palletizing Sequence ..................................................................... 29
10. Appendix: EDID Description ........................................................................ 30
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Record of Revision
Version and Date Page Old description New Description Remark
0.1 2012/05/15 All First Edition for Customer
0.2 2012/05/29 28 Update Back side drawing
0.3 2012/05/30 19 Update Pin Assignment
0.4 2012/06/14 30~33 Update EDID
0.5 2012/08/29 19 Pin 24 : EDID CLK, Pin 25: EDID_DATA, Pin 26 : Backlight power
0.6 2012/09/25 26,27 Update the requried drawing
1.0 2012/09/26 All Final confirmation
1.1 2012/10/09 6 Update CIE 1931
Pin 24/25/26 : NC
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1. Handling Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration or spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure human earth when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor tilt the Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure (Notebook PC Bezel, for example), do not twist nor bend the TFT Module even momentary. At designing the enclosure, it should be taken into consideration that no bending/twisting forces are applied to the TFT Module from outside. Otherwise the TFT Module may be damaged.
12) Small amount of materials having no flammability grade is used in the LCD module. The LCD module should be supplied by power complied with requirements of Limited Power Source (IEC60950 or UL1950), or be applied exemption.
13) Disconnecting power supply before handling LCD modules, it can prevent electric shock, DO NOT TOUCH the electrode parts, cables, connectors and LED circuit part of TFT module that a LED light bar build in as a light source of back light unit. It can prevent electrostatic breakdown.
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2. General Description
B140XTN02.4 is a Color Active Matrix Liquid Crystal Display composed of a TFT LCD panel, a driver circuit, and LED backlight system. The screen format is intended to support the 16:9 HD, 1366(H) x768(V) screen and 262K colors (RGB 6-bits data driver) with LED backlight driving circuit. All input signals are eDP(Embedded DisplayPort) interface compatible.
B140XTN02.4 is designed for a display unit of notebook style personal computer and industrial machine.
2.1 General Specification
The following items are characteristics summary on the table at 25
Items Unit Specifications
Screen Diagonal [mm] 354.95
Active Area [mm] 309.4 x 173.95
Pixels H x V 1366x3(RGB) x 768
ʚ
condition:
Pixel Pitch [mm] 0.2265 x 0.2265
Pixel Format R.G.B. Vertical Stripe
Display Mode Normally White
White Luminance
[cd/m2] 220 typ. (5 points average)
187 min. (5 points average) Luminance Uniformity 1.25 max. (5 points) Contrast Ratio 500 typ Response Time [ms] 8 typ / 16 Max
Nominal Input Voltage VDD [Volt] +3.3 typ.
Power Consumption [Watt] 3.3 max. (Include Logic and Blu power)
Weight [Grams] 285 max.
Physical Size include bracket
[mm]
Min Typ Max
Length 319.9 320.4 320.9
Width 204.6 205.1 205.6
- - 3.2
Electrical Interface 1 Lane eDP
Glass Thickness [mm] 0.4
Surface Treatment Glare, Hardness 3H,
Support Color 262K colors ( RGB 6-bit )
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Product Specification
Temperature Range
Operating Storage (Non-Operating)
AU OPTRONICS CORPORATION
o
[
C]
o
[
C]
0 to +50
-20 to +60
RoHS Compliance RoHS Compliance
2.2 Optical Characteristics
ʚ
The optical characteristics are measured under stable conditions at 25
Item Symbol Conditions Min. Typ. Max. Unit Note
White Luminance
I
LED
=20mA
5 points average 187 220 -
șR ș
L
Horizontal (Right)
CR = 10 (Left)
Viewing Angle
ȥ
Vertical (Upper)
CR = 10 (Lower)
5 Points
13 Points
400 500 -
- - 4
Luminance Uniformity
Luminance Uniformity
Contrast Ratio CR
Cross talk %
H
ȥ
L
į
5P
į
13P
Response Time TRT Rising + Falling
Rx
Red
Ry
Gx
Color /
Green
Gy
Chromaticity
Coodinates
Blue
Bx
By
CIE 1931
Wx
White
Wy
(Room Temperature) :
40
40
10
30
45
45
15
35
-
-
-
-
- - 1.25
- - 1.60
- 8 16
0.550 0.580 0.610
0.305 0.335 0.365
0.300 0.330 0.360
0.535 0.565 0.595
0.125 0.155 0.185
0.110 0.140 0.170
0.283
0.299
0.313 0.343
0.329 0.359
cd/m2
degree
msec
1, 4, 5.
4, 9
1, 3, 4
2, 3, 4
4, 6
4, 7
4, 8
4
NTSC %
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igh
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Product Specification
Note 1: 5 points position (Ref: Active area)
H/4
H/4
H
H/4
H/4
Note 2: 13 points position (Ref: Active area)
AU OPTRONICS CORPORATION
W/4 W/4 W/4 W/4
W
12
3
4
W
5
W/4
10
3
H/4
10
10
W/4
1
W/4
W/4
2
45
H/4
H
H/4
6
9
H/4
10
11
7
10
12
Note 3: The luminance uniformity of 5 or13 points is defined by dividing the maximum luminance values by the minimum test point luminance
Ӭ
Maximum Br
=
W5
Minimum Br
tness of five points
tness of five points
8
13
Maximum Br
Ӭ
W13
=
Minimum Bri
tness of thirteen points
htness of thirteen points
Note 4: Measurement method
The LCD module should be stabilized at given temperature for 30 minutes to avoid abrupt temperature change
during measuring. In order to stabilize the luminance, the measurement should be executed after lighting
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Backlight for 30 minutes in a stable, windless and dark room, and it should be measured in the center of screen.
AU OPTRONICS CORPORATION
Photo detector
Field=2
-
!!
Note 5
Note 6
Note 7
Ǻ
Definition of Average Luminance of White (YL):
Ǵ
Y
Measure the luminance of gray level 63 at 5 points
L (x) is corresponding to the luminance of the point X at Figure in Note (1).
Ǻ
Definition of contrast ratio:
Contrast ratio is calculated with the following formula.
Contrast ratio (CR)=
Ǻ
Definition of Cross Talk (CT)
B
CT = | Y
– YA | / YA × 100 (%)
Brightness on the “White” state
Bri
htness on the “Black” state
= [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5
L
Where
Y
A
= Luminance of measured location without gray level 0 pattern (cd/m2)
Y
B
= Luminance of measured location with gray level 0 pattern (cd/m2)
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Note 8: Definition of response time:
The output signals of BM-7 or equivalent are measured when the input signals are changed from “Black” to
“White” (falling time) and from “White” to “Black” (rising time), respectively. The response time interval between
the 10% and 90% of amplitudes. Refer to figure as below.
"Black"
100%
S ig
90%
n a l
(
R e
la t
iv e v
a lu
10%
e )
0%
Tr
Tf
"White""White"
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Note 9. Definition of viewing angle
Viewing angle is the measurement of contrast ratio ɪ10, at the screen center, over a 180° horizontal and
180° vertical range (off-normal viewing angles). The 180° viewing angle range is broken down as follows; 90°
(ș) horizontal left and right and 90° (ĭ) vertical, high (up) and low (down). The measurement direction is
typically perpendicular to the display surface with the screen rotated about its center to develop the desired
measurement viewing angle.
AU OPTRONICS CORPORATION
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3. Functional Block Diagram
The following diagram shows the functional block of the 14.0 inches wide Color TFT/LCD 30 Pin
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4. Absolute Maximum Ratings
An absolute maximum rating of the module is as following:
4.1 Absolute Ratings of TFT LCD Module
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage Vin -0.3 +4.0 [Volt] Note 1,2
4.2 Absolute Ratings of Environment
Item Symbol Min Max Unit Conditions
Operating Temperature TOP 0 +50 [oC] Note 4
Operation Humidity HOP 5 95 [%RH] Note 4
Storage Temperature TST -20 +60 [oC] Note 4
Storage Humidity HST
Note 1: At Ta (25ʚ )
Note 2: Permanent damage to the device may occur if exceed maximum values
Note 3: LED specification refer to section 5.2
5 95
[%RH]
Note 4
Note 4: For quality performance, please refer to AUO IIS (Incoming Inspection Standard).
Twb=39°C
Operating Range
Storage Range
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5. Electrical Characteristics
5.1 TFT LCD Module
5.1.1 Power Specification
Input power specifications are as follows;
ʚ
The power specification are measured under 25
Symble Parameter Min Typ Max Units Note
VDD Logic/LCD Drive
Volta
e
PDD VDD Power IDD IDD Current
I
Rush
Inrush Current
VDDrp Allowable
Logic/LCD Drive Ripple Voltage
Note 1 : Maximum Measurement ConditionǺBlack Pattern at 3.3V driving voltage. (P
and frame frenquency under 60Hz
3.0 3.3 3.6 [Volt]
-
-
- -
- -
0.9 [Watt] Note 1
250
2000
100
[mA] Note 1
[mA]
[mV]
Note 2
p-p
max=V3.3
x I
black
)
Typical Measurement Condition : Mosaic Pattern
Ǻ
Note 2
Measure Condition
90%
10%
0V
0.5ms
Vin rising time
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5.1.2 Signal Electrical Characteristics
Input signals shall be low or High-impedance state when VDD is off.
Signal electrical characteristics are as follows; Display Port main link signal:
Display port main link
ʳ ʳ Min Typ Max unit
VCM RX input DC Common Mode Voltage ʳ GND V
VDiff
Fallow as VESA display port standard V1.1a
B140XTN02.4 Document Version : 1.1
Peak-to-peak Voltage at a receiving Device 100 ʳ 1320 mV
P-P
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Display Port AUX_CH signal:
Display port AUX_CH
ʳ ʳ Min Typ Max unit
VCM AUX DC Common Mode Voltage 0 GND/0.15 V
VDiff
Fallow as VESA display port standard V1.1a.
Display Port V
AUX Peak-to-peak Voltage at a receiving Device 0.4 0.6 0.8 V
P-P
HPD
signal:
Display port V
HPD
ʳ ʳ Min Typ Max unit
V
HPD
HPD Voltage 2 - 2.5 V
Fallow as VESA display port standard V1.1a.
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5.2 Backlight Unit
5.2.1 LED characteristics
Parameter
Backlight Power Consumption
Symbol
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AU OPTRONICS CORPORATION
Min Typ Max Units Condition
PLED - - 2.1
[Watt]
(Ta=25 ), кNote 1 Vin =12V
LED Life-Time
Note 1: Calculator value for reference P
Note 2: The LED life-time define as the estimated time to 50% degradation of initial luminous.
N/A 15,000 - -
= VF (Normal Distribution) * IF (Normal Distribution) / Efficiency
LED
Hour
(Ta=25 ), Note 2к
I
5.2.2 Backlight input signal characteristics
Parameter
Symbol
Min Typ Max Units Remark
LED Power Supply VLED 6.0 12.0 21.0 [Volt]
LED Enable Input High Level
2.5 - 5.5 [Volt]
VLED_EN
LED Enable Input Low Level
- - 0.8 [Volt]
PWM Logic Input High Level
PWM Logic Input Low Level
2.5 - 5
VPWM_EN
- - 0.8
[Volt]
[Volt]
=20 mA
F
Define as
Connector
Interface
(Ta=25 )
к
PWM Input Frequency
PWM Duty Ratio
Note 1 : Recommend system pull up/down resistor no bigger than 10kohm
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FPWM 200 600 1K
Duty 5 -- 100
Hz
%
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6. Signal Interface Characteristic
6.1 Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format.
AU OPTRONICS CORPORATION
 
VW/LQH
WK/LQH
5 * % 5 * %
5 * % 5 * %
5 * % 5 * %
5 * % 5 * %
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6.2 Integration Interface Requirement
6.2.1 Connector Description
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following components.
Connector Name / Designation For Signal Connector
Manufacturer I-PEX or compatible
AU OPTRONICS CORPORATION
Type / Part Number
IPEX 20455-030E-˄2 or compatible
Mating Housing/Part Number IPEX 20453-030T-1 or compatible
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6.2.2 Pin Assignment (1 Lane)
eDP lane is a differential signal technology for LCD interface and high speed data transfer device.
PIN NO Symbol Function
1
NC
2
H_GND
3
NC
4
NC
5
H_GND
6
Lane0_N
7
Lane0_P
8
H_GND
AU OPTRONICS CORPORATION
No connect
High Speed Ground
No connect
No connect
High Speed Ground
Comp Signal Link Lane 0
True Signal Link Lane 0
High Speed Ground
ʳ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
AUX_CH_P
AUX_CH_N
H_GND
LCD_VCC
LCD_VCC
LCD_Self_Test
LCD_GND
LCD_GND
HPD
BL_GND
BL_GND
BL_GND
BL_GND
BL_Enable
BL_PWM_DIM
NC
True Signal Auxiliary Ch.
Comp Signal Auxiliary Ch.
High Speed Ground
LCD logic and driver power
LCD logic and driver power
LCD Panel Self Test Enable
LCD logic and driver ground
LCD logic and driver ground
HPD signal pin
Backlight ground
Backlight ground
Backlight ground
Backlight ground
Backlight On / Off
System PWM signal Input
No connect
ʳ
25
NC
26
NC
27
BL_PWR
28
BL_PWR
29
BL_PWR
30
NC
No connect
No connect
Backlight power
Backlight power
Backlight power
No connect
ʳ
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Connector
Pin 30
Note1: Start from right side.
Note2: Input signals shall be low or High-impedance state when VDD is off. Internal circuit of eDP inputs are as following.
Pin 1
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6.3 Interface Timing
6.3.1 Timing Characteristics
Basically, interface timings should match the 1366x768 /60Hz manufacturing guide line timing.
Parameter Symbol Min. Typ. Max. Unit
Frame Rate - 60 - Hz
AU OPTRONICS CORPORATION
Clock frequency 1/ T
T
Vertical
T
Section
T
T
Horizontal
T
Section
T
- 76.3 - MHz
Clock
788 798 768+A
V
768
VD
20 30 A
VB
1416 1598 1366+B
H
1366
HD
50 232 B
HB
Note 1 : The above is as optimized setting Note 2 : The maximum clock frequency = (1366+B)*(768+A)*60<80MHz
T
T
Line
ʳʳʳʳ
Clock
ʳʳʳʳ
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6.4 Power ON/OFF Sequence
Display Port panel power sequence:
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Display Port AUX_CH transaction only:
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Display Port panel power sequence timing parameter:
AU OPTRONICS CORPORATION
Note1: The sink must include the ability to generate black video autonomously. The sink must automatically enable black video under the following conditions:
-upon LCDVDD power on (with in T2 max)-when the "Novideostream_Flag" (VB-ID Bit 3) is received from the source (at the end of T9).
-when no main link data, or invalid video data, is received from the source. Black video must be displayed within 64ms (typ) from the start of either condition. Video data can be deemed invalid based on MSA and timing information, for example.
Note 2: The sink may implement the ability to disable the black video function, as described in Note 1, above, for system development and debugging purpose.
Note 3: The sink must support AUX_CH polling by the source immediately following LCDVDD power on without causing damage to the sink device (the source can re-try if the sink is not ready). The sink must be able to respond to an AUX_CH transaction with the time specified within T3 max.
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Display Port panel B/L power sequence timing parameter:
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7. Panel Reliability Test
7.1 Vibration Test
Test Spec:
Test method: Non-Operation
z
Acceleration: 1.5 G
z
Frequency: 10 - 500Hz Random
z
Sweep: 30 Minutes each Axis (X, Y, Z)
z
7.2 Shock Test
Test Spec:
Test method: Non-Operation
z
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AU OPTRONICS CORPORATION
Acceleration: 220 G , Half sine wave
z
Active time: 2 ms
z
Pulse: X,Y,Z .one time for each side
z
7.3 Reliability Test
Items
Temperature
Humidity Bias
High Temperature
Operation
Low Temperature
Operation
High Temperature
Storage
Low Temperature
Storage
Thermal Shock
Test
Ta= 40кккк, 90%RH, 300h
Ta= 50кккк, Dry, 300h
Ta= 0кккк, 300h
Ta= 60кккк, 35%RH, 300h
Ta= -20кккк, 50%RH, 250h
Ta=-20ккккto 60кккк, Duration at 30 min, 100 cycles
Required Condition Note
ESD
Contact : ±8 KV
Air : ±15 KV
Note1: According to EN 61000-4-2 , ESD class B: Some performance degradation allowed. Self-recoverable.
No data lost, No hardware failures.
Remark: MTBF (Excluding the LED): 30,000 hours with a confidence level 90%
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Note 1
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8. Mechanical Characteristics
8.1 LCM Outline Dimension
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Product Specification
AU OPTRONICS CORPORATION
Note: Prevention IC damage, IC positions not allowed any overlap over these areas.
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Product Specification
AU OPTRONICS CORPORATION
9. Shipping and Package
9.1 Shipping Label Format
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9.2 Carton Package
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Product Specification
AU OPTRONICS CORPORATION
9.3 Shipping Package of Palletizing Sequence
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10. Appendix: EDID Description
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Product Specification
AU OPTRONICS CORPORATION
Address
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
FUNCTION Value Value Value Note
ʳʳʳʳ
HEX BIN DEC
Header 00 00000000 0
ʳ
FF 11111111 255
ʳ
FF 11111111 255
ʳ
FF 11111111 255
ʳ
FF 11111111 255
ʳ
FF 11111111 255
ʳ
FF 11111111 255
ʳ
00 00000000 0
EISA Manuf. Code LSB 06 00000110 6
Compressed ASCII AF 10101111 175
΁ΣΠΕΦΔΥʹΠΕΖ
ΙΖΩͽ΄ͳΗΚΣΤΥ
32-bit ser # 00 00000000 0
ʳ
00 00000000 0
3C 00111100 60
24 00100100 36
!!!!
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
ʳ
00 00000000 0
ʳ
00 00000000 0
Week of manufacture 00 00000000 0
Year of manufacture 16 00010110 22
EDID Structure Ver. 01 00000001 1
EDID revision # 04 00000100 4
Video input def.
Max H image size
Max V image size
Display Gamma
Feature support
(digital I/P, non-TMDS, CRGB)
(rounded to cm)
(rounded to cm)
(=(gamma*100)-100)
(no DPMS, Active OFF, RGB, tmg
Blk#1)
Red/green low bits (Lower 2:2:2:2 bits)
Blue/white low bits (Lower 2:2:2:2 bits)
Red x (Upper 8 bits)
Red y/ highER 8 bits 55 01010101 85
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
95 10010101 149
1F 00011111 31
11 00010001 17
78 01111000 120
02 00000010 2
BB 10111011 187
F5 11110101 245
94 10010100 148
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
1D
1E
1F
20
21
22
Green x 54 01010100 84
Green y 90 10010000 144
Blue x 27 00100111 39
Blue y 23 00100011 35
White x 50 01010000 80
White y 54 01010100 84
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23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
Established timing 1 00 00000000 0
Established timing 2 00 00000000 0
Established timing 3 00 00000000 0
Standard timing #1 01 00000001 1
ʳ
01 00000001 1
Standard timing #2 01 00000001 1
ʳ
01 00000001 1
Standard timing #3 01 00000001 1
ʳ
01 00000001 1
Standard timing #4 01 00000001 1
ʳ
01 00000001 1
Standard timing #5 01 00000001 1
ʳ
01 00000001 1
Standard timing #6 01 00000001 1
ʳ
01 00000001 1
Standard timing #7 01 00000001 1
ʳ
ʳ ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
33
34
35
36
Pixel Clock/10000 LSB
37
Pixel Clock/10000 USB
Horz active Lower 8bits
38
Horz blanking Lower 8bits
39
3A
3B
3C
3D
3E
3F
HorzAct:HorzBlnk Upper 4:4 bits
Vertical Active Lower 8bits
Vertical Blanking Lower 8bits
Vert Act : Vertical Blanking (upper 4:4 bit)
HorzSync. Offset
HorzSync.Width
40
41
42 Horizontal Image Size Lower 8bits
VertSync.Offset : VertSync.Width
Horz&Vert Sync Offset/Width Upper 2bits
Standard timing #8 01 00000001 1
ʳ
01 00000001 1
ʳ
01 00000001 1
CE 11001110 206
1D 00011101 29
56 01010110 86
E2 11100010 226
50 01010000 80
00 00000000 0
1E 00011110 30
30 00110000 48
26 00100110 38
16 00010110 22
36 00110110 54
00 00000000 0
35 00110101 53
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
43 Vertical Image Size Lower 8bits
44 Horizontal & Vertical Image Size (upper 4:4 bits)
45
46
47
48
49
Horizontal Border
Vertical Border
Signal
(non-intr, norm, no stero, sep sync, neg pol)
(zero for internal LCD)
(zero for internal LCD)
00 00000000 0 ʳ
Detailed timing/monitor 00 00000000 0
descriptor #2 00 00000000 0
AD 10101101 173
10 00010000 16
00 00000000 0
18 00011000 24
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4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
ʳ
00 00000000 0
ʳ
0F 00001111 15
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
00 00000000 0
ʳ
20 00100000 32
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
Detailed timing/monitor 00 00000000 0
descriptor #3 00 00000000 0
ʳ
00 00000000 0
ʳ
FE 11111110 254
ʳ
00 00000000 0
Manufacture 41 01000001 65 A
Manufacture 55 01010101 85 U
Manufacture 4F 01001111 79 O
ʳ
0A 00001010 10
ʳ
20 00100000 32
ʳ
20 00100000 32
ʳ
20 00100000 32
ʳ
20 00100000 32
ʳ
20 00100000 32
ʳ
20 00100000 32
ʳ
20 00100000 32
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
6A
6B
6C
6D
6E
6F
70
Detailed timing/monitor 00 00000000 0
ʳ
20 00100000 32
ʳ
20 00100000 32
descriptor #4 00 00000000 0
ʳ
00 00000000 0
ʳ
FE 11111110 254
ʳ
00 00000000 0
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71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Manufacture P/N 42 01000010 66 B
Manufacture P/N 31 00110001 49 1
Manufacture P/N 34 00110100 52 4
Manufacture P/N 30 00110000 48 0
Manufacture P/N 58 01011000 88 X
Manufacture P/N 54 01010100 84 T
Manufacture P/N 4E 01001110 78 N
Manufacture P/N 30 00110000 48 0
Manufacture P/N 32 00110010 50 2
Manufacture P/N 2E 00101110 46 .
Manufacture P/N 34 00110100 52 4
ʳ
20 00100000 32
ʳ
0A 00001010 10
Extension Flag 00 00000000 0
Checksum E6 11100110 230
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