AudioControl XD0 Mk2 Schematic
DCBA
LM2950
TXP
TXN
0.1uF
U4
3
VO
C2
C10
330 uF
17
16
18
TP1
26
25
TP2
21
S7 LED3
S3 U2p15
S3 U2p3 & JP12
Title
Size
A
Date
Filename
1
VI
G
2
C4
out
VDD
R2
300/1watt
S2 R10
S2 R11
R12
S2 X2p5
S2 X2p8
S2 R13
c
Copyright 2003 Audio Crafters Guild
XD0 DIR, AJR Filter, Upsampler
ACG 2001.9.1
9 April 2003
XD0.S01
47k
1
RP1
JP1-JP9
10
9
8
7
6
5
4
3
2
1
VDD
47k
10
9
8
7
6
5
4
3
2
1
RP2
CFILT
CRIP
0.0022 uF
RFILT
2
12
13
14
5
4
ILRCK(TCBLD)
ISCLK(PRO/C)
SDIN(MUTE)
RXN
RXP
S2 R76
S2 R5
S2 R7
Master Clock Out
S2 R8
S2 X1p5
S2 X1p8
3
HWCONFIGBUS/9
Misc.
R
S
T
9
1
0
R
M
C
K
AES3 IN
H
/
S
2
4
1
1
R
E
R
R
Serial In
S
/
D
D
F
F
A
C
C
E
0
1
S
2
2
0
0.047 uF
3k
8
F
I
L
T
U
/
E
M
P
H
2
7
3
C1
10
C5
10
C7
0.1
6
V
A
+
Control
C
O
P
Y
FB1
7
A
G
N
D
CS8420
O
R
I
G
1
GNDANALOG
U1
V
/
A
U
T
D
C
I
B
O
L
2
1
8
9
2
3
V
D
+
1
5
FB8
C3
10
C6
10
C8
0.1
2
2
D
G
N
D
Serial Out
Output Master
Clock Generator
GNDDIGITAL
OLRCK
OSCLK
SDOUT
AES3 Out
OMCK
VIDEO
ERROR
RESET
S7 U20p7
R4
47k
4
VDD
(S3) CONFIG2
(S3) CONFIG0
(S3) CONFIG1
To U1 pin 11
NC7S32
1
U5
2
G
3
TP4
C77
V
5
TP5
4
FB9
VDD
600 ohms
39uF
2
1k
10.5k
polarity
S7
L1
D1
IN4004
U8
VO
A
R1
R3
2
1
NC7S86M5
SOT23
VI
1
39 uF
7486
U3:A
U3:B
Drawn by
3
C11
4
3
5
VEE
C9
3
C70
VDD
1
330 uF
S2 R12
0.1
FB10
RevNumber
2.1
NPT
ofSheet
1
in
VDD
2
3
4
8
A B C D
DCBA
J1
SPDIF IN
1
1 = Clock Out in Syncro Mode
2-4 I2S Inputs
5-6 Mode Jumper
2
I2SIN:2
10
9
8
7
6
1
2
3
4
5
R8
75
R7
R5
75
R76
75
75
J2
SPDIF OUT
S1 U1p10
Optional RF bypass to chassis
S1 U1p12
S1 U1p13
S1 U1p14
C76
0.1 uF
S1
4
S2
SC937
S1
S2
SC937
R6
R9
C72
C73
C74
75 75
C75
0.01 uF
S1 U1p4
S1 U1p5
S1 U1p26
S1 U1p25
1
2
X1
P1
5
P2
X2
8
2
SH
P1
P2
SH
1
3
Sheet In/Out label scheme
4
S1 U1p14
Sheet number
S7 OSC2p3
S7 OSC1p3
S1 U1p21
S1 U1p16
Pin number if applicaple
Device number or signal name
256 Fs
256 Fs
64 Fs
R11
R13
75
S1 U1p17
S1 U1p18
Fs
Data
R10
Expansion Port
J6
J5
1
2
3
4
5
6
7
8
9
10
For normal operation
install jumpers
3 to 3
5 to 5
7 to 7
9 to 9
Ground jumpers to pins 10 may
be cut if spare I/O pins are needed.
c
Copyright 2003 Audio Crafters Guild
1
2
3
4
5
6
7
8
9
10
VDD
S3 R17
S3 R15
S3 R16
S3 R18
Title
XD0 Digital I/O Connections
Size
A
Date
Filename
9 April 2003
ACG 2001.9.1
XD0.S02
A B C D
Drawn by
3
4
RevNumber
2.1
NPT
2
8
ofSheet
DAC Sample Rate Configurations & Emphasis
2
I S modes
44k no emph.
1
44k w/emph.
96k *
192k *
* Emphasis not available for 96k & 192k rates.
M4 M3 M2 M1 M0
0 1 1 0 1
0 0 1 0 1
1 1 1 0 1
1 1 0 0 1
S2 R12
2
R18
S1 U1p3
VDD
10k
JP12
10k
JP13
3
JP14
JP15
JP16
RP5
S2 R13
75
10k
R17
75
10k
S2 R11
R16
10k
75
S2 R10
R15
DCBA
VEE
FB2
C13
FB11
C14
10 uF
10 uF
C15
U6
6
V+
C16
0.1 uF
0.1 uF
FB13
2
1
9
75
12
LRCK
11
SCLK
10
MCLK
13
SDATA
6
D
V
D
G
D
G
N
N
D
D
2
7
8
V
D
8
1
A
A
G
G
N
N
D
D
U2
CS4396
or
2
2
8
V
V
A
R
+
E
F
AOUTLÂAOUTL+
CS4397 or
CS43122
R
M
E
M
C
M
M
M
4
2
3
2
3
/
M
M
0
H
1
4
5
1
1
6
4
U
S
U
T
E
T
E
T
E
C
1
1
1
5
7
AOUTRÂAOUTR+
F
F
I
I
L
L
T
T
CMOUT
-
+
2
2
6
7
FB12
24
23
19
20
25
330 uF
C20
VEE
C21
1
NC
8
NC
2
-
AD811
NC
7
S4 FB4 OR S8 FB102
S4 FB6 OR S8 FB103
S4 FB5 OR S8 FB100
S4 FB7 OR S8 FB101
0.1 uF
3
+
V-
5
4
C22
R80
C17
10 uF
C23
1k
R14
100k
1
FB3
3
0.1uF
10 uF
C12
U7
LM2950
VO
C18
1
L2
1
1
VI
G
2
C19
600 ohms
39uF
2
3
JP17
Sheet In/Out label scheme
4
S1 U1p14
Sheet number
Pin number if applicaple
Device number or signal name
S7 U20p7
S1 U5p4
C24
MUTEC
c
Copyright 2003 Audio Crafters Guild
0.1 uF
C25
10 uF
Title
Size
Date
Filename
C26
10 uF
XD0 CS4396/7/122 DAC Stage
A
9 April 2003
ACG 2001.9.1
XD0.S03
A B C D
GNDDIGITALGNDANALOG
Drawn by
4
RevNumber
2.1
NPT
3
8
ofSheet
DCBA
1
2
3
S3 U2p24
S3 U2p23
Left
4
3
12
G DRIVE
16
INPUT
15
FB4
RG1
open
FB6 FB7
13
14
6
2
1
5
GAIN SENSE
RG
G=100
+RG
+GAIN SENSE
+INPUT
+G DRIVE
C29
0.033uF
C31 C32
+
10 uF BG
N
N
U
U
L
L
L
L
U9
INA103
V
+9V
SENSE
OUPUT
8
REF
C27
11
R24
10
75
7
0.033uF
C33
10 uF BG 10 uF BG
+
C37
+
10 uF BG
+
S3 U2p19
FB5
LEFTOUT_J5
S3 U2p20
RG2
open
12
G DRIVE
16
INPUT
15
GAIN SENSE
13
RG
14
G=100
6
+RG
2
+GAIN SENSE
1
+INPUT
5
+G DRIVE
C30
0.033uF
10 uF BG
C36C35
10 uF BG
+
+
Right
3
N
U
L
L
U10
INA103
V
+
9
4
N
U
L
L
SENSE
OUPUT
V
8
C28
0.033uF
C34
C38
10 uF BG10 uF BG
REF
1
11
R25
10
75
7
++
RIGHTOUT_J6
2
3
FB14
4
FB15
S6U18p3S6U16p2
c
Copyright 2003 Audio Crafters Guild
S6U17p2 S6U19p3
Title
XD0 Analog Stage
FB16
FB17
Size
A
Date
Filename
9 April 2003
ACG 2001.9.1
Drawn by
XD0.S04
4
RevNumber
2.1
NPT
4
8
ofSheet
A B C D
DCBA
Vee
FB19
D6
U11
1
FB18
330 uF
C40
3
C79
VI
39 uF
2
VO
A
1
R19
R20
1k
10.5k
C78
C41
330 uF
39 uF
C43
R29
R31
10k
10k
R32
1k
2
-
3
+
R21
2
300/1watt
330 uF
C45
C39
330 uF
8
LM833M
4
0.05
U13:A
1
R33
47k
R26
C44
330 uF
R30
300k
R28
R34
4300
B
470
R27
C
2N4401
E
R35
220
U12
15
330 uF
C42
TO92
C B E
* * *
2N4401
Top View
1
2
3
4
GNDDIGITAL GNDANALOG
A B C D
C47
39 uF
R39
R41
10k
10k
1k
R42
330 uF
6
5
C49
R36
FB20
VAOSC
0.05
220
R37
C46
-
+
U13:B
7
LM833M
C48
330 uF
R38
4300
B
C
2N4401
E
U15
330 uF
3
R40
R43
300k
47k
470
R4415R45
Title
XD0 Clock Twin Shunt Regulator
4
RevNumber
2.1
NPT
ofSheet
c
Copyright 2003 Audio Crafters Guild
Size
A
Date
Filename
9 April 2003
ACG 2001.9.1
Drawn by
XD0.S05 5 8
DCBA
D3
U17
3
VI
A
C55
39 uF
J9
Right Power
D5
U19
2
VI
A
C61
39 uF
2
VO
1
1k
R47
S4U10
1
R49
R51R57
10.5k
300/1watt
DK# P10298 $0.58/10
2
3
VO
1
1k
R53
R55
300/1watt
10.5k
S4U10
3
3
C54
D2
U16
VI
A
39 uF
2
VO
1
R46
1k
S4U9
R48
300/1watt
10.5k
+15v Analog
1
330 uF
C50
330 uF
C51
FB22
+VA1
GND
J8
2
FB23
-VA1
GND
Left Power
FB24
FB25
+15v Analog
C52
330 uF
-15v Analog-15v Analog
330 uF
+VA2
GND
-VA2
GND
C53
D4
U18
2
VI
C56
330 uF
3
330 uF
C57
C60
39 uF
3
VO
A
1
R52
1k
R54
R56 R50
10.5k
300/1watt
S4U9
C58
C59
330 uF
330 uF
4
note: Output caps required for regulator stability
shown on analog stage sheet #4.
A B C D
DIR & DAC Regulator Input
Vee
GND
J7
Vdd
GND
Power In From External Supply
c
Copyright 2003 Audio Crafters Guild
S1L1, S2L2, S5U11
S1U4p2
S1U8p3, S7RP4
S1C11, S1R3
Title
XD0 Power Regulators
Size
A
9 April 2003
Date
Filename
ACG 2001.9.1
Drawn by
NPT
ofSheet
RevNumber
2.1
4
86XD0.S06
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