ATMEL TS68C429AVR, TS68C429AVF, TS68C429AMRB-C, TS68C429AMR, TS68C429AMFB-C Datasheet

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Features

• 8 Independent Receivers (Rx)

• 3 Independent Transmitters (Tx)

• Full TS68K Family Microprocessor Interface Compatibility

• 16-bit Data-bus

• ARINC 429 Interface: “1” and “0” Lines, RZ Code

• Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s

• Multi Label Capability

• Parity Control: Odd, Even, No Parity, Interrupt Capability

• Independent Programmable Frequency for Rx and Tx Channels

• 8 Messages FIFO per Tx Channel

• Independent Interrupt Request Line for Rx and Tx Functions

• Vectored Interrupts

• Daisy Chain Capability

• Direct Addressing of all Registers

• Test Modes Capability

• 20 MHz Operating Frequency

• Self-test Capability for Receiver Label Memories and Transmit FiFO

• Low Power: 400 mW

CMOS ARINC 429 Multichannel Receiver/ Transmitter

Description

The TS68C429A is an ARINC 429 controller. It is an enhanced version of the EF 4442 and it is designed to be connec ted to the new 16- or 32- bit microproc essors, especially these of the

Atmel TS68K family.

Screening

• MIL-STD-883, clas s B

• DESC Drawing 5962-955180

•

Atmel Standards

Application Note

• A detailed application note is available “AN 68C429A” on request.

R suffix PGA 84

Ceramic Pin Grid Array

Ceramic Quad Flat Pack

F suffix

CQFP 132

(MRT)

TS68C429A

Rev. 2120A–HIREL–08/0 2

Hardware Overview The TS68C429A is a h igh p erforma nce ARINC 429 c ontro ller d esig ned t o inte rface pri-

mary to the “Application Notes” on page 33). It can be connected to any TS68K processor family with an asynchronous bus with some additional logic in some cases.

As shown in Figure 1, the TS68C429A is divided into five main blocks, the microprocessor interface unit (MIU), the logical control unit (LCU), the interrupt control unit (ICU), the receiver channel unit (RCU) and the transmitter channel unit (TCU).

• The MIU handles the interface protocol of the host processor. Through this unit, the host sees the TS68C429A as a set of registers.

• The LCU controls the internal data flow and initializes the TS68C429A.

• The ICU manages one interrupt line for the RCU and one for the TCU. Each of these two parts has a daisy chain capability. All channels have a dedicated vectored interrupt answer. Receiver channels priority is programmable.

• The RCU is composed of 8 ARINC receiver channels made of: – a serial to parallel converter to translate the two serial signals (the “1” and “0”

– a memory to store the valid labels, – a control logic to check the validity of the received message, – a buffer to keep the last valid received message.

• The TCU is composed of three ARINC transmitter channels made of: – a parallel to serial converter to translate the messages into two serial signals

– a FIFO memory to store eight 32-bit ARINC messages, – a control logic to synchronize the message transmitter (parity, gap, speed,

• Test facility: Rx inputs can be internally connected to TX3 output.

• Self-test facility: The receiver control label matrix and transmitter FIFO can be tested. This self-test can be used to verify the integrity of the TS68C429A memories.

Atmel TS68K family microprocessor in a straight forward fash ion (see

in RZ code) into two 16-bit words,

(the “1” and “0” in RZ code),

etc.).

TS68C429A

2120A–HIREL–08/02

Figure 1. Simplified Block Diagram

TS68C429A

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Package See “Package Mechanical Data” on page 40 and “Terminal Connections” on page 41.

Figure 1. Signal Description

Pin Name Type Function

A0-8 I Address bus . The address bus is used to select one of the internal registers during a processor

read or write cycle.

D0-15 I/O This bi-directional bus is used to rece ive data from or transmit d ata to an intern al register during a

processor read or wri te c ycle. Du ring an in terru pt ac k now l edg e cy cl e, th e ve ctor number is given on the lower data bus (D0 - D7).

I Chip select (active low). This input is used to select the chip for internal register access. LDS UDS R/W I Read/write. This input defines a data transfer as a read (high) or a write (low) cycle. DTACK

IRQTX

IACKTX

IEITX

IEOTX

IRQRX

I Lower data strobe. This input (active low) validates lower data during R/W access (D0-D7).

I Upper data strobe. This input (active low) validates upper data during R/W access (D8-D15).

O Data transfer acknowledge. If the bus cycle is a processor read , the chip asser ts DTACK to

indicate that the information on the data bus is valid. If the bus cycle is a processor write, DTACK acknowledges the a cceptance of the data b y the MRT. DTACK access (CS

O Interrupt transmit request. This open drain output signals to the processor that an interrupt is

pending from the transmission part of the MRT. There are 6 causes that can generate an interrupt request (2 per channel: FIFO emp ty and end of transm is si on).

I Interrupt transmit acknowledge. If IRQTX is active, the MRT will begin an interrupt acknowledge

cycle. The MRT will generate a vector number to the processor which is the highest priority channel requesting interrupt service.

I Interrupt transmit enable in. This input, together with IEOTX signal, provides a daisy chained

interrupt structure for a vectored scheme. IEITX device is requesting interrupt service.

O Interrupt transmit enable out. This output, together with IEITX signal, provides a daisy chained

interrupt structure for a vectored interrupt scheme. IEOTX devices that neither the TS68C429A nor any highest priority peripheral is requesting an interrupt.

O Interrupt transmit request. This open drain output signals to the processor that an interrupt is

pending from the receiving part of the chip. There are 9 causes that can generate an interrupt request (1 per channel: valid message received, and 1 for bad parity on a received message).

asserted) or interrupt acknowledge cycle (IACKTX or IACKRK asserted).

(active low) indicates that no higher priority

will be asserted during chip selec t

(active low) indicates to lower priority

IACKRX IEIRX IEORX TX1H O Transmission “1” line of the channel 1. TX1L O Transmission “0” line of the channel 1. TX2H O Transmission “1” line of the channel 2. TX2L O Transmission “0” line of the channel 2. TX3H O Transmission “1” line of the channel 3. TX3L O Transmission “0” line of the channel 3. RX1H I Receivi ng “1” line of the channel 1. RX1L I Receiving “0” line of the chann el 1. RX2H I Receivi ng “1” line of the channel 2

TS68C429A

I Interrupt receive acknowledge. Same function as IACKTX but for receiver part.

I Interrupt receive enable in. Same function as IEITX but for receiver part.

I Interrupt receive enable out. Same function as IEOTX but for receiver part.

2120A–HIREL–08/02

Figure 1. Signal Description (Continued)

Pin Name Type Function

RX2L I Receiving “0” line of the chann el 2. RX3H I Receivi ng “1” line of the channel 3. RX3L I Receiving “0” line of the chann el 3. RX4H I Receivi ng “1” line of the channel 4. RX4L I Receiving “0” line of the chann el 4. RX5H I Receivi ng “1” line of the channel 5. RX5L I Receiving “0” line of the chann el 5. RX6H I Receivi ng “1” line of the channel 6. RX6L I Receiving “0” line of the chann el 6. RX7H I Receivi ng “1” line of the channel 7. RX7L I Receiving “0” line of the chann el 7. RX8H I Receivi ng “1” line of the channel 8. RX8L I Receiving “0” line of the chann el 8.

TS68C429A

RESET V

/GND I These inputs supply power to the chip. The VCC is powered at +5 volts and GND is the ground

CLK-SYS I The clock input is a single-phase signal used for internal timing of processor interface. CLK-ARINC I This input provides the timing clock to synchronize received/transmitted messaged.

I This input (active low) will initialize the TS68C429A registers.

connection.

2120A–HIREL–08/02

Figure 2 illustrates the functional signal groups.

Figure 2. Functional Signal Groups Diagram

Scope This drawing describes the specified requiremen ts for the ARINC multi channel

receiver/transmitter, in compliance either with MIL-STD-863 class B or SMD drawing.

Applicable Documents

MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics

2. MIL-STD-38535: general spe cifi cat ion s for micr oci rcui ts .

3. MIL-STD-1835 microcircuit case outlines.

4. DESC/SMD.

Requirements

General The microcircu its are in accordanc e with the applicabl e document and as s pecified

herein.

TS68C429A

2120A–HIREL–08/02

TS68C429A

Design and Construction

Terminal Connections Depending on the package, the terminal connections is detailed in “Terminal Connec-

tions” on page 41.

Package The circuits are packaged in a hermetically sealed ceramic package which is conform to

case outlines of MIL-STD 1835 (when defined):

• PGA 84,

• CQFP 132. The precise case outlines are described at the end of this specification (“Package

Mechanical Data” on page 40) and into MIL-STD-1835.

Special R ecommended Conditions for CMOS Devices

• The CMOS cell is basically composed of two complementary tr ansistors (a P-channe l

and an N-channel), an d, i n the ste ady s tate , onl y one trans istor i s turn ed- on . The a ct ive P-channel transistor sources current when the output is a logic high and presents a high impedance when the output is a logic low. Thus the overall result is extremely low power consumption beca use ther e is no power l oss throu gh the a ctive P- channel transis tor. Also since only once transistor is determined by leakage currents.

Because the basic CMOS cell is composed of two complementary transistors, a parasitic semiconductor controlled rectifier (SCR) formed and may be triggered when an input exceeds the supp ly vo ltage. T he SCR that is fo rmed b y this hig h input cau ses the device to become “latched” in a mode that may result in excessive current drain and eventual destruction of the device. Although the device is implemented with input protection diodes, care should be exercised to ensure that the maximum input voltages specification is not exceeded from voltage transients; others may require no additional circuitry.

• The TS68C429 A doesn’ t sati sfy tot ally the input/o utput d rive re quirem ents of TTL log ic

devices, see Table 4.

Electrical Characteristics

Table 1. Absolute Maximum Ratings

CMOS Latch-up

CMOS/TTL Levels

Symbol Parameter Test Conditions Min Max Unit

dmax

case

stg

leads

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Supply Voltage -0.3 +7.0 V Input Voltage -0.3 +7.0 V Max Power Dissipation 400 mW

M suffix -55 +125 °C

Operating Temperature

V suffix -40 +85 °C Storage Temperature -55 +150 °C Junction Temperature +160 °C Lead Temperature Max 5 sec. soldering +270 °C

Unless otherwise stated, all voltages are referenced to the reference terminal.

Table 2. Recommended Condition of Use

Symbol Parameter Test conditions Min Max Units

Supply Voltage 4.5 5.5 V Low Level Input Voltage -0.5 0.8 V High Level Input Voltage 2.25 5.8 V

M suffix -55 +125 °C

case

Operating Temperature

V suffix -40 +85 °C

Output Loading Capacita nce 130 pF

Clock System Frequency (See Figure 3)

0.5 20 MHz

This device contains protective circuitry against damage due to high static voltages or electrical fields: however, it is advised that normal precautions be taken to avoid application of any voltages hig her than maximum-rated vol tage s to this hi gh-i mpe dan ce circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).

Figure 3. Clock Input Timing Diagram

cyc

2.25V

0.8V

Note: Timing measurements are referenced to and from a low of 0.8-volt and a high voltage of

2.25 volts, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between

0.8-volt and 2.25 volts.

Table 3. Thermal Characteristics

Package Symbol Parameter Value Unit

PGA 68

CQFP 132

J-A

J-C

J-A

J-C

Thermal Resistance Jun c tion-to-ambient 28 °C/W Thermal Resistance Junction-to-case 2 °C/W Thermal Resistance Jun c tion-to-ambient 27 °C/W Thermal Resistance Junction-to-case 3 °C/W

TS68C429A

2120A–HIREL–08/02

TS68C429A

Power Considerations The average chip-junction tempe ra tur e, TJ, in °C can be obtained from:

= TA + (PD ⋅ θJA)(1)

= Ambient Temperature, °C

= Package Thermal Resistance, Junction-to-Ambient, °C/W

= P

INT

I/O

For most application s P An approximate relationship between P

Solving equations (1) and (2) for K gives:

where K is a constant pertaining to the particular part K can be determined from equation (3) by measuring P values of P value of T

The total thermal res istance of a pack age ( θ

package (case), surface (θ terms are related by the equation:

dent and can be minimized by such thermal management techniques as heat sinks, ambient air cooling and thermal co nvection. Thu s, good thermal managemen t on the part of the user can significantly reduce θ tution of θ temperature.

+ P

INT

I/O

= ICC x VCC, Watts—Chip Internal Power

= Power Dissipation on Input and Output Pins—User Determined

< P

I/O

= K: (TJ + 273) (2)

K = P

⋅ (TA + 273) + θJA ⋅ P

and TJ can be obtained by sol ving equ ations (1) and (2) it erativ ely for an y

and can be neglected.

INT

and TJ (if P

is neglected) is:

I/O

(3)

(at equilibriu m) for a known TA. Using this value of K, the

) can be separated into two components,

and θCA, representing the barrier to heat flow from the semiconductor junction to the

) and from the case to the outside ambient (θCA). These

= θJC + θ

(4)

is device related and cannot be influenced by the user. However, θCA is user depen-

so that θJA approximately equals θJC. Substi-

for θJA in equation (1) will result in a lower s emiconductor junction

Mechanical and Environment

The microcircuits shall meet all mechanical environmental requirements of either MILSTD-883 for class B devices or DESC devices.

Marking The document where are defined the marking are identified in the related reference doc-

uments. Each mic rocircuit are legib ly and permanentl y marked with the follow ing information as minimum:

•Atmel logo

• Manufacturer’s part number

• Class B identification

• Date-code of inspection lot

• ESD identifier if available

• Country of manufacturing

2120A–HIREL–08/02

Quality Conformance Inspection

DESC/MIL-STD-883 Is in accordance with MIL -M-3851 0 and met hod 50 05 of MIL-S TD-883 . Grou p A and B

inspections are performed on each production lot. Group C and D inspections are performed on a periodic basis.

Electrical Characteristics

General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the

relevant measurement conditions are given below:

• Table 4, Table 5: Static electrical characteristics for the electrical variants.

• Table 6, Table 7, Table 8: Dynamic electrical characteristics. For static characteristics (Table 4, Table 5), test methods refer to IEC 748-2 method

number, where existing. For dynamic characteristics (Table 6, Table 7, Table 8), test methods refer to clause 5. 5

of this specification.

Table 4. DC Electrical Characteristics With -55

°C ≤ T

≤ +125°C or -40° ≤ T

case

≤ +85°C; VCC = 5V ± 10%.

case

Symbol Parameter Min Max Unit

IDD Dynamic Current

Input High Voltage 2.25 VCC + 0.3 V Input Low Voltage -0.5 0.8 V Output High Voltage (exc ep t IR QRX, IRQTX: open drain outputs) 2.7 V Output Low Voltage 0.5 V Output Source Current (except IRQRX,

: open drain outputs)

IRQTX Output Sink Current (V

= 2.7V) -8 mA

out

= 0.5V) 8 mA

out

Input Leakage Current (Vin = 0 to VCC) ±20 µA

= T

(1)

case

min

= V

⋅ V

max

)

65 mA

Note: 1. IDD is measured with all I/O pins at 0V, all input pins at 0V except signals CS, IACKxx, LDS, UDS at 5V and CLK-SYS and

CLK-ARINC which run at t

cyc

mini.

Table 5. Capacitance (TA = 25°C)

Symbol Parameter Max Unit

out

Input Capacitance 10 pF HI-Z Output Capacitance 20 pF

TS68C429A

2120A–HIREL–08/02

Clock Timing

Table 6. Clock System (CLK SYS)

Symbol Parameter Min Max Unit

S Clock Period 50 2000 ns

cyc

, t

CLS

CHS

, t

crS

cfS

Table 7. Clock ARINC (CLK ARINC)

Symbol Parameter Min Max Unit

ACycle Time

cyc

, t

CLA

CHA

, t

crA

cfA

Note: 1. t

A ≥ 4 x t

cyc

Clock Pulse Width 20 ns Rise and Fall Times 5 ns

Clock Pulse Width 240 ns Rise and Fall Times 5 ns

TS68C429A

(1)

200 8000 ns

AC Electrical Characteristics

Figure 4. Read Cycle

With VCC = 5 VDC ± 10% VSS = 0 VDC. IEIxx

, IEOxx, IACKxx, must be understood as generic signals (xx = RX and TX).

Notes: 1. LDS/UDS can be asserted on the next or previous CLK-SYS period after CS goes low but (4) must be met for the next

period.

2. The cycle ends when the first of CS

, LDS/UDS goes high.

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Figure 5. Write Cycle

3. LDS/UDS can be asserted on the same or previous CLK-SYS period as CS but (3) and (4) must be met.

Figure 6. Interrupt Cycle (IEIxx = 0)

Notes: 1. If UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value.

2. If IEOxx DTACK

TS68C429A

goes low, neither ve cto r nor DTAC K are generate d, els e IEOxx stays inactive and a vector is generated (D7-D0 and

2120A–HIREL–08/02

Figure 7. Interrupt Cycle (IEIxx = 1)

Notes: 1. If UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value.

2. If IEOxx DTACK

goes low, neither ve cto r nor DTAC K are generate d, els e IEOxx stays inactive and a vector is generated (D7-D0 and

TS68C429A

Table 8. Timing Characteristic

Number Symbol Parameter Min Max T/G

1t 2t 3t 4t 5t 6t 7t 8t

9t 10 t 11 t 12 t 13 t 14 t 15 t 16 t 17 t

AVCSL

RWVCSL

DIVDSL

SVCL

CLDKL

CLDOV

DKLDOV

SHDKH

SHDXZ

SHDOZ

ILIOL

IKHIOH

IILDKL

IILDOV

DKLSH

SHAH

Address valid to CS low 0 - T ns R/W valid to CS low 0 - T ns Data in valid to LDS/UDS low 0 - T ns CS, LDS/UDS, IACKxx valid to CLK-SYS low 5 - T ns CLK-SYS low to DTACK low - 45 T ns CLK-SYS low to data out valid - 50 T ns DTACK low to data out valid - 10 G ns CS or LDS/UDS or IACKxx high to DTACK high - 35 G ns CS or LDS/UDS or IACKxx high to DTACK hi-z - 50 G ns CS or LDS/UDS or IACKxx high to data out hi-z - 25 G ns IEIxx or IACKxx low to IEOxx low - 35 T ns IACKxx high to IEOxx h igh - 40 T ns IEIxx low to DTACK low - 40 T ns IEIxx low to data out valid - 45 T ns CS, IACKxx, LDS/UDS inactive time 15 - T ns DTACK low to CS or LDS/UDS or IACKxx high 0 - G ns CS or LDS/UDS high to address hold time 0 - G ns

(1)

Unit

2120A–HIREL–08/02

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