Atmel GSB User Manual

Instruction Set Nomenclature

Status Register (SREG)

SREG: Status Register

C: Carry Flag

Z: Zero Flag

N: Negative Flag

V: Two’s complement overflow indicator

S: N ⊕ V, For signed tests

H: Half Carry Flag

T: Transfer bit used by BLD and BST instructions

I: Global Interrupt Enable/Disable Flag

Registers and Operands

Rd: Destination (and source) register in the Register File

Rr: Source register in the Register File

R: Result after instruction is executed

K: Constant data

k: Constant address

b: Bit in the Register File or I/O Register (3-bit)

s: Bit in the Status Register (3-bit)

X,Y,Z: Indirect Address Register

(X=R27:R26, Y=R29:R28 and Z=R31:R30)

8-bit

Instruction Set

A: I/O location address

q: Displacement for direct addressing (6-bit)

Rev. 0856I–AVR–07/10

I/O Registers

RAMPX, RAMPY, RAMPZ

Registers concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space on MCUs with
more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.

RAMPD

Register concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with more than 64K
bytes data space.

EIND

Register concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs with more
than 64K words (128K bytes) program space.

Stack

STACK: Stack for return address and pushed registers

SP: Stack Pointer to STACK

Flags

⇔: Flag affected by instruction

0: Flag cleared by instruction

1: Flag set by instruction

-: Flag not affected by instruction

2

AVR Instruction Set

0856I–AVR–07/10

AVR Instruction Set

The Program and Data Addressing Modes

The AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Program
memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory). This section describes
the various addressing modes supported by the AVR architecture. In the following figures, OP means the operation code
part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To generalize, the
abstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space,
respectively.

Note: Not all addressing modes are present in all devices. Refer to the device spesific instruction summary.

Register Direct, Single Register Rd

Figure 1. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two Registers Rd and Rr

Figure 2. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

0856I–AVR–07/10

3

I/O Direct

OP Rr/Rd

16

31

15 0

Data Address

0x0000

RAMEND

20 19

Data Space

Figure 3. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

Note: Some complex AVR Microcontrollers have more peripheral units than can be supported within the 64 locations reserved in the

opcode for I/O direct addressing. The extended I/O memory from address 64 to 255 can only be reached by data addressing,
not I/O addressing.

Data Direct

Figure 4. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source
register.

4

AVR Instruction Set

0856I–AVR–07/10

AVR Instruction Set

Data Space

0x0000

RAMEND

Y OR Z - REGISTER

OP qRr/Rd

0

05610

15

15

Data Space

0x0000

X, Y OR Z - REGISTER

015

RAMEND

Data Indirect with Displacement

Figure 5. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instruction
word. Rd/Rr specify the destination or source register.

Data Indirect

Figure 6. Data Indirect Addressing

Operand address is the contents of the X-, Y-, or the Z-register. In AVR devices without SRAM, Data Indirect Addressing is
called Register Indirect Addressing. Register Indirect Addressing is a subset of Data Indirect Addressing since the data
space form 0 to 31 is the Register File.

0856I–AVR–07/10

5

Data Indirect with Pre-decrement

Data Space

0x0000

X, Y OR Z - REGISTER

015

-1

RAMEND

Data Space

0x0000

X, Y OR Z - REGISTER

015

1

RAMEND

Figure 7. Data Indirect Addressing with Pre-decrement

The X,- Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-,
Y-, or the Z-register.

Data Indirect with Post-increment

Figure 8. Data Indirect Addressing with Post-increment

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-regis­ter prior to incrementing.

6

AVR Instruction Set

0856I–AVR–07/10

AVR Instruction Set

FLASHEND

0x0000

LSB

FLASHEND

0x0000

1

LSB

Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions

Figure 9. Program Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. For LPM, the LSB selects
low byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the LSB should be cleared. If ELPM is used, the
RAMPZ Register is used to extend the Z-register.

Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction

Figure 10. Program Memory Addressing with Post-increment

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. The LSB selects low byte
if cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.

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7

Direct Program Addressing, JMP and CALL

FLASHEND

31 16

OP 6 MSB

16 LSB

PC

21 0

15 0

0x0000

FLASHEND

PC

15 0

0x0000

Figure 11. Direct Program Memory Addressing

Program execution continues at the address immediate in the instruction word.

Indirect Program Addressing, IJMP and ICALL

Figure 12. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z­register).

8

AVR Instruction Set

0856I–AVR–07/10

AVR Instruction Set

FLASHEND

1

0x0000

Relative Program Addressing, RJMP and RCALL

Figure 13. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047.

0856I–AVR–07/10

9

Conditional Branch Summary

Test Boolean Mnemonic Complementary Boolean Mnemonic Comment

Rd > Rr Z•(N ⊕ V) = 0 BRLT

Rd  Rr (N ⊕ V) = 0 BRGE Rd < Rr (N ⊕ V) = 1 BRLT Signed

Rd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE Signed

Rd ≤ Rr Z+(N ⊕ V) = 1 BRGE

Rd < Rr (N ⊕ V) = 1 BRLT Rd ≥ Rr (N ⊕ V) = 0 BRGE Signed

Rd > Rr C + Z = 0 BRLO

Rd  Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS Unsigned

Rd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE Unsigned

Rd ≤ Rr C + Z = 1 BRSH

Rd < Rr C = 1 BRLO/BRCS Rd ≥ Rr C = 0 BRSH/BRCC Unsigned

Carry C = 1 BRCS No carry C = 0 BRCC Simple

Negative N = 1 BRMI Positive N = 0 BRPL Simple

Overflow V = 1 BRVS No overflow V = 0 BRVC Simple

Zero Z = 1 BREQ Not zero Z = 0 BRNE Simple

Note: 1. Interchange Rd and Rr in the operation before the test, i.e., CP Rd,Rr → CP Rr,Rd

(1)

(1)

(1)

(1)

Rd ≤ Rr Z+(N ⊕ V) = 1 BRGE* Signed

Rd > Rr Z•(N ⊕ V) = 0 BRLT* Signed

Rd ≤ Rr C + Z = 1 BRSH* Unsigned

Rd > Rr C + Z = 0 BRLO* Unsigned

10

AVR Instruction Set

0856I–AVR–07/10

Complete Instruction Set Summary

Instruction Set Summary

AVR Instruction Set

Mnemonics Operands Description Operation Flags #Clocks

Arithmetic and Logic Instructions

ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1

ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1

(1)

ADIW

SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1

SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1

SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1

SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1

(1)

SBIW

AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1

ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1

OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1

ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1

EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1

COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1

NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1

INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1

DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1

SER Rd Set Register Rd ← $FF None 1

(1)

MUL

(1)

MULS

MULSU

(1)

FMUL

FMULS

FMULSU

DES K Data Encryption if (H = 0) then R15:R0

RJMP k Relative Jump PC ← PC + k + 1 None 2

(1)

IJMP

(1)

EIJMP

(1)

JMP

Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2

Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2

Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2

Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2

(1)

Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2

Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2

(1)

Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2

(1)

Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2

else if (H = 1) then R15:R0←←

Branch Instructions

Indirect Jump to (Z) PC(15:0)

Extended Indirect Jump to (Z) PC(15:0)

kJump PC← kNone3

PC(21:16)←←Z,0

PC(21:16)←←Z,EIND

Encrypt(R15:R0, K)
Decrypt(R15:R0, K)

None 2

None 2

#Clocks
XMEGA

1/2

0856I–AVR–07/10

11

(3)(5)

(3)

(3)

(3)

(3)

#Clocks
XMEGA

(3)

2 / 3

(3)

2 / 3

(3)

3

(3)

3 / 4

Mnemonics Operands Description Operation Flags #Clocks

RCALL k Relative Call Subroutine PC ← PC + k + 1 None 3 / 4

(1)

ICALL

EICALL

CALL

(1)

(1)

k call Subroutine PC ← kNone4 / 5

Indirect Call to (Z) PC(15:0)

Extended Indirect Call to (Z) PC(15:0)

PC(21:16)←←Z,0

PC(21:16)←←Z,EIND

None 3 / 4

None 4

(3)

RET Subroutine Return PC ← STACK None 4 / 5

RETI Interrupt Return PC ← STACK I 4 / 5

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4

SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None 1 / 2 / 3 2 / 3 / 4

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1 / 2

Data Transfer Instructions

MOV Rd, Rr Copy Register Rd ← Rr None 1

(1)

MOVW

Rd, Rr Copy Register Pair Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← KNone1

LDS

LD

(1)

(2)

Rd, k Load Direct from data space Rd ← (k) None 1

Rd, X Load Indirect Rd ← (X) None 1

(5)/2(3)

(5)2(3)

(3)(4)

2

(3)(4)

1

12

AVR Instruction Set

0856I–AVR–07/10

AVR Instruction Set

Mnemonics Operands Description Operation Flags #Clocks

(2)

LD

(2)

LD

(2)

LD

(2)

LD

(2)

LD

LDD

(2)

LD

(2)

LD

(2)

LD

LDD

STS

(2)

ST

(2)

ST

(2)

ST

(2)

ST

(2)

ST

(2)

ST

STD

(2)

ST

(2)

ST

(2)

ST

STD

LPM

LPM

LPM

ELPM

ELPM

ELPM

SPM

SPM

(1)

(1)

(1)

(1)

(1)

(1)(2)

(1)(2)

(1)(2)

(1)

(1)

Rd, X+ Load Indirect and Post-Increment RdX←←(X)

Rd, -X Load Indirect and Pre-Decrement X ← X - 1,

Rd ← (X)←←

X + 1

X - 1
(X)

None 2

None 2

Rd, Y Load Indirect Rd ← (Y) ← (Y) None 1

Rd, Y+ Load Indirect and Post-Increment RdY←←(Y)

Rd, -Y Load Indirect and Pre-Decrement YRd←←Y - 1

Y + 1

(Y)

None 2

None 2

Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

Rd, Z Load Indirect Rd ← (Z) None 1

Rd, Z+ Load Indirect and Post-Increment RdZ←←(Z),

Rd, -Z Load Indirect and Pre-Decrement ZRd←←Z - 1,

Z+1

(Z)

None 2

None 2

Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

k, Rr Store Direct to Data Space (k) ← Rd None 1

X, Rr Store Indirect (X) ← Rr None 1

X+, Rr Store Indirect and Post-Increment (X)X←←Rr,

-X, Rr Store Indirect and Pre-Decrement X
(X)←←

X + 1

X - 1,
Rr

None 1

None 2

Y, Rr Store Indirect (Y) ← Rr None 1

Y+, Rr Store Indirect and Post-Increment (Y)Y←←Rr,

-Y, Rr Store Indirect and Pre-Decrement Y
(Y)←←

Y + 1

Y - 1,
Rr

None 1

None 2

Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2

Z, Rr Store Indirect (Z) ← Rr None 1

Z+, Rr Store Indirect and Post-Increment (Z)Z←←Rr

Z + 1

None 1

-Z, Rr Store Indirect and Pre-Decrement Z ← Z - 1 None 2

Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

Load Program Memory R0 ← (Z) None 3 3

Rd, Z Load Program Memory Rd ← (Z) None 3 3

Rd, Z+ Load Program Memory and Post-

(1)

(1)

(1)

Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3

Rd, Z+ Extended Load Program Memory and

Increment

Extended Load Program Memory R0 ← (RAMPZ:Z) None 3

Post-Increment

RdZ←←(Z),

RdZ←←(RAMPZ:Z),

Z + 1

Z + 1

None 3 3

None 3

Store Program Memory (RAMPZ:Z) ← R1:R0 None - -

Z+ Store Program Memory and Post-

Increment by 2

(RAMPZ:Z)Z←←R1:R0,

Z + 2

None - -

(3)

(3)/3(5)

(5)/2(3)

(3)

(3)/3(5)

(3)

(5)/2(3)

(3)

(3)/3(5)

(3)

(5)/2(3)

(5)/2(3)

(5)/2(3)

(3)

(5)/2(3)

(5)/2(3)

(3)

(3)

(5)/2(3)

(5)/2(3)

(3)

(3)

IN Rd, A In From I/O Location Rd ← I/O(A) None 1

OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1

(1)

PUSH

POP

(1)

Rr Push Register on Stack STACK ← Rr None 2 1

Rd Pop Register from Stack Rd ← STACK None 2 2

#Clocks
XMEGA

(3)(4)

1

(3)(4)

2

(3)(4)

1

(3)(4)

1

(3)(4)

2

(3)(4)

2

(3)(4)

1

(3)(4)

1

(3)(4)

2

(3)(4)

2

(3)

2

(3)

1

(3)

1

(3)

2

(3)

1

(3)

1

(3)

2

(3)

2

(3)

1

(3)

1

(3)

2

(3)

2

(3)

(3)

0856I–AVR–07/10

13

Mnemonics Operands Description Operation Flags #Clocks

XCH Z, Rd Exchange (Z)Rd←←Rd,

LAS Z, Rd Load and Set (Z)Rd←←Rd v (Z)

LAC Z, Rd Load and Clear (Z)Rd←←($FF – Rd) • (Z)

LAT Z, Rd Load and Toggle (Z)Rd←←Rd ⊕ (Z)

Bit and Bit-test Instructions

LSL Rd Logical Shift Left Rd(n+1)

LSR Rd Logical Shift Right Rd(n)

ROL Rd Rotate Left Through Carry Rd(0)

ROR Rd Rotate Right Through Carry Rd(7)

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1

BSET s Flag Set SREG(s) ← 1SREG(s)1

BCLR s Flag Clear SREG(s) ← 0SREG(s)1

SBI A, b Set Bit in I/O Register I/O(A, b) ← 1None1

CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0None1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0C1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0N1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0Z1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0I1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0S1

SEV Set Two’s Complement Overflow V ← 1V1

CLV Clear Two’s Complement Overflow V ← 0V1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0T1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0H1

MCU Control Instructions

(1)

BREAK

Break (See specific descr. for BREAK) None 1

Rd(0)

Rd(7)

Rd(n+1)

Rd(n)

C

C

C

C

←
←
←

←
←
←

←
←
←

←
←
←

(Z)

(Z)

(Z)

(Z)

Rd(n),
0,
Rd(7)

Rd(n+1),
0,
Rd(0)

C,
Rd(n),
Rd(7)

C,
Rd(n+1),
Rd(0)

None 1

None 1

None 1

None 1

Z,C,N,V,H 1

Z,C,N,V 1

Z,C,N,V,H 1

Z,C,N,V 1

(5)

21

(5)

/2 1

#Clocks
XMEGA

14

AVR Instruction Set

0856I–AVR–07/10

AVR Instruction Set

Mnemonics Operands Description Operation Flags #Clocks

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep) None 1

WDR Watchdog Reset (see specific descr. for WDR) None 1

Notes: 1. This instruction is not available in all devices. Refer to the device specific instruction set summary.

2. Not all variants of this instruction are available in all devices. Refer to the device specific instruction set summary.

3. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external
RAM interface.

4. One extra cycle must be added when accessing Internal SRAM.

5. Number of clock cycles for Reduced Core tinyAVR.

#Clocks
XMEGA

0856I–AVR–07/10

15

ADC – Add with Carry

Description:

Adds two registers and the contents of the C Flag and places the result in the destination register Rd.

Operation:

(i) Rd ← Rd + Rr + C

Syntax: Operands: Program Counter:

(i) ADC Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0001 11rd dddd rrrr

Status Register (SREG) Boolean Formula:

ITHSVNZC

––⇔⇔⇔⇔⇔⇔

H: Rd3•Rr3+Rr3•R3

+R3•Rd3

Set if there was a carry from bit 3; cleared otherwise

S: N ⊕ V, For signed tests.

V: Rd7•Rr7•R7

+Rd7•Rr7•R7

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N: R7

Set if MSB of the result is set; cleared otherwise.

Z: R7

• R6 •R5• R4 •R3 •R2 •R1 •R0

Set if the result is $00; cleared otherwise.

C: Rd7•Rr7+Rr7•R7

+R7•Rd7

Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

; Add R1:R0 to R3:R2

add r2,r0 ; Add low byte

adc r3,r1 ; Add with carry high byte

Words: 1 (2 bytes)
Cycles: 1

16

AVR Instruction Set

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AVR Instruction Set

ADD – Add without Carry

Description:

Adds two registers without the C Flag and places the result in the destination register Rd.

Operation:

(i) Rd ← Rd + Rr

Syntax: Operands: Program Counter:

(i) ADD Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0000 11rd dddd rrrr

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––⇔⇔⇔⇔⇔⇔

H: Rd3•Rr3+Rr3•R3

+R3•Rd3

Set if there was a carry from bit 3; cleared otherwise

S: N ⊕ V, For signed tests.

V: Rd7•Rr7•R7

+Rd7•Rr7•R7

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N: R7

Set if MSB of the result is set; cleared otherwise.

Z: R7

• R6 •R5• R4 •R3 •R2 •R1 •R0

Set if the result is $00; cleared otherwise.

C: Rd7 •Rr7 +Rr7 •R7

+ R7 •Rd7

Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

add r1,r2 ; Add r2 to r1 (r1=r1+r2)

add r28,r28 ; Add r28 to itself (r28=r28+r28)

Words: 1 (2 bytes)
Cycles: 1

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ADIW – Add Immediate to Word

Description:

Adds an immediate value (0 - 63) to a register pair and places the result in the register pair. This instruction operates on the
upper four register pairs, and is well suited for operations on the pointer registers.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) Rd+1:Rd ← Rd+1:Rd + K

Syntax: Operands: Program Counter:

(i) ADIW Rd+1:Rd,K d ∈ {24,26,28,30}, 0 ≤ K ≤ 63 PC ← PC + 1

16-bit Opcode:

1001 0110 KKdd KKKK

Status Register (SREG) and Boolean Formula:

ITHSVNZC

–– –⇔⇔⇔⇔⇔

S: N ⊕ V, For signed tests.

V: Rdh7

• R15

Set if two’s complement overflow resulted from the operation; cleared otherwise.

N: R15

Set if MSB of the result is set; cleared otherwise.

Z: R15

•R14 •R13 •R12 •R11 •R10 •R9 •R8 •R7• R6• R5• R4• R3• R2 •R1• R0

Set if the result is $0000; cleared otherwise.

C: R15

• Rdh7

Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rdh:Rdl after the operation (Rdh7-Rdh0 = R15-R8, Rdl7-Rdl0=R7-R0).

Example:

adiw r25:24,1 ; Add 1 to r25:r24

adiw ZH:ZL,63 ; Add 63 to the Z-pointer(r31:r30)

Words: 1 (2 bytes)
Cycles: 2

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AVR Instruction Set

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AVR Instruction Set

AND – Logical AND

Description:

Performs the logical AND between the contents of register Rd and register Rr and places the result in the destination regis­ter Rd.

Operation:

(i) Rd ← Rd • Rr

Syntax: Operands: Program Counter:

(i) AND Rd,Rr 0 ≤ d ≤ 31, 0 ≤ r ≤ 31 PC ← PC + 1

16-bit Opcode:

0010 00rd dddd rrrr

Status Register (SREG) and Boolean Formula:

ITHSVNZC

–– –⇔ 0 ⇔⇔ –

S: N ⊕ V, For signed tests.

V: 0

Cleared

N: R7

Set if MSB of the result is set; cleared otherwise.

Z: R7

•R6 •R5 •R4 •R3• R2 •R1 •R0

Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

and r2,r3 ; Bitwise and r2 and r3, result in r2

ldi r16,1 ; Set bitmask 0000 0001 in r16

and r2,r16 ; Isolate bit 0 in r2

Words: 1 (2 bytes)
Cycles: 1

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ANDI – Logical AND with Immediate

Description:

Performs the logical AND between the contents of register Rd and a constant and places the result in the destination regis­ter Rd.

Operation:

(i) Rd ← Rd • K

Syntax: Operands: Program Counter:

(i) ANDI Rd,K 16 ≤ d ≤ 31, 0 ≤ K ≤ 255 PC ← PC + 1

16-bit Opcode:

0111 KKKK dddd KKKK

Status Register (SREG) and Boolean Formula:

ITHSVNZC

–– –⇔

0

⇔⇔ –

S: N ⊕ V, For signed tests.

V: 0

Cleared

N: R7

Set if MSB of the result is set; cleared otherwise.

Z: R7

•R6• R5•R4 •R3• R2• R1• R0

Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

andi r17,$0F ; Clear upper nibble of r17

andi r18,$10 ; Isolate bit 4 in r18

andi r19,$AA ; Clear odd bits of r19

Words: 1 (2 bytes)
Cycles: 1

20

AVR Instruction Set

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AVR Instruction Set

b7-------------------b0 C

ASR – Arithmetic Shift Right

Description:

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C Flag of the SREG. This operation
effectively divides a signed value by two without changing its sign. The Carry Flag can be used to round the result.

Operation:

(i)

Syntax: Operands: Program Counter:

(i) ASR Rd 0 ≤ d ≤ 31 PC ← PC + 1

16-bit Opcode:

1001 010d dddd 0101

Status Register (SREG) and Boolean Formula:

ITHSVNZC

–– –⇔⇔⇔⇔⇔

S: N ⊕ V, For signed tests.

V: N ⊕ C (For N and C after the shift)

N: R7

Set if MSB of the result is set; cleared otherwise.

Z: R7

•R6 •R5• R4 •R3 •R2• R1• R0

Set if the result is $00; cleared otherwise.

C: Rd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

ldi r16,$10 ; Load decimal 16 into r16

asr r16 ; r16=r16 / 2

ldi r17,$FC ; Load -4 in r17

asr r17 ; r17=r17/2

Words: 1 (2 bytes)
Cycles: 1

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BCLR – Bit Clear in SREG

Description:

Clears a single Flag in SREG.

Operation:

(i) SREG(s) ← 0

Syntax: Operands: Program Counter:

(i) BCLR s 0 ≤ s ≤ 7PC ← PC + 1

16-bit Opcode:

1001 0100 1sss 1000

Status Register (SREG) and Boolean Formula:

ITHSVNZC

⇔⇔⇔⇔⇔⇔⇔⇔

I: 0 if s = 7; Unchanged otherwise.

T: 0 if s = 6; Unchanged otherwise.

H: 0 if s = 5; Unchanged otherwise.

S: 0 if s = 4; Unchanged otherwise.

V: 0 if s = 3; Unchanged otherwise.

N: 0 if s = 2; Unchanged otherwise.

Z: 0 if s = 1; Unchanged otherwise.

C: 0 if s = 0; Unchanged otherwise.

Example:

bclr 0 ; Clear Carry Flag

bclr 7 ; Disable interrupts

Words: 1 (2 bytes)
Cycles: 1

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AVR Instruction Set

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AVR Instruction Set

BLD – Bit Load from the T Flag in SREG to a Bit in Register

Description:

Copies the T Flag in the SREG (Status Register) to bit b in register Rd.

Operation:

(i) Rd(b) ← T

Syntax: Operands: Program Counter:

(i) BLD Rd,b 0 ≤ d ≤ 31, 0 ≤ b ≤ 7PC ← PC + 1

16 bit Opcode:

1111 100d dddd 0bbb

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Example:

; Copy bit

bst r1,2 ; Store bit 2 of r1 in T Flag

bld r0,4 ; Load T Flag into bit 4 of r0

Words: 1 (2 bytes)
Cycles: 1

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BRBC – Branch if Bit in SREG is Cleared

Description:

Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is cleared. This instruction
branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is
represented in two’s complement form.

Operation:

(i) If SREG(s) = 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRBC s,k 0 ≤ s ≤ 7, -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if condition is false

16-bit Opcode:

1111 01kk kkkk ksss

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Example:

cpi r20,5 ; Compare r20 to the value 5

brbc 1,noteq ; Branch if Zero Flag cleared

...

noteq:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)
Cycles: 1 if condition is false

2 if condition is true

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AVR Instruction Set

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AVR Instruction Set

BRBS – Branch if Bit in SREG is Set

Description:

Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is set. This instruction
branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is
represented in two’s complement form.

Operation:

(i) If SREG(s) = 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRBS s,k 0 ≤ s ≤ 7, -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if condition is false

16-bit Opcode:

1111 00kk kkkk ksss

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Example:

bst r0,3 ; Load T bit with bit 3 of r0

brbs 6,bitset ; Branch T bit was set

...

bitset: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)
Cycles: 1 if condition is false

2 if condition is true

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BRCC – Branch if Carry Cleared

Description:

Conditional relative branch. Tests the Carry Flag (C) and branches relatively to PC if C is cleared. This instruction branches
relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is repre­sented in two’s complement form. (Equivalent to instruction BRBC 0,k).

Operation:

(i) If C = 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRCC k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if condition is false

16-bit Opcode:

1111 01kk kkkk k000

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Example:

add r22,r23 ; Add r23 to r22

brcc nocarry ; Branch if carry cleared

...

nocarry: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)
Cycles: 1 if condition is false

2 if condition is true

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AVR Instruction Set

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AVR Instruction Set

BRCS – Branch if Carry Set

Description:

Conditional relative branch. Tests the Carry Flag (C) and branches relatively to PC if C is set. This instruction branches rel­atively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented
in two’s complement form. (Equivalent to instruction BRBS 0,k).

Operation:

(i) If C = 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRCS k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if condition is false

16-bit Opcode:

1111 00kk kkkk k000

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Example:

cpi r26,$56 ; Compare r26 with $56

brcs carry ; Branch if carry set

...

carry: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)
Cycles: 1 if condition is false

2 if condition is true

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BREAK – Break

Description:

The BREAK instruction is used by the On-chip Debug system, and is normally not used in the application software. When
the BREAK instruction is executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip Debugger access to
internal resources.

If any Lock bits are set, or either the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK instruc­tion as a NOP and will not enter the Stopped mode.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) On-chip Debug system break.

Syntax: Operands: Program Counter:

(i) BREAK None PC ← PC + 1

16-bit Opcode:

1001 0101 1001 1000

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Words: 1 (2 bytes)
Cycles: 1

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AVR Instruction Set

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AVR Instruction Set

BREQ – Branch if Equal

Description:

Conditional relative branch. Tests the Zero Flag (Z) and branches relatively to PC if Z is set. If the instruction is executed
immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned or signed
binary number represented in Rd was equal to the unsigned or signed binary number represented in Rr. This instruction
branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is
represented in two’s complement form. (Equivalent to instruction BRBS 1,k).

Operation:

(i) If Rd = Rr (Z = 1) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BREQ k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if condition is false

16-bit Opcode:

1111 00kk kkkk k001

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Example:

cp r1,r0 ; Compare registers r1 and r0

breq equal ; Branch if registers equal

...

equal: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)
Cycles: 1 if condition is false

2 if condition is true

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BRGE – Branch if Greater or Equal (Signed)

Description:

Conditional relative branch. Tests the Signed Flag (S) and branches relatively to PC if S is cleared. If the instruction is exe­cuted immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the signed binary
number represented in Rd was greater than or equal to the signed binary number represented in Rr. This instruction
branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is
represented in two’s complement form. (Equivalent to instruction BRBC 4,k).

Operation:

(i) If Rd ≥ Rr (N ⊕ V = 0) then PC ← PC + k + 1, else PC ← PC + 1

Syntax: Operands: Program Counter:

(i) BRGE k -64 ≤ k ≤ +63 PC ← PC + k + 1

PC ← PC + 1, if condition is false

16-bit Opcode:

1111 01kk kkkk k100

Status Register (SREG) and Boolean Formula:

ITHSVNZC

––––––––

Example:

cp r11,r12 ; Compare registers r11 and r12

brge greateq ; Branch if r11 ≥ r12 (signed)

...

greateq: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)
Cycles: 1 if condition is false

2 if condition is true

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AVR Instruction Set

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