Atmel AVR ATtiny22, AVR ATtiny22L Preliminary Data Sheet
Features
• Utilizes the AVR
• AVR - High-performance and Low-power RISC Architecture
– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
• Data and Nonvolatile Program Memory
– 2K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of internal SRAM
– 128 Bytes of In-System Programmab le EEPR OM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
• Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources
– Power-on Reset Circu it
– Selectable On-chip RC Oscillator
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.4 mA
– Idle Mode: 0.5 mA
– Power Down Mode: <1 µA
• I/O and Packages
– 5 Programmable I/O Lines
– 8-pin PDIP and SOIC
• Operating Voltages
– 2.7 - 6.0V (ATtiny22L)
– 4.0 - 6.0V (ATtiny22)
• Speed Grades
– 0 - 4 MHz (ATtiny22L)
– 0 - 8 MHz (ATtiny22)
®
RISC Architecture
8-bit
Microcontr oller
with 2K Bytes of
In-System
Programmable
Flash
A Ttiny22
A Ttiny22L
Preliminary
Description
The ATtiny22/ L is a low-p ower CMO S 8 -bit micr ocon troll ers b ase d on the AV R RIS C
architecture. By executing powerful instructions in a single clock cycle, the ATtiny22/L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
Pin Configuration
PDIP/SOIC
8
RESET
(CLOCK) PB3
PB4
GND
1
2
3
4
VCC
7
PB2 (SCK/T0)
6
PB1 (MISO/INT0)
5
PB0 (MOSI)
Rev. 1273A–04/99
1
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithm etic Lo gic Unit (A LU), al lowing two ind ependen t regist ers to b e access ed in on e single inst ruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
Block Diagram
Figure 1. The ATtiny22/L Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
OSCILLATOR
GND
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
SPI
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTER
INTERRUPT
UNIT
EEPROM
TIMING AND
CONTROL
RESET
DATA REGISTER
PORTB
PORTB DRIVERS
PB0 - PB4
2
ATtiny22/22L
DATA DIR.
REG. PORTB
ATtiny22/22L
The ATtiny22/L provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM,
128 bytes SRAM, five gen er al purpo se I/O l ine s, 32 g ene ral p ur pos e w or king r e gist ers , an 8- bit ti mer /counter, internal and
external interrupts , progr ammab le Wa tchdog Timer with i nternal osci llator, an S PI se rial p ort fo r Flash Memory downl oading and two softwa re selectable powe r saving modes. T he Idle Mode st ops the CPU while a llowing the SRAM,
timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the register contents
but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip Flash allows the
program memory to be reprogrammed in-system through an SPI serial interface. By combining an 8-bit RISC CPU with ISP
Flash on a monolithic chip, the Atmel ATtiny22/L is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATtiny22/L AVR is supported with a full suite of program and system development tools including: C compilers, macro
assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Pin Descriptions ATtiny22/L
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB4..PB0)
Port B is a 5-bi t bi-dir ectional I /O port . Port pi ns can pr ovide in ternal p ull-up res istors (s elected fo r each bit). Wh en the
device is clocked from an external clock source, PB3 is used as the clock input. The port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
RESET
Reset input. An exter na l res et is g ene ra ted by a l ow le vel o n th e RE SE T pin. Res et pulses lon ger than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
CLOCK
Clock signal input in external clock mode.
Clock Options
External Clock
The ATtiny22/L can be clocked by an ext ernal cl ock sign al, as s hown in Figur e 2, or by the on -chip RC os cill ator. This RC
oscillator runs at a nomi nal frequ ency of 1 MHz (VCC = 5V). A fuse bit - RCEN - in the Fla sh memory selects the on -chip
RC oscillator as the clock source when programmed (“0”). The ATtiny22/L is shipped with this bit programmed.
3
Figure 2. External Clock Drive Configuration
PB3
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one arithmetic logic unit (ALU) operation is executed. Two operands
are output from the registe r file, the operati on is executed, and the result is sto red back in the regi ster file in one cl ock
cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing enabling
efficient address cal cula tions . One of th e thre e addres s poi nters i s also u sed as the a ddress pointer for the c onstan t table
look up function. These added function registers are the 16-bit X-register, Y-register and Z-register.
Figure 3. The ATtiny22/L AVR RISC Architecture
AVR
1K x 16
Program
Flash
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
ATtiny22/L Architecture
Data Bus 8-bit
Status
and Test
32 x 8
General
Purpose
Registers
ALU
Direct Addressing
Indirect Addressing
128 x 8
Data
SRAM
Control
Registers
Interrupt
Unit
SPI
Unit
8-bit
Timer/Counter
Watchdog
Timer
I/O Lines
128 x 8
EEPROM
4
ATtiny22/22L
ATtiny22/22L
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 3 shows the ATtiny22/L AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the regi ster file is ass igned the 32 lowe rmost Data Sp ace addresse s ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and oth er I/O func tions. The I/O memory can be ac cesse d directl y, or as th e Data Spa ce locati ons follo wing those of the register file, $20 - $5F.
The AVR has Harvard architecture - wi th separate memories a nd buses for pro gram and data. The p rogram memory is
accessed with a two stage pipeline. While one instruction is bei ng executed, the next instructio n is pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system
downloadable Flash memory.
With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subrouti ne calls, the return addres s program counter (PC) is sto red on the stack. The stack is
effectively allocated in the general da ta S RAM , a nd c onsequently the sta ck s iz e i s onl y li mi ted by the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The 8-bit stack pointer SP is read/write accessible in the I/O space.
The 128 bytes data SRAM + regist er file and I/O register s can be easily a ccessed thro ugh the five different ad dressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Figure 4. Memory Maps
EEPROM Data Memory
$000
EEPROM
(128 x 8)
$07F
5
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the
program memory. T he different in terrupts ha ve priority in accordan ce with thei r interrupt ve ctor positi on. The lower the
interrupt vector address, the higher the priority.
General Purpose Register File
Figure 5 shows the structure of the 32 general purpose registers in the CPU.
Figure 5. AVR CPU General Purpose Working Registers
7 0 Addr.
R0 $00
R1 $01
R2 $02
…
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
…
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
All the register oper ating instruc tions in th e instruc tion set ha ve direc t and single c ycle acces s to all registers. The only
exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a
register and the LDI instructi on for load immediate con stant data. These instructi ons apply to the second hal f of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or
on a single register apply to the entire register file.
As shown in Fig ure 5, e ach reg ister is al so a ssigned a da ta mem ory add ress , map ping t hem di rectly into the fir st 32 locations of the user Data Space. Although the register file is not physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X, Y and Z registers can be set to index any register
in the file.
6
ATtiny22/22L
ATtiny22/22L
X-Register, Y-Register, and Z-Register
The registers R26..R31 have some added functions to their general purpose usage. These registers are the address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as:
Figure 6. The X, Y, and Z Registers
15 0
X - register 7 0 7 0
R27 ($1B) R26 ($1A)
15 0
Y - register 7 0 7 0
R29 ($1D) R28 ($1C)
15 0
Z - register 7 0 7 0
R31 ($1F) R30 ($1E)
In the different addr essing modes these add ress reg isters have func tions as fix ed di splacem ent, au tomatic inc rement and
decrement (see the descriptions for the different instructions).
ALU - Arithmetic Logic Unit
The high-performa nce AV R ALU oper ates in di rect conn ectio n with all the 32 gener al purpos e working registe rs. Withi n a
single clock cy c le, ALU operations between regis ter s in th e r eg is ter fi le ar e exec uted . The A LU o per ati on s a re di v ided i nto
three main categories - arithmetic, logic and bit-functions
In-System Programmable Flash Program Memory
The ATtiny22/L contains 2K b ytes on- chip In- System Prog rammabl e Flash memor y for p rogram s torage. Sinc e all instruc tions are 16- or 32- bit words, the Flash is organiz ed as 1 K x 16. The Flash m emory has an enduranc e of at l east 1000
write/erase cycles.
The ATtiny22/L Program Counter PC is 10 bits wide, hence addressing the 1024 program memory addresses. See
page 38 for a detailed description on Flash data programming.
Constant tables must be allocated within the address 0-2K (see the LPM - Load Program Memory instruction description).
See page 9 for the different addressing modes.
EEPROM Data Memory
The ATtiny22/L contains 128 bytes of EEPROM data memory. It is organized as a separate data space, in which single
bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access
between the EEPROM and the CPU is described on page 30 specifying the EEPROM address register, the EEPROM data
register, and the EEPROM control register.
For the SPI data downloading, see page 38 for a detailed description.
7
SRAM Data Memory
The following figure shows how the ATtiny22/L Data Memory is organized:
Figure 7. SRAM Organization
Register File Data Address Space
R0 $00
R1 $01
R2 $02
……
R29 $1D
R30 $1E
R31 $1F
I/O Registers
$00 $20
$01 $21
$02 $22
……
$3D $5D
$3E $5E
$3F $5F
Internal SRAM
$60
$61
$62
…
$DD
$DE
$DF
The 224 Data Memory loca tions address the Regi ster file, I/O M emo ry and the data SRA M. The fi rst 96 loc ation s addres s
the Register File + I/O Memory, and the next 128 locations address the data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with
Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing
pointer registers.
The Direct addressing reaches the entire data address space.
The Indirect with Displ acement mo de features 63 addres s locations reach from the base address gi ven by the Y and Z
register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X,
Y and Z are used and decremented and incremented.
The 32 general purpose working registers, 64 I/O registers and the 128 bytes of data SRAM in the ATtiny22/L are all
directly accessible through all these addressing modes.
8
ATtiny22/22L
ATtiny22/22L
Program and Data Addressing Modes
The ATtiny22/L AVR RISC Microcon troller supports powerful and efficient addr essing modes for access to the program
memory (Flash) and dat a memor y. This s ection de scr ibes the d iffere nt addres sing modes su pporte d by th e AVR a rchitecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact
location of the addressing bits.
Register Direct, Single Register Rd
Figure 8. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Direct, Two Registers Rd and Rr
Figure 9. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
9
I/O Direct
Figure 10. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Data Direct
Figure 11. Direct Data Addressing
A 16-bit Data Address is contained in the 16 LSBs of a two-word instr uction. Rd/Rr specify the de stination or source
register.
10
ATtiny22/22L
ATtiny22/22L
Data Indirect with Displacement Figure 12. Data Indirect with Displacement
Operand address is the result o f the Y or Z- register contents ad ded to the addre ss contained in 6 bits of the instruction
word.
Data Indirect
Figure 13. Data Indirect Addressing
Operand address is the contents of the X, Y or the Z-register.
11
Data Indirect With Pre-Decrement
Figure 14. Data Indirect Addressing With Pre-Decrement
The X, Y or the Z-register is decremen ted be fore the oper ation. Operand ad dress is the decrem ented co ntents of the X, Y
or the Z-register.
Data Indirect With Post-Increment
Figure 15. Data Indirect Addressing With Post-Increment
The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z-register
prior to incrementing.
12
ATtiny22/22L
ATtiny22/22L
Constant Addressing Using the LPM Instruction
Figure 16. Code Memory Constant Addressing
Constant byte address i s sp ec ified by th e Z- regi st er c onte nts. The 15 MSBs select wor d add ress (0 - 1K ) , th e LSB s elec ts
low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
Indirect Program Addressing, IJMP and ICALL
Figure 17. Indirect Program Memory Addressing
Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the content of the
Z-register).
13
Relative Program Addressing, RJMP and RCALL
Figure 18. Relative Program Memory Addressing
Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.
Memory Access and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external clock signal applied to the CLOCK pin.
No internal clock division is used.
Figure 19. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 19 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
14
ATtiny22/22L
ATtiny22/22L
Figure 20. Single Cycle ALU Operation
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
Figure 20 shows the internal tim ing con ce pt for the re gis ter fil e. In a si ngle cl oc k cy cle an ALU oper at ion using two r egi ste r
operands is executed, and the result is stored back to the destination register.
Figure 21. On-Chip Data SRAM Access Cycles
T1 T2 T3 T4
System Clock Ø
Address
Data
WR
Data
RD
Prev. Address
Address
The internal data SRAM access is performed in two System Clock cycles as described in Figure 21.
Read Write
15
I/O Memory
The I/O space definition of the ATtiny22/L is shown in the following table:
Table 1. ATtiny22/L I/O Space
Address Hex Name Function
$3F ($5F) SREG Status REGister
$3D ($5D) SPL Stack Pointer Low
$3B ($5B) GIMSK General Interrupt MaSK register
$3A ($5A) GIFR General Interrupt Flag Register
$39 ($59) TIMSK Timer/Counter Interrupt MaSK register
$38 ($58) TIFR Timer/Counter Interrupt Flag register
$35 ($55) MCUCR MCU Control Register
$34 ($54) MCUSR MCU Status Register
$33 ($53) TCCR0 Timer/Counter 0 Control Register
$32 ($52) TCNT0 Timer/Counter 0 (8-bit)
$21 ($41) WDTCR Watchdog Timer Control Register
$1E ($3E) EEAR EEPROM Address Register
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$18 ($38) PORTB Data Register, Port B
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B
Note: Reserved and unused locations are not shown in the table.
All the different ATtiny22/L I/O and peripherals are placed in the I/O space. The different I/O locations are accessed by the
IN and OUT instructio ns transferring data between the 32 ge neral purpose working register s and the I/O space. I/O
registers withi n the add ress ra nge $00 - $1F a re direc tly bit -accessi ble usi ng the S BI and C BI ins tructio ns. In t hese
registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set
chapter for more details. When using the I/O specific commands IN, OUT the I/O addresses $00 - $3F must be used. When
addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this document
are shown with the SRAM address in parentheses.
For compatibility with fu tur e dev ices , r eser v ed bi ts sh oul d be writte n to z er o if accessed. Reserved I/O m emo ry a ddr ess es
should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O reg ister, wr iting a o ne back int o any f lag r ead as set, th us clea ring the flag. The CBI and SBI i nstruc tion s
work with registers $00 to $1F only.
The different I/O and peripherals control registers are explained in the following sections.
Status Register - SREG
The AVR status register - SREG - at I/O space location $3F ($5F) is defined as:
Bit 76543210
$3F ($5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
16
ATtiny22/22L
ATtiny22/22L
• Bit 7 - I: Global Interrupt Enable
The global interrup t ena ble b it mu st b e se t (on e) for the interr upts to be enab led. The i ndivi dual interru pt enable contr ol i s
then performed in sep arate contr ol regis ters. If the glo bal interr upt enabl e register is cleared ( zero), non e of the interr upts
are enabled inde pendent of the indi vidua l interrup t enable setting s. The I-bi t is clear ed by hard ware aft er an inter rupt has
occurred, and is set by the RETI instruction to enable subsequent interrupts.
Bit 6 - T: Bit Copy Storage
•
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A
bit from a register in the regi s ter fil e c an be cop ie d in to T by the B ST in st ructi on, and a bit in T can be copied into a bit in a
register in the register file by the BLD instruction.
Bit 5 - H: Half Carry Flag
•
The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed
information.
Bit 4 - S: Sign Bit, S = N ⊕ V
•
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruc-
tion Set Description for detailed information.
Bit 3 - V: Two’s Complement Overflow Flag
•
The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for
detailed information.
Bit 2 - N: Negative Flag
•
The negative flag N indicates a negative result from an arithmetical or logical operation. See the Instruction Set Description
for detailed information.
Bit 1 - Z: Zero Flag
•
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the Instruction Set Description for
detailed information.
Bit 0 - C: Carry Flag
•
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruction S et Description for detailed
information.
Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from
an interrupt routine. This must be handled by software.
Stack Pointer - SPL
An 8-bit register at I/O address $3 D ($5D) forms th e stack poin ter of the ATtin y22/L. 8 bits are us ed to address the
128 bytes of SRAM in locations $60 - $DF.
Bit 76543210
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
The Stack Pointer points to the data SRA M stack area where the Su broutin e and Interru pt Stacks are lo cated. Thi s Stack
space in the data SRAM must be de fined by the program bef ore any subroutine calls are executed or interr upts are
enabled. The stack pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed
onto the Stack with the PUSH instruction, and it is decremented by two when an address is pushed onto the Stack with
subroutine calls and interrupts. The Stack Pointer is incremented by one when data is popped from the Stack with the POP
instruction, and it is incremented b y two when an address is popped from the Stack with return fro m subroutine RET or
return from interrupt RETI.
17
Reset and Interrupt Handling
The ATtiny22/L provides two interrupt sources. These interrupts and the separate reset vector, each have a separate
program vector in the progr am me mor y s pac e. Bo th int er rupts ar e assi gn ed individual enable bit s whic h mus t be se t ( one )
together with the I-bit in the status register in order to enable the interrupt.
The lowest addresses in the program memor y space are automatical ly defined as the Reset and Interrupt vector s. The
complete list of ve ctors is shown i n Table 2 . The li st also determines th e prior ity levels of the in terrupts . The lower the
address the higher is the priority level. RESET has the highest priority, next is INT0 - the External Interrupt Request 0, etc.
Table 2. Reset and Inte rru pt Vectors
Vector No. Program Address Source Interrupt Definition
1 $000 RESET Hardware Pin, Power-on Reset and Watchdog Reset
2 $001 INT0 External Interrupt Request 0
3 $002 TIMER0, OVF0 Timer/Counter0 Overflow
The most typical program setup for the Reset and Interrupt Vector Addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp TIM_OVF0 ; Timer0 Overflow Handler;
$003 MAIN: ldi r16, low(RAMEND) ; Main program start
out SPL, r16
<instr> xxx
… … … …
Reset Sources
The ATtiny22/L provides three sources of reset:
• Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V
• External Reset. The MCU is reset when a low level is present on the RESET
pin for more than 50 ns.
POT
).
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
During reset, all I/O registers are set to their initial values, and the program starts execution from address $000. The
instruction placed in addre ss $000 must be an RJMP - relative j ump - instructio n to the reset handli ng routine. If the
program never enables an inte r rupt s ou rce, the interrupt vecto rs a re no t us ed , an d reg ular program code can be p la ced at
these locations. The circuit diagram in Figure 22 shows the reset logic. Table 3 defines the timing and electrical parameters
of the reset circuitry.
18
ATtiny22/22L
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