Atmel AVR ATmega103, AVR ATmega103L User Manual
Features
• Utilizes the AVR
• AVR – High-performance and Low-power RISC Architecture
– 121 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers + Peripheral Control Registers
– Up to 6 MIPS Throughput at 6 MHz
• Data and Nonvolatile Program Memory
– 128K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 4K Bytes Internal SRAM
– 4K Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
– SPI Interface for In-System Programming
• Peripheral Features
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
– Real-time Counter (RTC) with Separate Oscillator
– Two 8-bit Timer/Counters with Separate Prescaler and PWM
– Expanded 16-bit Timer/Counter System with Separate Prescaler, Compare,
Capture Modes and Dual 8-, 9-, or 10-bit PWM
– Programmable Watchdog Timer with On-chip Oscillator
– 8-channel, 10-bit ADC
• Special Microcontroller Features
– Low-power Idle, Power-save and Power-down Modes
– Software Selectable Clock Frequency
– External and Internal Interrupt Sources
• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 5.5 mA
– Idle Mode: 1.6 mA
– Power-down Mode: < 1 µA
• I/O and Packages
– 32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
– 64-lead TQFP
• Operating Voltages
– 2.7 - 3.6V for ATmega103L
– 4.0 - 5.5V for ATmega103
• Speed Grades
– 0 - 4 MHz for ATmega103L
– 0 - 6 MHz for ATmega103
®
RISC Architecture
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega103(L)
Rev. 0945G–09/01
1
Pin Configuration TQFP
PC6 (A14)
PC5 (A13)
PC7 (A15)
PA7 (AD7)
ALE
PA6 (AD6)
PA5 (AD5)
PA4 (AD4)
(AD2) PA2
(AD1) PA1
(AD0) PA0
VCC
GND
(ADC7) PF7
(ADC6) PF6
(ADC5) PF5
(ADC4) PF4
(ADC3) PF3
(ADC2) PF2
(ADC1) PF1
(ADC0) PF0
AREF
AGND
AVCC
PA3 (AD3)
52
53
54
55
56
57
58
59
60
612361
622262
63
63
6464
INDEX CORNER
1512503494485476467458449
PEN
(PDI/RXD) PE0
(PDO/TXD) PE1
431042114112401339143815371636173518341933
(AC-) PE3
(AC+) PE2
(INT4) PE4
(INT5) PE5
(INT6) PE6
(INT7) PE7
PC4 (A12)
(SS) PB0
PC3 (A11)
(SCK) PB1
PC2 (A10)
(MOSI) PB2
PC1 (A9)
(MISO) PB3
PC0 (A8)
(OC0/PWM0) PB4
(OC1A/PWM1A) PB5
RD
WR
32
31
30
29
28
27
26
25
24
21
20
(OC1B/PWM1B) PB6
PD7 (T2)
PD6 (T1)
PD5
PD4 (IC1)
PD3 (INT3)
PD2 (INT2)
PD1 (INT1)
PD0 (INT0)
XTAL1
XTAL2
GND
VCC
RESET
TOSC1
TOSC2
PB7 (OC2/PWM2)
2
ATmega103(L)
0945G–09/01
ATmega103(L)
Description The ATmega103(L) is a low-power, CMOS, 8-bit microcontroller based on the AVR
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega103(L) achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
The ATmega103(L) provides the following features: 128K bytes of In-System Programmable Flash, 4K bytes EEPROM, 4K bytes SRAM, 32 general-purpose I/O lines, 8 input
lines, 8 output lines, 32 general-purpose working registers, real-time counter (RTC), 4
flexible timer/counters with compare modes and PWM, UART, programmable watchdog
timer with internal oscillator, an SPI serial port and 3 software-selectable power saving
modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the timer oscillator continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
The On-chip ISP Flash allows the program memory to be reprogrammed in-system
through a serial interface or by a conventional nonvolatile memory programmer. By
combining an 8-bit RISC CPU with a large array of ISP Flash on a monolithic chip, the
Atmel ATmega103(L) is a powerful microcontroller that provides a highly flexible and
cost-effective solution to many embedded control applications.
The ATmega103(L) AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators and evaluation kits.
0945G–09/01
3
Block Diagram Figure 1. The ATmega103(L) Block Diagram
PA0 - PA7PF0 - PF7
VCC
GND
AVCC
AGND
AREF
PORTF BUFFERS
ANALOG MUX ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PORTA DRIVER/BUFFERS
DATAREGISTER
PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
DATADIR.
REG. PORTA
INTERNAL
OSCILLATOR
WATCHDOG
MCU CONTROL
REGISTER
COUNTERS
INTERRUPT
8-BIT DATA BUS
TIMER
TIMER/
UNIT
PC0 - PC7
PORTC DRIVERS
DATAREGISTER
PORTC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
XTAL1
XTAL1
TOSC2
TOSC1
RESET
ALE
WR
RD
ANALOG
COMPARATOR
DATAREGISTER
+
-
PORTE
CONTROL
LINES
DATADIR.
REG. PORTE
ALU
STATUS
REGISTER
SPI
DATAREGISTER
PORTB
PORTB DRIVER/BUFFERSPORTE DRIVER/BUFFERS
EEPROM
PROGRAMMING
LOGIC
UART
DATADIR.
REG. PORTB
PB0 - PB7PE0 - PE7
DATAREGISTER
PORTD
PORTD DRIVER/BUFFERS
PD0 - PD7
DATADIR.
REG. PORTD
PEN
VCC
GND
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ATmega103(L)
0945G–09/01
ATmega103(L)
Pin Descriptions
VCC Supply voltage.
GND Ground.
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors
(selected for each bit). The Port A output buffers can sink 20 mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low,
they will source current if the internal pull-up resistors are activated.
Port A serves as Multiplexed Address/Data bus when using external SRAM.
The Port A pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port B output
buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
The Port B pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port C (PC7..PC0) Port C is an 8-bit output port. The Port C output buffers can sink 20 mA.
Port C also serves as Address output when using external SRAM.
Since Port C is an output only port, the Port C pins are not tri-stated when a reset condition becomes active.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output
buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features.
The Port D pins are tri-stated when a reset condition becomes active, even if the clock is
not running.
Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port E output
buffers can sink 20 mA. As inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port E also serves the functions of various special features.
The Port E pins are tri-stated when a reset condition becomes active, even if the clock is
not running
Port F (PF7..PF0) Port F is an 8-bit input port. Port F also serves as the analog inputs for the ADC.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
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5
TOSC1 Input to the inverting Timer/Counter oscillator amplifier.
TOSC2 Output from the inverting Timer/Counter oscillator amplifier.
WR
RD
External SRAM write strobe
External SRAM read strobe
ALE ALE is the Address Latch Enable used when the External Memory is enabled. The ALE
strobe is used to latch the low-order address (8 bits) into an address latch during the first
access cycle, and the AD0-7 pins are used for data during the second access cycle.
AVCC Supply voltage for Port F, including ADC. The pin must be connected to VCC when not
used for the ADC. See “ADC Noise Canceling Techniques” on page 77 for details when
using the ADC.
AREF AREF is the analog reference input for the ADC converter. For ADC operations, a volt-
age in the range AGND to AVCC must be applied to this pin.
AGND If the board has a separate analog ground plane, this pin should be connected to this
ground plane. Otherwise, connect to GND.
PEN
PEN is a programming enable pin for the serial programming mode. By holding this pin
low during a power-on reset, the device will enter the serial programming mode. PEN
has no function during normal operation.
Clock Options
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which
can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used.
Figure 2. Oscillator Connections
MAX 1 HC BUFFER
HC
C2
C1
Note: When using the MCU oscillator as a clock for an external device, an HC buffer should be
connected as indicated in the figure.
XTAL2
XTAL1
GND
6
ATmega103(L)
0945G–09/01
ATmega103(L)
External Clock To drive the device from an external clock source, XTAL2 should be left unconnected
while XTAL1 is driven as shown in Figure 3.
Figure 3. External Clock Drive Configuration
NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
GND
Timer Oscillator For the Timer Oscillator pins, TOSC1 and TOSC2, the crystal is connected directly
between the pins. No external capacitors are needed. The oscillator is optimized for use
with a 32,768 Hz watch crystal. Applying an external clock source to TOSC1 is not
recommended.
0945G–09/01
7
Architectural Overview
Figure 4. The ATmega103(L) AVR RISC Architecture
AVR ATmega103(L) Architecture
Data Bus 8-bit
64K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
and Test
Purpose
Registers
Direct Addressing
Indirect Addressing
Status
32 x 8
General
Peripherals
ALU
4K x 8
Data
SRAM
4K x 8
EEPROM
The AVR uses a Harvard architecture concept – with separate memories and buses for
program and data. The program memory is accessed with a single-level pipeline. While
one instruction is being executed, the next instruction is pre-fetched from the program
memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Programmable Flash memory. With a few exceptions, AVR
instructions have a single 16-bit word format, meaning that every program memory
address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM and,
consequently, the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 16-bit stack pointer (SP) is read/write accessible in the
I/O space.
The 4000 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture.
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
8
ATmega103(L)
0945G–09/01
ATmega103(L)
rate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt
vector position. The lower the interrupt vector address, the higher the priority.
The memory spaces in the AVR architecture are all linear and regular memory maps.
General-purpose Register File
Figure 5 shows the structure of the 32 general-purpose working registers in the CPU.
Figure 5. AVR CPU General-purpose Working Registers
7 0 Addr.
R0 $00
R1 $01
R2 $02
.=.=.
R13 $0D
General R14 $0E
Purpose R15 $0F
Working R16 $10
Registers R17 $11
. . .
R26 $1A X-register low byte
R27 $1B X-register high byte
R28 $1C Y-register low byte
R29 $1D Y-register high byte
R30 $1E Z-register low byte
R31 $1F Z-register high byte
All the register operating instructions in the instruction set have direct and single-cycle
access to all registers. The only exception are the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the
LDI instruction for load immediate constant data. These instructions apply to the second
half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND and
OR and all other operations between two registers or on a single register apply to the
entire register file.
0945G–09/01
As shown in Figure 5, each register is also assigned a data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great
flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any
register in the file.
The 4K bytes of SRAM available for general data are implemented as addresses $0060
to $0FFF.
9
X-register, Y-register and Zregister
The registers R26..R31 have some added functions to their general-purpose usage.
These registers are address pointers for indirect addressing of the SRAM. The three
indirect address registers X, Y, and Z are defined as:
Figure 6. X-, Y-, and Z-registers
15 0
X-register 7 0 7 0
R27 ($1B) R26 ($1A)
15 0
Y-register 7 0 7 0
R29 ($1D) R28 ($1C)
15 0
Z-register 7 0 7 0
R31 ($1F) R30 ($1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different
instructions).
ALU – Arithmetic Logic Unit
ISP Flash Program Memory
The high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main
categories: arithmetic, logical and bit functions.
The ATmega103(L) contains 128K bytes of On-chip In-System Programmable Flash
memory for program storage. Since all instructions are single or double 16-bit words, the
Flash is organized as 64K x 16. The Flash memory has an endurance of at least 1000
write/erase cycles.
Constant tables can be allocated in the entire program memory space (see the LPM –
Load Program Memory and ELPM – Extended Load Program Memory instruction
descriptions).
SRAM Data Memory The ATmega103(L) supports two different configurations for the SRAM data memory as
listed in Table 1.
Table 1. Memory Configurations
Configuration Internal SRAM Data Memory External SRAM Data Memory
A 4000 None
B 4000 up to 64K
Note: When using 64K of external SRAM, 60K will be available.
10
ATmega103(L)
0945G–09/01
Figure 7. Memory Configurations
Memory Configuration A
Program Flash
(32K/64K x 16)
$0000
ATmega103(L)
Data MemoryProgram Memory
32 Registers
64 I/O Registers
Internal SRAM
(4000 x 8)
$0000 - $001F
$0020 - $005F
$0060
$0FFF
Memory Configuration B
Program Memory
Program Flash
(32K/64K x 16)
$7FFF/$FFFF
$0000
Data Memory
32 Registers
64 I/O Registers
Internal SRAM
(4000 x 8)
External SRAM
(0 - 64K x 8)
$0000 - $001F
$0020 - $005F
$0060
$0FFF
$1000
0945G–09/01
$7FFF/
$FFFF
$FFFF
11
The 4096 first data memory locations address both the register file, the I/O memory and
the internal data SRAM. The first 96 locations address the register file and I/O memory,
and the next 4000 locations address the internal data SRAM.
An optional external data SRAM can be used with the ATmega103(L). This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. If a 64K external SRAM is used, 4K of
the external memory is lost as the addresses are occupied by internal memory.
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (RD
External SRAM operation is enabled by setting the SRE bit in the MCUCR register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH and
POP take one additional clock cycle. If the stack is placed in external SRAM, interrupts,
subroutine calls and returns take two clock cycles extra because the 2-byte program
counter is pushed and popped. When external SRAM interface is used with wait state,
two additional clock cycles are used per byte. This has the following effect: Data transfer
instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns
will need four clock cycles more than specified in the “Instruction Set Summary” on page
130.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement and Indirect with Post-increment. In the
register file, registers R26 to R31 feature the indirect addressing pointer registers.
and WR) are inactive during the whole access cycle.
Program and Data Addressing Modes
The Indirect with Displacement mode features 63 address locations reached from the
base address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented and incremented.
The entire data address space including the 32 general-purpose working registers and
the 64 I/O registers are all accessible through all these addressing modes. See the next
section for a detailed description of the different addressing modes.
The ATmega103(L) AVR RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM, register
file and I/O memory). This section describes the different addressing modes supported
by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.
12
ATmega103(L)
0945G–09/01
ATmega103(L)
Register Direct, Single Register Rd
Register Direct, Two Registers Rd and Rr
Figure 8. Direct Single Register Addressing
15
OP d
04
The operand is contained in register d (Rd).
Figure 9. Direct Register Addressing, Two Registers
15
OP dr
0459
REGISTER FILE
0
d
31
REGISTER FILE
0
Operands are contained in registers r (Rr) and d (Rd). The result is stored in register d
(Rd).
I/O Direct Figure 10. I/O Direct Addressing
15
OP P
n
d
r
31
I/O MEMORY
0
05
63
0945G–09/01
Operand address is contained in six bits of the instruction word. n is the destination or
source register address.
13
Data Direct Figure 11. Direct Data Addressing
31
OP Rr/Rd
15 0
20 19
16 LSBs
A 16-bit data address is contained in the 16 LSBs of a 2-word instruction. Rd/Rr specify
the destination or source register.
16
Data Space
$0000
$FFFF
Data Indirect with
Figure 12. Data Indirect with Displacement
Displacement
15
Y- OR Z-REGISTER
15
OP an
Operand address is the result of the Y- or Z-register contents added to the address contained in six bits of the instruction word.
Data Indirect Figure 13. Data Indirect Addressing
X-, Y- OR Z-REGISTER
Data Space
$0000
0
05610
$FFFF
Data Space
$0000
015
14
$FFFF
Operand address is the contents of the X-, Y,- or the Z-register.
ATmega103(L)
0945G–09/01
ATmega103(L)
Data Indirect with Predecrement
Data Indirect with Postincrement
Figure 14. Data Indirect Addressing with Pre-decrement
Data Space
$0000
015
X-, Y- OR Z-REGISTER
-1
$FFFF
The X-, Y-, or the Z-register is decremented before the operation. Operand address is
the decremented contents of the X-, Y-, or the Z-register.
Figure 15. Data Indirect Addressing with Post-increment
Data Space
$0000
015
X-, Y- OR Z-REGISTER
Constant Addressing Using the LPM and ELPM Instructions
1
$FFFF
The X-, Y-, or the Z-register is incremented after the operation. Operand address is the
contents of the X-, Y-, or the Z-register prior to incrementing.
Figure 16. Code Memory Constant Addressing
PROGRAM MEMORY
$0000
0115
Z-REGISTER
$7FFF/$FFFF
Constant byte address is specified by the Z-register contents. The 15 MSBs select word
address (0 - 32K), LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
0945G–09/01
15
If ELPM is used, LSB of the RAM Page Z register (RAMPZ) is used to select low or high
memory page (RAMPZ0 = 0: Low Page, RAMPZ0 = 1: High Page).
Direct Program Address, JMP and CALL
Indirect Program Addressing, IJMP and ICALL
Figure 17. Direct Program Memory Addressing
31
OP
15 0
21 20
16 LSBs
16
PROGRAM MEMORY
$0000
$7FFF/$FFFF
Program execution continues at the address immediate in the instruction words.
Figure 18. Indirect Program Memory Addressing
PROGRAM MEMORY
015
Z-REGISTER
$0000
Relative Program Addressing, RJMP and RCALL
16
ATmega103(L)
$7FFF/$FFFF
Program execution continues at address contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register).
Figure 19. Relative Program Memory Addressing
15
15
1112
OP k
PROGRAM MEMORY
0
PC
1
0
$0000
$7FFF/$FFFF
0945G–09/01
ATmega103(L)
Program execution continues at address PC + k + 1. The relative address k is -2048 to
2047.
EEPROM Data Memory The EEPROM memory is organized as a separate data space in which single bytes can
be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles. The access between the EEPROM and the CPU is described on page 54 specifying the EEPROM address register, the EEPROM data register and the EEPROM
control register.
Memory Access Times and Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and
internal memory access.
The AVR CPU is driven by the System Clock Ø, directly generated from the external
clock crystal for the chip. No internal clock division is used.
Figure 20 shows the parallel instruction fetches and instruction executions enabled by
the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for
functions per cost, functions per clocks and functions per power unit.
Figure 20. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
System Clock Ø
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
0945G–09/01
Figure 21 shows the internal timing concept for the register file. In a single clock cycle,
an ALU operation using two register operands is executed and the result is stored back
to the destination register.
Figure 21. Single Cycle ALU Operation
T1 T2 T3 T4
System Clock Ø
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
17
The internal data SRAM access is performed in two System Clock cycles as described
in Figure 22.
Figure 22. On-chip Data SRAM Access Cycles
T1 T2 T3 T4
System Clock Ø
Address
Prev. Address
Address
Data
WR
Data
RD
See “Interface to External SRAM” on page 79. for a description of the access to the
external SRAM.
I/O Memory The I/O space definition of the ATmega103(L) is shown in Table 2.
Table 2. ATmega103(L) I/O Space
I/O Address (SRAM
Address) Name Function
$3F ($5F) SREG Status REGister
$3E ($5E) SPH Stack Pointer High
$3D ($5D) SPL Stack Pointer Low
$3C ($5C) XDIV XTAL Divide Control Register
$3B ($5B) RAMPZ RAM Page Z Select Register
Write
Read
18
$3A ($5A) EICR External Interrupt Control Register
$39 ($59) EIMSK External Interrupt MaSK register
$38 ($58) EIFR External Interrupt Flag Register
$37 ($57) TIMSK Timer/Counter Interrupt MaSK register
$36 ($56) TIFR Timer/Counter Interrupt Flag register
$35 ($55) MCUCR MCU General Control Register
$34 ($54) MCUSR MCU Status Register
$33 ($53) TCCR0 Timer/Counter0 Control Register
$32 ($52) TCNT0 Timer/Counter0 (8-bit)
$31 ($51) OCR0 Timer/Counter0 Output Compare Register
$30 ($50) ASSR Asynchronous Mode Status Register
$2F ($4F) TCCR1A Timer/Counter1 Control Register A
$2E ($4E) TCCR1B Timer/Counter1 Control Register B
ATmega103(L)
0945G–09/01
Table 2. ATmega103(L) I/O Space (Continued)
I/O Address (SRAM
Address) Name Function
$2D ($4D) TCNT1H Timer/Counter1 High Byte
$2C ($4C) TCNT1L Timer/Counter1 Low Byte
$2B ($4B) OCR1AH Timer/Counter1 Output Compare Register A High Byte
$2A ($4A) OCR1AL Timer/Counter1 Output Compare Register A Low Byte
$29 ($49) OCR1BH Timer/Counter1 Output Compare Register B High Byte
$28 ($48) OCR1BL Timer/Counter1 Output Compare Register B Low Byte
$27 ($47) ICR1H Timer/Counter1 Input Capture Register High Byte
$26 ($46) ICR1L Timer/Counter1 Input Capture Register Low Byte
$25 ($45) TCCR2 Timer/Counter2 Control Register
$24 ($44) TCNT2 Timer/Counter2 (8-bit)
$23 ($43) OCR2 Timer/Counter2 Output Compare Register
$21 ($41) WDTCR Watchdog Timer Control Register
$1F ($3F) EEARH EEPROM Address Register High
ATmega103(L)
$1E ($3E) EEARL EERPOM Address Register Low
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR EEPROM Control Register
$1B ($3B) PORTA Data Register, Port A
$1A ($3A) DDRA Data Direction Register, Port A
$19 ($39) PINA Input Pins, Port A
$18 ($38) PORTB Data Register, Port B
$17 ($37) DDRB Data Direction Register, Port B
$16 ($36) PINB Input Pins, Port B
$15 ($35) PORTC Data Register, Port C
$12 ($32) PORTD Data Register, Port D
$11 ($31) DDRD Data Direction Register, Port D
$10 ($30) PIND Input Pins, Port D
$0F ($2F) SPDR SPI I/O Data Register
$0E ($2E) SPSR SPI Status Register
$0D ($2D) SPCR SPI Control Register
$0C ($2C) UDR UART I/O Data Register
$0B ($2B) USR UART Status Register
0945G–09/01
$0A ($2A) UCR UART Control Register
$09 ($29) UBRR UART Baud Rate Register
$08 ($28) ACSR Analog Comparator Control and Status Register
$07 ($27) ADMUX ADC Multiplexer Select Register
19
Table 2. ATmega103(L) I/O Space (Continued)
I/O Address (SRAM
Address) Name Function
$06 ($26) ADCSR ADC Control and Status Register
$05 ($25) ADCH ADC Data Register High
$04 ($24) ADCL ADC Data Register Low
$03 ($23) PORTE Data Register, Port E
$02 ($22) DDRE Data Direction Register, Port E
$01 ($21) PINE Input Pins, Port E
$00 ($20) PINF Input Pins, Port F
Note: Reserved and unused locations are not shown in the table.
All the different ATmega103(L) I/Os and peripherals are placed in the I/O space. The different I/O locations are directly accessed by the IN and OUT instructions transferring
data between the 32 general-purpose working registers and the I/O space. I/O registers
within the address range $00 - $1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the “Instruction Set Summary” on page 130 for
more details. When using the I/O specific instructions IN and OUT, the I/O register
address $00 - $3F are used. When addressing I/O registers as SRAM, $20 must be
added to this address. All I/O register addresses throughout this document are shown
with the SRAM address in parentheses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a one back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The different I/O and peripherals control registers are explained in the following
sections.
Status Register – SREG The AVR status register (SREG) at I/O space location $3F ($5F) is defined as:
Bit 76543210
$3F ($5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7 – I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The
individual interrupt enable control is then performed in separate control registers. If the
global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after
an interrupt has occurred and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
20
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
ATmega103(L)
0945G–09/01
ATmega103(L)
into T by the BST instruction and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
instruction set description on page 130 for detailed information.
• Bit 4 – S: Sign Bit, S = N
The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the instruction set description on page 130 for detailed
information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics. See the
instruction set description on page 130 for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction set description on page 130 for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the
instruction set description on page 130 for detailed information.
• Bit 0 – C: Carry Flag
⊕ V
The carry flag C indicates a carry in an arithmetical or logical operation. See the instruction set description on page 130 for detailed information.
Note that the status register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by
software.
Stack Pointer – SP The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the
I/O space locations $3E ($5E) and $3D ($5D). As the ATmega103(L) supports up to
64K bytes memory, all 16 bits are used.
Bit 151413121110 9 8
$3E ($5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
$3D ($5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
00000000
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by one when
data is pushed onto the stack with the PUSH instruction and it is decremented by 2
when an address is pushed onto the stack with subroutine calls and interrupts. The
Stack Pointer is incremented by 1 when data is popped from the stack with the POP
instruction and it is incremented by 2 when an address is popped from the stack with
return from subroutine RET or return from interrupt RETI.
0945G–09/01
21
RAM Page Z Select Register – RAMPZ
Bit 7654321 0
$3B ($5B) –––––––RAMPZ0RAMPZ
Read/WriteRRRRRRRR/W
Initial Value0000000 0
The RAMPZ register is normally used to select which 64K RAM page is accessed by the
Z pointer. As the ATmega103(L) does not support more than 64K of SRAM memory,
this register is used only to select which page in the program memory is accessed when
the ELPM instruction is used. The different settings of the RAMPZ0 bit have the following effects:
RAMPZ0 = 0: Program memory address $0000 - $7FFF (lower 64K bytes) is
accessed by ELPM
RAMPZ0 = 1: Program memory address $8000 - $FFFF (higher 64K bytes) is
accessed by ELPM
Note that LPM is not affected by the RAMPZ setting.
MCU Control Register – MCUCR
The MCU Control Register contains control bits for general MCU functions.
Bit 7654321 0
$35 ($55) SRE SRW SE SM1 SM0 – – – MCUCR
Read/Write R/W R/W R/W R/W R/W R R R
Initial Value0000000 0
• Bit 7 – SRE: External SRAM Enable
When the SRE bit is set (one), the external data SRAM is enabled, and the pin functions
AD0 - 7 (Port A), and A8 - 15 (Port C) are activated as the alternate pin functions. Then
the SRE bit overrides any pin direction settings in the respective data direction registers.
When the SRE bit is cleared (zero), the external data SRAM is disabled and the normal
pin and data direction settings are used.
• Bit 6 – SRW: External SRAM Wait State
When the SRW bit is set (one), a one-cycle wait state is inserted in the external data
SRAM access cycle. When the SRW bit is cleared (zero), the external data SRAM
access is executed with a three-cycle scheme. See Figure 51 on page 80 and Figure 52
on page 80.
• Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP
instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit just before the
execution of the SLEEP instruction.
• Bits 4, 3 – SM1/SM0: Sleep Mode Select Bits 1 and 0
22
This bit selects between the three available sleep modes as shown in Table 3.
Table 3. Sleep Mode Select
SM1 SM0 Sleep Mode
0 0 Idle Mode
01 Reserved
1 0 Power-down
1 1 Power-save
ATmega103(L)
0945G–09/01
ATmega103(L)
• Bits 2..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
XTAL Divide Control Register – XDIV
The XTAL Divide Control Register is used to divide the XTAL clock frequency by a number in the range 1 - 129. This feature can be used to decrease power consumption when
the requirement for processing power is low.
Bit 7 654321 0
$3C ($5C) XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 XDIV
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0 000000 0
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is set (one), the clock frequency of the CPU and all peripherals is
divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be set and
cleared run-time to vary the clock frequency as suitable to the application.
• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the
value of these bits is denoted d, the following formula defines the resulting CPU clock
frequency f
clk
:
f
CLK
XTAL
-------------------=
129
d–
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is
set to one, the value written simultaneously into XDIV6..XDIV0 is taken as the division
factor. When XDIVEN is cleared to zero, the value written simultaneously into
XDIV6..XDIV0 is rejected. As the divider divides the master clock input to the MCU, the
speed of all peripherals is reduced when a division factor is used.
Reset and Interrupt Handling
The ATmega103(L) provides 23 different interrupt sources. These interrupts and the
separate reset vector each have a separate program vector in the program memory
space. All interrupts are assigned individual enable bits that must be set (one) together
with the I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 4. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority and next is INT0 (the External
Interrupt Request 0), etc.
Table 4. Reset and Interrupt Vectors
Program
Vecto r No .
1 $0000 RESET
2 $0002 INT0 External Interrupt Request 0
3 $0004 INT1 External Interrupt Request 1
4 $0006 INT2 External Interrupt Request 2
5 $0008 INT3 External Interrupt Request 3
6 $000A INT4 External Interrupt Request 4
Address Source Interrupt Definition
Hardware Pin, Power-on Reset and Watchdog
Reset
0945G–09/01
23
Table 4. Reset and Interrupt Vectors (Continued)
Program
Vecto r No .
7 $000C INT5 External Interrupt Request 5
8 $000E INT6 External Interrupt Request 6
9 $0010 INT7 External Interrupt Request 7
10 $0012 TIMER2 COMP Timer/Counter2 Compare Match
11 $0014 TIMER2 OVF Timer/Counter2 Overflow
12 $0016 TIMER1 CAPT Timer/Counter1 Capture Event
13 $0018 TIMER1 COMPA Timer/Counter1 Compare Match A
14 $001A TIMER1 COMPB Timer/Counter1 Compare Match B
15 $001C TIMER1 OVF Timer/Counter1 Overflow
16 $001E TIMER0 COMP Timer/Counter0 Compare Match
17 $0020 TIMER0 OVF Timer/Counter0 Overflow
18 $0022 SPI, STC SPI Serial Transfer Complete
19 $0024 UART, RX UART, Rx Complete
20 $0026 UART, UDRE UART Data Register Empty
21 $0028 UART, TX UART, Tx Complete
22 $002A ADC ADC Conversion Complete
Address Source Interrupt Definition
23 $002C EE READY EEPROM Ready
24 $002E ANALOG COMP Analog Comparator
The most typical program setup for the Reset and Interrupt vector addresses are:
Address Labels Code Comments
$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
$0012 jmp TIM2_COMP ; Timer2 Compare Handler
$0014 jmp TIM2_OVF ; Timer2 Overflow Handler
$0016 jmp TIM1_CAPT ; Timer1 Capture Handler
$0018 jmp TIM1_COMPA ; Timer1 CompareA Handler
$001A jmp TIM1_COMPB ; Timer1 CompareB Handler
$001C jmp TIM1_OVF ; Timer1 Overflow Handler
$001E jmp TIM0_COMP ; Timer0 Compare Handler
$0020 jmp TIM0_OVF ; Timer0 Overflow Handler
$0022 jmp SPI_STC ; SPI Transfer Complete Handler
$0024 jmp UART_RXC ; UART RX Complete Handler
$0026 jmp UART_DRE ; UDR Empty Handler
24
ATmega103(L)
0945G–09/01
$0028 jmp UART_TXC ; UART TX Complete Handler
$002A jmp ADC ; ADC Conversion Complete Handler
$002C jmp EE_RDY ; EEPROM Ready Handler
$002E jmp ANA_COMP ; Analog Comparator Handler
;
$0030 MAIN: ldi r16, high(RAMEND); Main program start
$0031 out SPH,r16
$0032 ldi r16, low(RAMEND)
$0033 out SPL,r16
$0034 <instr> xxx
... ... ... ...
Reset Sources The ATmega103(L) has three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on
Reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET pin for
more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and
the Watchdog is enabled.
ATmega103(L)
During reset, all I/O registers except the MCU Status Register are then set to their initial
values and the program starts execution from address $0000. The instruction placed in
address $0000 must be a JMP (absolute jump) instruction to the reset handling routine.
If the program never enables an interrupt source, the interrupt vectors are not used and
regular program code can be placed at these locations. The circuit diagram in Figure 23
shows the reset logic. Table 5 defines the timing and electrical parameters of the reset
circuitry.
Figure 23. Reset Logic
VCC
RESET
PEN D Q
E
XTAL1
10-50K
100-500K
Power-on Reset
Circuit
Reset Circuit
Watchdog
Timer
On-chip
RC Oscillator
POR
14-stage Ripple Counter
Delay Unit
COUNTER RESET
Q8 Q11 Q13
SUT0
SUT1
QS
Q
R
INTERNAL
RESET
0945G–09/01
25
Table 5. Reset Characteristics (V
Symbol Parameter Condition Min Typ Max Units
Power-on Reset Threshold
(rising)
(1)
V
POT
Power-on Reset Threshold
(falling)
= 5.0V)
CC
1.0 1.4 1.8 V
0.4 0.6 0.8 V
V
RST
T
TOUT
Note: 1. The Power-on Reset will not work unless the supply voltage has been below V
RESET Pin Threshold Voltage VCC/2 V
SUT = 00 5 CPU cycles
Reset Delay Time-out Period
(falling).
SUT = 01
SUT = 10
SUT = 11
0.4
3.2
12.8
0.5
4.0
16.0
0.6
4.8
19.2
ms
POT
Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. As
shown in Figure 23, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after V
on Threshold voltage (V
), regardless of the VCC rise time (see Figure 24). The Fuse
POT
has reached the Power-
CC
bits SUT1 and SUT0 are used to select start-up time as indicated in Table 5. A “0” in the
table indicates that the fuse is programmed.
The user can select the start-up time according to typical oscillator start-up time. The
number of WDT oscillator cycles used for each time-out except for SUT = 00 is shown in
Table 6. The frequency of the Watchdog oscillator is voltage-dependent as shown in
“Typical Characteristics” on page 118.
Table 6. Number of Watchdog Oscillator Cycles
SUT 1/0 Time-out at VCC = 5V Number of WDT Cycles
01 0.5 ms 512
26
10 4.0 ms 4K
11 16.0 ms 16K
The setting SUT 1/0 = 00 starts the MCU after 5 CPU clock cycles, and can be used
when an external clock signal is applied to the XTAL1 pin. This setting does not use the
WDT oscillator and enables very fast start-up from the sleep modes Power-down or
Power-save if the clock signal is present during sleep. For details, refer to the programming specification starting on page 99.
If the built-in start-up delay is sufficient, RESET
an external pull-up resistor. By holding the pin low for a period after V
applied, the Power-on Reset period can be extended. Refer to Figure 25 for a timing
example of this.
ATmega103(L)
can be connected to VCC directly or via
has been
CC
0945G–09/01
Figure 24. MCU Start-up, RESET Tied to VCC.
V
VCC
RESET
TIME-OUT
INTERNAL
RESET
POT
V
RST
t
TOUT
ATmega103(L)
Figure 25. MCU Start-up, RESET
V
VCC
RESET
TIME-OUT
INTERNAL
RESET
POT
Controlled Externally
V
RST
t
TOUT
External Reset An external reset is generated by a low level on the RESET
than 50 ns will generate a reset even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset. When the applied signal reaches the Reset Threshold
Voltage (V
period t
) on its positive edge, the delay timer starts the MCU after the Time-out
RST
has expired.
TOUT
Figure 26. External Reset during Operation
VCC
pin. Reset pulses longer
0945G–09/01
RESET
TIME-OUT
INTERNAL
RESET
V
RST
t
TOUT
27
Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
. Refer to page 52 for details on operation of the Watchdog.
t
TOUT
Figure 27. Watchdog Reset during Operation
VCC
RESET
MCU Status Register – MCUSR
WDT
TIME-OUT
RESET
TIME-OUT
INTERNAL
RESET
1 XTAL Cycle
t
TOUT
The MCU Status Register provides information on which reset source caused an MCU
reset.
Bit 7 654321 0
$34 ($54) – –––––EXTRFPORFMCUSR
Read/Write R RRRRRR/WR/W
Initial Value0 00000See bit description
• Bits 7..2 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
• Bit 1 – EXTRF: External Reset Flag
After a Power-on Reset, this bit is undefined (X). It will be set by an external reset. A
Watchdog reset will leave this bit unchanged.
• Bit 0 – PORF: Power-on Reset Flag
28
This bit is set by a Power-on Reset. A Watchdog Reset or an External Reset will leave
this bit unchanged.
To summarize, Table 7 shows the value of these two bits after the three modes of reset:
Table 7. PORF and EXTRF Values after Reset
Reset Source EXTRF PORF
Power-on Reset undefined 1
External Reset 1 unchanged
Watchdog Reset unchanged unchanged
To make use of these bits to identify a reset condition, the user software should clear
both the PORF and EXTRF bits as early as possible in the program. Checking the
PORF and EXTRF values is done before the bits are cleared. If the bit is cleared before
an external or Watchdog reset occurs, the source of reset can be found by using the following truth table, Table 8.
ATmega103(L)
0945G–09/01
ATmega103(L)
Table 8. Reset Source Identification
Reset Source EXTRF PORF
Watchdog Reset 0 0
Power-on Reset 0 1
External Reset 1 0
Power-on Reset 1 1
Interrupt Handling The ATmega103(L) has two dedicated 8-bit Interrupt Mask control registers; EIMSK
(External Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register). In
addition, other enable and mask bits can be found in the peripheral control registers.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
External Interrupt Mask Register – EIMSK
If an interrupt condition occurs when the corresponding interrupt enable bit is cleared
(zero), the interrupt flag will be set and remembered until the interrupt is enabled or the
flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one), and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt routine or restored when returning from an interrupt routine. This must be handled by
software.
Bit 7 6 5 4 3 2 1 0
$39 ($59) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 EIMSK
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bits 7..4 – INT7 - INT4: External Interrupt Request 7 - 4 Enable
When an INT7 - INT4 bit is set (one) and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control
bits in the External Interrupt Control Register (EICR) define whether the external interrupt is activated on rising or falling edge or is level-sensed. Activity on any of these pins
will trigger an interrupt request even if the pin is enabled as an output. This provides a
way of generating a software interrupt.
• Bits 3..0 – INT3 - INT0: External Interrupt Request 3 - 0 Enable
0945G–09/01
When an INT3 - INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The external interrupts are
always low-level triggered interrupts. Activity on any of these pins will trigger an interrupt
29
External Interrupt Flag Register – EIFR
External Interrupt Control Register – EICR
request even if the pin is enabled as an output. This provides a way of generating a software interrupt. When enabled, a level-triggered interrupt will generate an interrupt
request as long as the pin is held low.
Bit 7 6 5 4 3 2 1 0
$38 ($58) INTF7 INTF6 INTF5 INTF4 – – – – EIFR
Read/Write R/W R/W R/W R/W R R R R
Initial Value 0 0 0 0 0 0 0 0
• Bits 7..4 – INTF7 - INTF4: External Interrupt 7 - 4 Flags
When an edge on the INT7 - INT4 pins triggers an interrupt request, the corresponding
interrupt flag, INTF7 - INTF4, becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7 - INT4 in EIMSK, is set (one), the MCU will jump to
the interrupt vector. The flag is cleared when the corresponding interrupt routine is executed. Alternatively, the flag is cleared by writing a logical “1” to it. These flags are
always cleared when INTF7 - INFT4 are configured as level interrupts.
• Bits 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
Bit 7 6 5 4 3 2 1 0
$3A ($5A) ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
• Bits 7..0 – ISCX1, ISCX0: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7 - INT4 if the SREG
I-flag and the corresponding interrupt mask in the EIMSK are set. The level and edges
on the external pins that activate the interrupts are defined in Table 9.
Table 9. Interrupt Sense Control
ISCX1 ISCX0 Description
0 0 The low level of INTX generates an interrupt request.
01Reserved
1 0 The falling edge of INTX generates an interrupt request.
1 1 The rising edge of INTX generates an interrupt request.
The value on the INTX pin is sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low-level
interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level-triggered interrupt will
generate an interrupt request as long as the pin is held low.
30
ATmega103(L)
0945G–09/01
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