Atmel AVR ATasicICE POD User Manual
ATasicICE POD
www.BDTIC.com/ATMEL
User Guide
June 1998
ATasicICE POD
www.BDTIC.com/ATMEL
User Guide
1.0 Introduction
1.1 Descripti on of
the ASIC ICE Pod
The AVR ATasicICE POD is an ex tension to the AVR ATasicICE (ASIC ICE) wh ich
gives a quick start ASIC development platform for the AVR ASIC users. The ASIC POD
includes two example designs to demonstrate the interface between the AVR core and
the custom logic.
The ASIC ICE POD is bas ed on a fiel d programmable g ate array ( FPGA) that c an be
programmed to function as a custom I/O logic for the AVR core. A set of 64 I/O pins from
the FPGA are made available to the user through connectors. In addition, the ASIC ICE
POD includes SRAM, RS232 ports, and a clock oscillator as on-board resources.
Figure 1-1.
ASIC ICE POD Bl ock Diagram
AVR ATASICICE
HOST PC
W/ AVR
STUDIO
HOST
INTERFACE
CLOCK
GENERATION
LOGIC
AVR V2 CORE
ADR
CTRL
DBUS
PROGRAM
MEMORY
INTERNAL
DATA
MEMORY
This document describes how to configure the FPGA and to use the on-board resources
to the ASIC ICE POD. The ASIC ICE interface is d escribed in the ICEPRO ASIC
Designer’s Guide together with the example designs.
1.2 Power Supply
ATasicICE POD User Guide 1
It is recommended t o u se the emulator power supp ly wh ich i s av ailable on the pod connector. This is done by adding a jumper to the JP2 pins (default setting, see Figure 1-2).
Total current drawn from the emulator must not exceed 1A (@ 5V). At higher currents
POD INTERFACE
POD
ATasicICE POD User Guide
M1
M1M0
M2
M2
M0
JP4
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external power should be used instead. When using an external power supply the
jumper at JP2 must be removed.
WARNING! When using external power, the emulator must be switched on before the
external power supply is connected. The external power must be switched off before the
emulator is switched off.
1.3 FPGA
Configuration
Figure 1-2.
POD, FPGA Configuration
EXTERNAL
POWER
CONFIG DONE
LED
XCHECKER
XCHECKER
CONNECTOR
CONNECTOR
MODE SELECT
FPGA CONFIG.
MEMORY
The FPGA can be configured either by using an XChecker cable or a FLASH memory
containing the configuration data. Figure 1-2 shows the pod’s location of the XChecker
cable connector, the PLCC socket for the FLASH memory and the mode select jumpers.
The (green) conf igur ation DON E LED wi ll be li t if the configur atio n proces s is suc cessful.
1.3.1 Configuration Mode
Selection
The mode select jumpers (JP4) must be installed according to the following table:
Source M0 M1 M2
XChecker - - FLASH X X -
Note: (X = Jumper inserted, - = No jumper inserted)
Figure 1-3.
Mode Select Jumper Pin-Out
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1.3.2 Configuration Using
the XChecker Cable
1.3.3 Configuration Using
FLASH
1.3.4 FPGA ASIC ICE
Interface Pin-out
Disconnect any power sources connected to the pod and turn off the emulator. Connect
the XChecker cable directly to the XChecker connector on the pod. It is not necessary to
use the flying lead connectors supplied with the XChecker. Supply power and start the
downloading from the XChecker download utility.
WARNING! If the XChecker cable is used to configure the FPGA, the FLASH must be
removed from the socket.
Generate a binary file from the bit configura tion file using the Xilinx makepro m utility.
Use this file to progra m th e FLA SH in a de vi ce progr a mme r. Sup porte d FLA SH dev ic es
are: AT29C010-JC, AT29 C010 A- J C and AT2 9C02 0- JC . Disc onn ec t an y p ower sources
connected to the pod and turn off the emulator. Insert the programmed flash into the
configuration socket on the pod and set the configuration mode jumpers.
Memory Signals
Signal Name FPGA pin-out (physical pin number)
ADR 15:0 = {237, 235, 231, 229, 226, 224, 218, 216, 236, 234, 230, 228, 225, 223,
217, 215}
DBUS 7:0 = {13, 12, 11, 10, 9, 8, 5, 4}
XRAMRE = {23}
XRAMWE = {24}
IORE = {25}
IOWE = {26}
MRAMACK = {27}
CPUWAIT = {34}
Note: Pin numbering = {MSB,..., LSB}
System (Reset / Instruction) Signals
Signal Name FPGA pin-out (physical pin number)
ARESET
IRESET = {20}
SLEEPI = {16}
WDRI = {18}
Interrupt Signals
Signal Name FPGA pin-out (physical pin number)
IRQ 4:0 = {50, 49, 48, 47, 46}
IRQACK = {51}
GLOBINT = {52}
IRQOK = {53}
Note: Pin numbering = {MSB,..., LSB}
= {15}
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Extended Signals (Reserved For Future Use)
Signal Name FPGA pin-out (physical pin number)
IOEXTEND 4:0 = {43, 42, 41, 39, 38}
Note: Pin numbering = {MSB,..., LSB}
Clocks
Signal Name FPGA pin-out (physical pin number)
CLKALWAYS = {57}
EXTCLKIN = {not connected to the FPGA}
EXTCLKEN = {not connected to the FPGA}
CLKRUN = {31}
CLKOSC = {63}
CLKIO = {118}
CLKSTOPIO = {32}
CLKSTOPCORE = {33}
CLKEN = {44}
IOBUSY = {28}
1.4 General I/O Ports
The general I/O por t conne ctors ar e labeled P ORTA-P ORTH on th e pod ca rd. Th ese
ports are direct ly conne cted to th e FPGA. E ach port h as eigh t I/O pins an d two groun d
pins. Short cables should be used when connecting additional logic on the port pins.
Figure 1-4.
Port Connector Pin-Out
PORTx
06
2
GND
WARNING!
The general I/O ports are sensitive to electrostatic discharges.
Ports
Signal Name FPGA pin-out (physical pin number)
PORTA 7:0
(GIO 7:0)
PORTB 7:0
(GIO 15:8)
PORTC 7:0
(GIO 23:16)
PORTD 7:0
(GIO 31:24)
= {167, 168, 169, 170, 171, 172, 175, 176}
= {155, 156, 157, 160, 162, 163, 164, 165}
= {142, 144, 145, 146, 147, 149, 153, 154}
= {131, 132, 133, 134, 136, 137, 138, 139}
4
7GND 1
3
5
PORTE 7:0
(GIO 39:32)
= {116, 117, 124, 125, 126, 127, 128, 130}
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