ATMEL AVR1508 User Manual

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AVR1508: Xplain training - XMEGA DAC

Features

• Required knowledge

AVR1500: Xplain training – XMEGA™ Basic
AVR1502: Xplain training – XMEGA Direct Memory Access Controller

• Software prerequisites

Atmel
WinAVR/GCC 20100110 or later

• Hardware prerequisites

Xplain evaluation board
JTAGICE mkII

• Estimated completion time

2 hours

1 Introduction

Before starting with this training, it is recommended to do the Atmel XMEGA-Basics
training. For more information about the Atmel XMEGA Digital to Analog Converter
(DAC), please refer to the corresponding data sheet, the Atmel XMEGA Manual
and the AVR1301 application note.

®

AVR® Studio® 4.18 or later

8-bit
Microcontrollers

Application Note

The XMEGA DAC converts digital signals to analog signals. This can be used in
applications where you want stereo sound, signal generation, calibration or signal
compensation.

This training will show how to set up and use the DAC with practical code
examples.

Figure 1-1. DAC Overview

Rev. 8317A-AVR-06/10

2 Module Overview

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This section provides an overview of the basic configuration options and functionality
of the DAC.

2.1 Conversion Triggers

A DAC conversion can be triggered either by (1) the data registers being written to or
(2) from an incoming event from the Atmel XMEGA Event System.

2.2 Single and Dual Channel Operation

The DAC module contains two data channels with corresponding data registers, but
only one conversion block. The user can choose between using channel 0 as a
continuous-drive output or both channels as two Sample/Hold outputs.

2.2.1 Single Channel Operation

2.2.2 Dual Channel Operation

The channel operation mode is configured with the Channel Select bitfield (
Control Register B (

In Single Channel mod
is always connected to the data registers and the output driver stage of channel 0,
hence the concept continuous-drive output.

Figure 2-1 shows the DAC in single channel op
Hold stage is bypassed compared to Figure 1-1.

Figure 2-1. Single Channel

In dual ch
for channel 0 and 1. Thus, sample and hold blocks are used to keep the output values
between conversions. To be able to maintain a stable output value on the two
outputs, the channels must be refreshed regularly.

ann

CTRLB).

e, only one of the two channels is used. The conversion block

eration mode. Note that the Sample /

Operation

el mode, the DAC conversion block is alternately used to convert values

CHSEL) in

A refresh of the channel means that its value is converted and output again. This is
necessary because the Sample/Hold circuit will lose its analog signal voltage over
time, just like the voltage over a capacitor that is discharging through a parallel
resistor.

Note that a higher refresh rate causes higher power consumption (for details, please
refer to the data sheet).

The sample interval is the time to store (sample) a value for analog output. This is
analogous to charging a capacitor. If the sample time is too long, you may lose
information from signals with high slew rate (steep curved signals). If the sample rate

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is slower than the refresh rate, the DAC module has an internal refresh interval
generator as well. The automatic refresh interval is configured with the Refresh
Timing Control bitfield (

Note that manual conversions or event triggering does not affect the refresh interval.
This means that the channels will be refreshed at constant intervals even if extra
conversions are done in between, caused by for instance a manual update of a data
register.

Figure 2-2. Channel refresh and conversion request

REFRESH) in the Timing Control register (TIMCTRL).

AVR1508

Figure 2-2 shows an example. Each sample is done in time int
Sample Interval. After sampling Channel 0, the Channel 1 is sampled, and this may
be repeated if using the automatic refresh feature, see number 1 in the Figure 2-2. If

annel

a ch
the numbers 2, 4 and 6 in Figure 2-2.

2.3 Left and Right Adjusted Values

The Atmel XMEGA DAC module can be configured to accept left adjusted values by
setting the Left-adjust Value bit (LEFTADJ) in Control Register C (CTRLC). Figure 2-3

s the difference between right and left adjusted values in the DAC value

show
registers.

Figure 2-3. Left and Right Adjusted Values

e

rvals; we call it a

conversion is requested, there will be additional updates, for instances, see

8317A-AVR-06/10

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The 12-bit input value to the DAC contains two 8-bit registers, referred to as the high

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and low registers. By default, the 12-bit value is distributed with the 8 LSB in the low
register and 4 MSB in the high register.

In some applications, it is useful to work with left-adjusted data. This could be if, for
instance, storing 8-bit data to the DAC and using the high-byte register only (8 MSB).

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