ATMEL AVR1502 User Manual

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AVR1502: Xplain Training - Direct Memory

Access Controller

Prerequisites

• Required knowledge

AVR1500: Xplain Training - XMEGA

• Software prerequisites

Atmel® AVR® Studio® 4.18 or later
WinAVR/GCC 20100110 or later

• Hardware prerequisites

JTAGICE mkII
Xplain evaluation board

• Estimated completion time:

2 hours

1 Introduction

This application note covers the basic features of the Atmel XMEGA Direct Memory
Access Controller (DMAC). The goal for this training is to getting started with
simple memory transfers almost without using CPU time, and reading and writing
to peripherals with hardly any CPU intervention.

™

Basics

8-bit
Microcontrollers

Application Note

There are four DMA channels that have individual source, destination, triggers and
block sizes. The DMA Controller can move data from one memory area to another,
between memories and peripherals and between peripherals.

Rev. 8310A-AVR-06/10

2 Setting up the DMA Controller

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The Atmel XMEGA Direct Memory Access Controller (DMAC) is a highly flexible four­channel DMA Controller capable of transferring data between memories and
peripherals with minimal CPU intervention. While the CPU spends time in low-power
sleep modes or performs other tasks, the XMEGA DMAC offloads the CPU by taking
care of mere data copying from one area to another. The following sub-chapters are
meant to complement the understanding when doing the tasks in this training.

2.1 DMA Transaction

A complete DMA read and write operation between memories and/or peripherals is
called a DMA transaction. A transaction is done in data blocks and the size of the
transaction (number of bytes to transfer) is selectable from software and controlled by
the block size and repeat counter settings. Each block transfer is divided into smaller
bursts, see Figure 2-1.

Figure 2-1. DMA Transaction

2.2 Addressing

When a DMA channel requests a data transfer, the bus arbiter will wait until the AVR
core is not using the data bus and permit the DMA Controller to transfer data.
Transfers are done in bursts of 1, 2, 4 or 8 bytes. Addressing can be static,
incremental or decremental. Automatic reload of source and/or destination address
can be done after each burst transfer, block transfer, when transfer is complete, or
disabled. DMA transfers can be triggered by application software, peripherals and
events.

The size of the block transfer is set by the Block Transfer Count Register, and can be
anything from 1 byte to 64 Kbytes. A repeat counter can be enabled to set a number
of repeated block transfers before a transaction is complete. The repeat is from 1 to
255 and unlimited repeat count can be achieved by setting the repeat count to zero.

A bus arbiter controls when the DMA controller and the AVR core can use the bus.
The core always has priority, so as long as the core request access to the bus, any
pending burst transfer must wait. The core requests bus access when it executes an
instruction that write or read data to SRAM, IO memory, EEPROM and the External
Bus Interface.

If the source or destination is SRAM, the user will most likely want to increment or
decrement the address pointer. Therefore, it is possible to set the DMAC source /
destination in incremental or decremental mode.

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AVR1502

8310A-AVR-06/10

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SRAM
Address

The DMAC will increment the
address pointer automatically in
incremental mode

In incremental mode, the DMAC will start at the source address. After the first byte
has been sent, the next byte will be read from the previous address plus one.

In decremental mode, it is opposite, where the DMAC will start at a given source
address and proceed with the previous addresses.

The original source and destination addresses are stored by the DMA controller, so
that the source and destination addresses can be individually configured to be
reloaded at the following points:

• End of each burst transfer

• End of each block transfer

• End of transaction

• Never reload

When using the DMAC with a peripheral, such as the SPI, the data register is fixed,
and it is important that the addressing mode is static.

0x2066 34
0x2067 76
0x2068 13
0x2069 113

Value

AVR1502

2.3 Transfer Triggers

2.4 Interrupts

The main purpose of the DMA triggers is to synchronize the peripherals with the
transfer rate. For instance, when using the USART and transferring at 9600 baud, the
DMA should not be triggered more often than the transfer complete flag is set.

DMA transfers can only be started when a DMA transfer request is detected. A
transfer request can be triggered from software, from an external trigger source
(peripheral) or from an event. There are dedicated source trigger selections for each
DMA channel. The available trigger sources may vary from one device to another,
depending on the modules or peripherals that exist in the device (see the XMEGA
manual for different transfer triggers).

The DMA Controller can generate interrupts when an error is detected on a DMA
channel or when a transaction is complete for a DMA channel. Each DMA channel
has a separate interrupt vector, and there are different interrupt flags for error and
transaction complete. If repeat is not enabled the transaction complete flag is set at
the end of the Block Transfer. If unlimited repeat is enabled, the transaction complete
flag is also set at the end of each Block Transfer.

8310A-AVR-06/10

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