ATMEL AVR User Manual

Farnell Order Code Equinox Order Code

111-806 EQ-8051-ST1 (UK)
302-2249 AVR-DV1 (UK)
302-2286 UISP-S4
302-2298 UISP-LV4

111-715 MPW-PLUS (UK)
302-2225 SG-ALLWRITER

111-788 AVR-BAS-LIT
302-2330 AVR-BAS-FULL
302-2365 SS-90S8515-P

* Max speed depends on Vcc voltage. Frequencies and Currents listed are for

Vcc = 5.0V & T = 25ºC

Please verify correct part codes for low voltage parts before ordering.

Key

SRAM - Static RAM

ISP - In-System Programmable

I/O - Input/Output

ADC - Analogue to Digital Convertor

SPI - Serial Peripheral Interface

PWM - Pulse Width Modulation

PAR - Parallel programming mode

FLASH - Reprogrammable Code Memory

EEPROM - Parallel programming mode

Atmel AVR Microcontroller Family - Product Selection Guide

For further information please contact Equinox Technologies UK Ltd on Tel: [phone] Fax: [phone] E-mail: [e-mail]

Disclaimer: Whilst information is supplied in good faith, we are not liable for any errors or omissions. Please consult the relevant Atmel datasheet. E&OE

DEVICE 90S1200 90S2313 90S2343 90S4414 90S8515 90S2333 90S8535 MEGA603 MEGA103

ON-CHIP MEMORY

FLASH (Bytes) 1K 2K 2K 4K 8K 2K 8K 64K 128K
EEPROM (Bytes) 64 128 128 256 512 128 512 2K 4K
SRAM (Bytes) 0 128 128 256 512 128 512 4K 4K
In-System Programmable (ISP) YES YES YES YES YES YES YES YES YES

HARDWARE FEATURES

I/O Pins 15 15 5 32 32 20 32 32I/O, 8O, 8I 32I/O, 8O, 8I
On-chip RC Oscillator YES NO YES NO NO NO NO NO NO
Real Time Clock (RTC) NO NO NO NO NO NO NO YES YES
SPI Port NO NO NO YES YES YES YES YES YES
Full Duplex Serial UART NO YES NO YES YES YES YES 1 1
Watchdog Timer YES YES YES YES YES YES YES YES YES
Timer/Counters 122222 233
PWM Channels (10-bit) - 1 - 2 2 1 TBA 2 2
Analogue Comparator YES YES NO NO NO NO NO NO NO
ADC NO NO NO NO NO 6CH/10BIT 8CH/10BIT 8CH/10BIT 8CH/10BIT
IDLE and Power Down modes YES YES YES YES YES YES YES YES YES
Interrupts 4113131314172424

MISCELLANEOUS

AVR Instructions 89 118 118 118 118 118 120 121 121
Max External Clock Frequency 12MHz 10MHz 10MHz 8MHz 8MHz 8MHz 8MHz 6MHz 6MHz
Vcc Voltage Range (V) 4.0-6.0V 4.0-6.0V 4.0-6.0V 4.0-6.0V 4.0-6.0V 4.0-6.0V 4.0-6.0V 4.0-6.0V 4.0-6.0V

EQUINOX SUPPORT TOOLS

AVR Starter System ISP/PAR ISP/PAR ISP/PAR ISP/PAR ISP/PAR ISP/PAR ISP only ACT-UPG1 ACT-UPG1
AVR Development System ZIF-ISP ZIF-ISP ZIF-ISP ZIF-ISP ZIF-ISP ZIF-ISP ZIF-ISP UISP-UPG1 UISP-UPG1
Micro-ISP Series IV Programmer ISP only ISP only ISP only ISP only ISP only ISP only ISP only ISP only ISP only
Micro-ISP Series IV LV Prog. ISP only ISP only ISP only ISP only ISP only ISP only ISP only ISP only ISP only
Micro-Pro Device Programmer PAR only PAR only - ZIF-ISP ZIF-ISP - - - -
AllWriter Universal Programmer PAR PAR - PAR PAR - - - -
AVR BASIC LITE YES (1K) - - - - - - - -
AVR BASIC FULL YES YES YES YES YES YES YES YES YES
AT90S8515 Socket Stealer (DIL-40) NO NO NO YES YES NO NO NO NO

Atmel AVR Microcontroller Family - Product Selection Guide

For further information please contact Equinox Technologies UK Ltd on Tel: [phone] Fax: [phone] E-mail: [e-mail]

Disclaimer: Whilst information is supplied in good faith, we are not liable for any errors or omissions. Please consult the relevant Atmel datasheet. E&OE

Farnell Order Code Equinox Order Code

303-1068 SS-90S8515-J

121-022 UC-PM1

Continued....

Device 90S1200 90S2313 90S2343 90S4414 90S8515 90S2333 90S8535 MEGA603 MEGA103

EQUINOX SUPPORT TOOLS

AT90S8515 Socket Stealer (PLCC) NO NO NO YES YES NO NO NO NO
DOBOX-MOD1 YES YES YES YES YES NO YES NO NO

PACKAGE TYPES (Farnell Codes)
6AC - - - - - - - 120-984 120-972
8JC - - - 111-480 111-508 - 120-959 - ­8PC - - - 111-478 111-491 - 120-960 - ­10PC - 111-454 111-430 - - - - - ­10SC - 111-466 111-442 - - - - - ­12PC 690-752 - - - - - - - ­12SC 690-934 - - - - - - - -

Errata

•

Lock Bits at High V

•

Reset During EEPROM Write

•

Verifying EEPROM in System

•

Serial Programming at Voltages Below 3.0 Volts

CC

4. Lock Bits at High V

On some devices, the lock bits will not erase at hig h VCC. In this situation, it will
not be possible to reprogram the devices when the lock bits are set.

Problem Fix/Workaround

Lower V
unlock, and it will be possible to reprogram the device at any V

3. Reset During EEPROM Write

If reset is activated during EEPROM write the result is not what should be
expected. The EEPR OM write cyc le comple tes as norm al, but the ad dress reg is­ters are reset to 0. The result is that both the address written and address 0 in the
EEPROM can be corrupted.

Problem Fix/Workaround

Avoid using address 0 for storage , unles s you can guaran tee that you wi ll not ge t
a reset during EEPROM write.

2. Verifying EEPROM in System

EEPROM veri fy in I n-Sys tem P rogram ming mo de ca nnot op erat e with m aximu m
clock frequency. This is independent of the SPI clock frequency.

Problem Fix/Workaround

Reduce the clock speed, or avoid using the EEPROM verify feature.

1. Serial Programming at Voltages Below 3.0 Volts

At voltages below 3.0 Volts, serial programming might fail.

Problem Fix/Workaround

Keep V

below 4.0V before you perform a chip-erase. Then the device will

CC

above 3.0 Volts during in-system programming.

CC

CC

CC

.

8-Bit
Microcontroller
with 2K bytes
In-System
Programmable
Flash

AT90S2313
Rev. B
Errata Sheet

Rev. 1191B–01/99

1

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Fax-on-Demand

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© Atmel Corporation 1999.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war­ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop­erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
not authorized for use as critical components in life support devices or systems.

Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.

Printed on recycled paper.

1191B–01/99/xM

Features

•

Utilizes the AVR® RISC Architecture

•

AVR - High-performance and Low-power RISC Architecture

– 118 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 10 MIPS Throughput at 10 MHz

•

Data and Nonvolatile Program Memory

– 2K Bytes of In-System Programmable Flash

Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security

•

Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9- or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– SPI Serial Interface for In-System Programming
– Full Duplex UART

•

• Special Microcontroller Features
– Low-power Idle and Power Down Modes
– External and Internal Interrupt Sources

•

• Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation

•

Power Consumption at 4 MHz, 3V, 25°C

– Active: 2.8 mA
– Idle Mode: 0.8 mA
– Power Down Mode: <1 µA

•

I/O and Pac ka ges

– 15 Programmable I/O Lines
– 20-pin PDIP and SOIC

•

Operating Voltages

– 2.7 - 6.0V (AT90S2313-4)
– 4.0 - 6.0V (AT90S2313-10)

•

Speed Grades

– 0 - 4 MHz (AT90S2313-4)
– 0 - 10 MHz (AT90S2313-10)

8-bit
Microcontroller
with 2K bytes
In-System
Programmable
Flash

AT90S2313

Description

The AT90S2313 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the

(continued)

Pin Configuration

PDIP/SOIC

Note: This is a summary document. For the complete 87 page
document, please visit our web site at

[e-mail]

Rev. 0839ES–04/99

www.atmel.com

and request literature #0839E.

or e-mail at

1

AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consump­tion versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.

Block Diagram

Figure 1.

The AT90S2313 Block Diagram

2

AT90S2313

AT90S2313

The AT90S2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM,
128 bytes SRAM, 15 general purpose I/O lines, 32 general purpose working registers, flexible timer/counters with compare
modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscilla­tor, an SPI serial port for Flash Memory d ownloading and two software selec table power sav ing modes. The Idle Mode
stops the CPU while allowi ng the SRAM, timer/ counte rs, SPI po rt and i nterrup t syst em to contin ue func tionin g. The power
down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip In-System Program­mable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a
conventional non vo lat il e m emo ry p ro gramm er . B y co mbi ni ng an e nha nc ed RISC 8-bit CPU with In-System Programm abl e
Flash on a monolithic chip, the Atmel AT90S2313 is a powerful microcontroller that provides a highly flexible and cost
effective solution to many embedded control applications.

The AT90S2313 AVR is supported with a full suite of program and system development tools including: C compilers, macro
assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

GND

Ground pin.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). PB0 and PB1
also serve as th e pos itiv e in put (AI N0) a nd th e nega tive inpu t (AIN1 ), res pecti vely, of th e on-c hip a nalog com parator . The
Port B output buffers can sink 20mA and can drive LED displays directly. When pins PB0 to PB7 are used as inputs and
are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port B pins are tri-stated
when a reset condition becomes active, even if the clock is not active.

Port D (PD6..PD0)

Port D has seven bi-directional I/O port with internal pull-up resistors, PD6..PD0. The Port D output buffers can sink 20 mA.
As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins
are tri-stated when a reset condition becomes active, even if the clock is not active.

RESET

Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running. Shorter pulses
are not guaranteed to generate a reset.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

3

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means th at d ur ing one single clock cycle, one ALU (Ar ithmeti c Logic Unit) operation is executed. Two ope ra nds
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.

Figure 2.

The AT90S2313 AVR RISC Architecture

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address cal culation s. O ne of the three address point ers is also used a s the ad dress pointer for the c onst ant tabl e
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 2 shows the AT90S2313 AVR RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fa ct th at the regis ter file is as signe d the 32 lowerm ost Data S pace a ddre sses ($00 - $1F) , al lowin g
them to be accessed as though they were ordinary memory locations.

4

AT90S2313

AT90S2313

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and oth er I/O func tions. The I/O mem ory can be accessed di rectl y, or as the D ata Space lo catio ns foll ow­ing those of the register file, $20 - $5F.

The AVR has Harvard architecture - with separate memories and buses for pro gram and data. The progr am memory is
accessed with a two stage pipeline. While one instruc tion is being executed, the next instruction i s pre-fetched from the
program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-system
Programmable Flash memory.

With the relative jump and call instructions, the whole 1K address space is directly accessed. Most AVR instructions have a
single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

During interrupts and subroutine c alls, the ret urn address program counter (PC) is stor ed on the stac k. The stac k is
effectively allocated in the general data SRAM, and co ns equ entl y the sta ck s iz e i s onl y li mi ted b y the total SRAM size and
the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are
executed). The 8-bit stack pointer SP is read/write accessible in the I/O space.

The 128 bytes data SRAM + r egister file and I/O registe rs can be easil y accessed through the fi ve different addr essing
modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 3.

Memory Mapss

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrup ts have a sepa rate inter rupt vecto r in the interrupt ve ctor tab le at the beginn ing of the pro­gram memory. The different int errupts have pr iority in acco rdance with thei r interrupt vec tor position . The lower the
interrupt vector address the higher the priority.

5

Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

$3F ($5F) SREG I T H S V N Z C 19
$3E ($5E) Reserv ed
$3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 20
$3C ($5C) Reserved
$3B ($5B) GIMSK INT1 INT0 - - - - - -25
$3A ($5A) GIFR INTF1 INTF0

$39 ($59) TIMSK TOIE1 OCIE1A
$38 ($58) TIFR TOV1 OCF1A
$37 ($57) Reserv ed
$36 ($56) Reserv ed
$35 ($55) MCUCR - - SE SM ISC11 ISC10 I SC01 ISC00 28
$34 ($54) Reserv ed
$33 ($53) TCCR0 - - - - - CS02 CS01 CS00 31
$32 ($52) TCNT0 Timer/Counter0 (8 Bit) 31
$31 ($51) Reserv ed

$30 ($50) Reserv ed
$2F ($4F) TCCR1A COM1A1 COM1A0 - - - -PWM11PWM10 33
$2E ($4E) TCCR1B ICNC1 ICES1
$2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte 35
$2C ($4C) TCNT1L Timer/Counter1 - Counter Register Low Byte 35
$2B ($4B) OCR1AH Timer/Counter1 - Compare Register High Byte 36
$2A ($4A) OCR1AL Timer/Counter1 - Compare Register Low Byte 36

$29 ($49) Reserv ed

$28 ($48) Reserv ed

$27 ($47) Reserv ed

$26 ($46) Reserv ed

$25 ($45) ICR1H Timer/Counter1 - Input Capture Register High Byte 36

$24 ($44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 36

$23 ($43) Reserv ed

$22 ($42) Reserv ed

$21 ($41) WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 38

$20 ($40) Reserv ed
$1F ($3F) Reserved
$1E ($3E) EEAR - EEPROM Address Register 40
$1D ($3D) EEDR EEPROM Data register 40
$1C ($3C) EECR
$1B ($3B) Reserv ed
$1A ($3A) Reserv ed

$19 ($39) Reserv ed

$18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 50

$17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 50

$16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 50

$15 ($35) Reserv ed

$14 ($34) Reserv ed

$13 ($33) Reserv ed

$12 ($32) PORTD - PORTD6 P ORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 55

$11 ($31) DDRD

$10 ($30) PIND

... Reserved
$0C ($2C) UDR UART I/O Data Register 44
$0B ($2B) USR RXC TXC UDRE FE OR
$0A ($2A) UCR RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 45

$09 ($29) UBRR UART Baud Rate Register 47
$08 ($28) ACSR ACD

… Reserved

$00 ($20) Reserv ed

- - - - - EEMWE EEWE EERE 40

- DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 55

- PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 55

- ACO ACI ACIE ACIC ACIS1 ACIS0 48

- - TICIE1 - TOIE0 -26

- -ICF1-TOV0-27

. - CTC1 CS12 CS11 CS10 34

- - -45

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.

26

6

AT90S2313

AT90S2313

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers
ADC Rd, Rr Add with Carry two Registers
ADIW Rdl,K Add Immediate to Word
SUB Rd, Rr Subtract two Registers
SUBI Rd, K Subtract Constant from Register
SBIW Rdl,K Subtract Immediate from Word
SBC Rd, Rr Subtract with Carry two Registers
SBCI Rd, K Subtract with Carry Constant from Reg.
AND Rd, Rr Logical AND Registers
ANDI Rd, K Logical AND Register and Constant
OR Rd, Rr Logical OR Registers
ORI Rd, K Logical OR Register and Constant
EOR Rd, Rr Exclusive OR Registers
COM Rd One’s Complement
NEG Rd Two’s Complement
SBR Rd,K Set Bit(s) in Register
CBR Rd,K Clear Bit(s) in Register
INC Rd Increment
DEC Rd Decrement
TST Rd Test for Zero or Minus
CLR Rd Clear Register
SER Rd Set Register

BRANCH INSTRUCTIONS

RJMP k Relative Jump
IJMP Indirect Jump to (Z)
RCALL k Relative Subroutine Call
ICALL Indirect Call to (Z)
RET Subroutine Return
RETI Interrupt Return
CPSE Rd,Rr Compare, Skip if Equal
CP Rd,Rr Compare Rd
CPC Rd,Rr Compare with Carry Rd
CPI Rd,K Compare Register with Immediate Rd
SBRC Rr, b Skip if Bit in Register Cleared
SBRS Rr, b Skip if Bit in Register is Set
SBIC P, b Skip if Bit in I/O Register Cleared
SBIS P, b Skip if Bit in I/O Register is Set
BRBS s, k Branch if Status Flag Set
BRBC s, k Branch if Status Flag Cleared
BREQ k Branch if Equal
BRNE k Branch if Not Equal
BRCS k Branch if Carry Set
BRCC k Branch if Carry Cleared
BRSH k Branch if Same or Higher
BRLO k Branch if Lower
BRMI k Branch if Minus
BRPL k Branch if Plus
BRGE k Branch if Greater or Equal, Signed
BRLT k Branch if Less Than Zero, Signed
BRHS k Branch if Half Carry Flag Set
BRHC k Branch if Half Carry Flag Cleared
BRTS k Branch if T Flag Set
BRTC k Branch if T Flag Cleared
BRVS k Branch if Overflow Flag is Set
BRVC k Branch if Overflow Flag is Cleared
BRIE k Branch if Interrupt Enabled
BRID k Branch if Interrupt Disabled

Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd − Rr
Rd ← Rd − K
Rdh:Rdl ← Rdh:Rdl − K
Rd ← Rd − Rr − C
Rd ← Rd − K − C
Rd ← Rd • Rr
Rd ← Rd • K
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd ⊕ Rr
Rd ← $FF − Rd
Rd ← $00 − Rd
Rd ← Rd v K
Rd ← Rd • ($FF − K)
Rd ← Rd + 1
Rd ← Rd − 1
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← $FF

PC ← PC + k + 1
PC ← Z
PC ← PC + k + 1
PC ← Z
PC ← STACK
PC ← STACK
if (Rd = Rr) PC ← PC + 2 or 3

− Rr Z, N,V,C,H 1

− Rr − C Z, N,V,C,H 1

− K Z, N,V,C,H 1

if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (R(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC + k + 1
if (SREG(s) = 0) then PC←PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if (I = 1) then PC ← PC + k + 1
if (I = 0) then PC ← PC + k + 1

Z,C,N,V,H 1
Z,C,N,V,H 1
Z,C,N,V,S 2
Z,C,N,V,H 1
Z,C,N,V,H 1
Z,C,N,V,S 2
Z,C,N,V,H 1
Z,C,N,V,H 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,C,N,V 1
Z,C,N,V,H 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
Z,N,V 1
None 1

None 2
None 2
None 3
None 3
None 4
I4
None 1 / 2

None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2
None 1 / 2

7

Instruction Set Summary (Continued)

Mnemonics Operands Description Operation Flags #Clocks

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd
LDI Rd, K Load Immediate Rd
LD Rd, X Load Indirect Rd
LD Rd, X+ Load Indirect and Post-Inc. Rd
LD Rd, - X Load Indirect and Pre-Dec. X
LD Rd, Y Load Indirect Rd
LD Rd, Y+ Load Indirect and Post-Inc. Rd
LD Rd, - Y Load Indirect and Pre-Dec. Y
LDD Rd,Y+q Load Indirect with Displacement Rd
LD Rd, Z Load Indirect Rd
LD Rd, Z+ Load Indirect and Post-Inc. Rd
LD Rd, -Z Load Indirect and Pre-Dec. Z
LDD Rd, Z+q Load Indirect with Displacement Rd
LDS Rd, k Load Direct from SRAM Rd
ST X, Rr Store Indirect (X)
ST X+, Rr Store Indirect and Post-Inc. (X)
ST - X, Rr Store Indirect and Pre-Dec. X
ST Y, Rr Store Indirect (Y)
ST Y+, Rr Store Indirect and Post-Inc. (Y)
ST - Y, Rr Store Indirect and Pre-Dec. Y
STD Y+q,Rr Store Indirect with Displacement (Y + q)
ST Z, Rr Store Indirect (Z)
ST Z+, Rr Store Indirect and Post-Inc. (Z)
ST -Z, Rr Store Indirect and Pre-Dec. Z
STD Z+q,Rr Store Indirect with Displacement (Z + q)
STS k, Rr Store Direct to SRAM (k)
LPM Load Program Memory R 0
IN Rd, P In Port Rd
OUT P, Rr Out Port P
PUSH Rr Push Register on Stack STACK
POP Rd Pop Register from Stack Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b)
CBI P,b Clear Bit in I/O Register I/O(P,b)
LSL Rd Logical Shift Left Rd(n+1)
LSR Rd Logical Shift Right Rd(n)
ROL Rd Rotate Left Through Carry Rd(0)
ROR Rd Rotate Right Through Carry Rd(7)
ASR Rd Arithmetic Shift Right Rd(n)
SWAP Rd Swap Nibbles Rd(3..0)
BSET s Flag Set SREG(s)
BCLR s Flag Clear SREG(s)
BST Rr, b Bit Store from Register to T T
BLD Rd, b Bit load from T to Register Rd(b)
SEC Set Carry C
CLC Clear Carry C
SEN Set Negative Flag N
CLN Clear Negative Flag N
SEZ Set Zero Flag Z
CLZ Clear Zero Flag Z
SEI Global Interrupt Enable I
CLI Global Interrupt Disable I
SES Set Signed Test Flag S
CLS Clear Signed Test Flag S
SEV Set Twos Complement Overflow V
CLV Clear Twos Complement Overflow V
SET Set T in SREG T
CLT Clear T in SREG T
SEH Set Half Carry Flag in SREG H
CLH Clear Half Carry Flag in SREG H
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 3
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

← Rr None 1

← KNone1
← (X) None 2
← (X), X ← X + 1 None 2

← X − 1, Rd ← (X) None 2

← (Y) None 2
← (Y), Y ← Y + 1 None 2

← Y − 1, Rd ← (Y) None 2

← (Y + q) None 2
← (Z) None 2
← (Z), Z ← Z+1 None 2

← Z - 1, Rd ← (Z) None 2

← (Z + q) None 2

← (k) None 2
← Rr None 2
← Rr, X ← X + 1 None 2

← X - 1, (X) ← Rr None 2

← Rr None 2
← Rr, Y ← Y + 1 None 2

← Y - 1, (Y) ← Rr None 2

← Rr None 2
← Rr None 2
← Rr, Z ← Z + 1 None 2

← Z - 1, (Z) ← Rr None 2

← Rr None 2

← Rr None 2

← (Z) None 3
← PNone1

← Rr None 1

← Rr None 2

← STACK None 2

← 1None2
← 0None2

← Rd(n), Rd(0) ← 0 Z,C,N,V 1

← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

← Rd(n+1), n=0..6 Z,C,N,V 1

←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

← 1 SREG(s) 1
← 0 SREG(s) 1

← Rr(b) T 1

← TNone1

← 1C1
← 0 C 1
← 1N1
← 0 N 1
← 1Z1

← 0 Z 1
← 1I1
← 0 I 1

← 1S1

← 0 S 1

← 1V1

← 0 V 1

← 1T1

← 0 T 1

← 1H1

← 0 H 1

8

AT90S2313

AT90S2313

Ordering Information

Speed (MHz) Power Supply Ordering Code Package Operation Range

4 2.7 - 6.0V AT90S2313-4PC

AT90S2313-4SC
AT90S2313-4PI

AT90S2313-4SI

10 4.0 - 6.0V AT90S2313-10PC

AT90S2313-10SC
AT90S2313-10PI

AT90S2313-10SI

20P3
20S

20P3
20S

20P3
20S

20P3
20S

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Commercial

(0°C to 70°C)

Industrial

(-40°C to 85°C)

Package Type

20P3 20-lead, 0.300" Wide, Plastic Dual In-Line Package (PDIP)
20S 20-lead, 0.300" Wide, Plastic Gull-Wing Small Outline (SOIC)

9

Packaging Information

20P3,

20-lead, 0.300" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-001 BA

1.060(26.9)

.210(5.33)

SEATING

PLANE

.980(24.9)

.900(22.86) REF

MAX

.150(3.81)
.115(2.92)

.110(2.79)
.090(2.29)

.014(.356)
.008(.203)

PIN

1

.070(1.78)
.045(1.13)

.325(8.26)
.300(7.62)

0

REF

15

.430(10.92) MAX

.022(.559)
.014(.356)

.280(7.11)
.240(6.10)

.090(2.29)

MAX

.005(.127)

MIN

.015(.381) MIN

20S,

20-lead, 0.300" Wide,
Plastic Gull-Wing Small Outline (SOIC)
Dimensions in Inches and (Millimeters)

0.020 (0.508)

0.013 (0.330)

0.299 (7.60)

PIN 1

0
8

REF

0.035 (0.889)

0.015 (0.381)

.050 (1.27) BSC

0.513 (13.0)

0.497 (12.6)

0.012 (0.305)

0.003 (0.076)

0.291 (7.39)

0.013 (0.330)

0.009 (0.229)

0.420 (10.7)

0.393 (9.98)

0.105 (2.67)

0.092 (2.34)

10

AT90S2313

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway
San Jose, CA 95131
TEL [phone]
FAX [phone]

Europe

Atmel U.K., Ltd.
Coliseum Business Centre
Riverside Way
Camberley, Surrey GU15 3YL
England
TEL [phone]
FAX [phone]

Asia

Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
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East Kowloon
Hong Kong
TEL [phone]
FAX [phone]

Japan

Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinka wa
Chuo-ku, Tokyo 104-0033
Japan
TEL [phone]
FAX [phone]

Atmel Colorado Springs

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Colorado Springs, CO 80906
TEL [phone]
FAX [phone]

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Zone Indu strie lle
13106 Rousset Cedex
France
TEL [phone]
FAX [phone]

Fax-on-Demand

North America:
1-[phone]

International:
1-[phone]

e-mail

[e-mail]

Web Site

http://www.atmel.com

BBS

1-[phone]

© Atmel Corporation 1999.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war­ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual prop­erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are
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Terms and product names in this document may be trademarks of others.

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0839ES–04/99/xM