Atmel Avr Service Manual

Introduction

This document contains the latest information about the AVR data book and the AVR data sheets.

All references to the data book refers to the August 1999 version of the “AVR MICROCONTROLLER DATA BOOK”.

All references to the A VR data she ets refer to the latest version of the AVR d ata sheets on Atmel’s web page www.atmel.com

RISC

The data she ets on Atmel’s w eb pa ge are updated more frequen tly than the p rinted data book. All known errors in each data sheet are corrected wh en a new v ersion is released.

This document contains known errors that have not been corrected yet. All designers using AVR microcontrollers should use this document together with the data sheets. It is updated frequently, and should contain a complete list of all known documentation errors at any given time.

Please note that this document only covers errors in the AVR documentation. For errors in the AVR microcontrollers, see the errata sheet for each device.

If you find errors in the documentation that are not listed in this document, please send an email to the AVR support line avr@atmel.com

Overview of data sheets

Part Number Data Sheet Revision

in the August 1999

AVR Data Book

AT90S1200 0838E-04/99 0838E-04/99 AT90S2313 0839E-04/99 0839E-04/99 AT90S/LS2323 and AT90S/LS2343 1004B-04/99 1004B-04/99 AT90S/LS2333 and AT90S/LS4443 1042D-04/99 1042D-04/99 AT90S4414/8515 0841E-04/99 0841E-04/99 AT90S/LS4434 and AT90S/LS8535 1041E-04/99 1041E-04/99 AT90C8534 1229A-04/99 1229A-04/99 ATtiny10/11/12 1006A-04/99 1006B-10/99 ATtiny15 1187A-06/99 1187B-11/99 ATtiny22/22L 1273A-04/99 1273A-04/99 ATmega161/161L 1228A-05/99 1228A-08/99 ATmega603/603L and ATmega103/103L 0945D-06/99 0945E-12/99 AVR Instruction Set 0856B-06/99 0856B-06/99 ATtiny28 N/A 1062B-10/99

Data Sheet Revision

on Atmel’s web site

www.atmel.com

8-Bit Microcontroller

Data Book Updates and Changes

Rev. 12/99A

AT90S1200

The latest data sheet on the web is rev. 0838E-04/99. The data sheet in the printed data book is rev. 0838E-04/99.

Changes in the AT90S1200 Data Sheet:

Page: Change or Add:

2-3 In feature list under

I/O and packages,

replace “20-pin PDIP and SOIC” by “20-pin PDIP, SOIC and SSOP”.

2-20 Table 4: remove this note: “Not e: When ch anging the ISC01/ ISC00 bit s, INT0 must be disabl ed by cl earing its Int er-

rupt Enable bit in the GIMSK registe r. Otherwise an interrupt can occur when the bits are changed. ”

2-25 In the note for Table 6, add “To avoid unintenti onal MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.” In the

EEPROM Read/Write Access

description,

change

“When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.”

2-26 In the

Bit 0 - EERE: EEPROM Read Enable

description,

change

“When EERE has been set, the CPU i s halt ed f or two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four clock cycles before the next instruction is executed.”

2-27 In the

Analog Comparator Control and Status Register

description, change the initial value of ACO from “0” to

“N/A”.

2-29 in the 2-33 in the

Port B Input Pins Address - PINB Port D Input Pins Address - PIND

description, change the Initial Values from “Hi-Z” to “N/A”. description, change the Initial Values of bits 0 to 6 from “Hi-Z” to “N/A”.

2-44 Replace figure 34 by the one below:

Figure

34 Serial Programming and Verify

VCC

PB7 PB6 PB5

2.7 - 6.0

SCK MISO MOSI

AT90S1200

GND

CLOCK INPUT

Data Book Updates and Changes

RESET

XTAL1 GND

Data Book Updates and Changes

2-49: Replace the row bel ow in

ACIO

Analog Comparator Input Offset Voltage

by:

ACIO

2-50 In first l ine of

Analog Comparator Input Offset Voltage

Typical Characteristics

are not tested during manufacturing.”.

2-62 In

, replace “2-2-xx” by “2-xx”.

DC characteristics

VCC = 5V 40 mV

VCC = 5V Vin = VCC /2

40 mV

, change “These data are characterized, but not tested.” to “These figures

AT90S2313

The latest data sheet on the web is rev. 0839E-04/99. The data sheet in the printed data book is rev. 0839E-04/99.

Changes in the AT90S2313 Data Sheet:

Page: Change or Add:

3-28 Table 5: remove this note: “Note: W hen changing th e ISC11/ISC10 bits, INT1 must be disable d by clea ring it s Inter -

rupt Enable bit in the GIMSK registe r. Otherwise an interrupt can occur when the bits are changed. ”

3-29 Table 6: remove this note: “Not e: When ch anging the ISC01/ ISC00 bit s, INT0 must be disabl ed by cl earing its Int er-

rupt Enable bit in the GIMSK registe r. Otherwise an interrupt can occur when the bits are changed. ”

3-38 On the top of the page, add paragraph “Note: If the compare register contains the TOP value and the prescaler is

not in use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-counting and down-counting values are reached simultaneously. When the prescaler is in use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter reaches the TOP value, but the down-counting compare match is not interpreted to be reached before the next time the counter reaches the TOP-value, making a one period PWM pulse.”

3-39 In the note for Table 14, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.” In the

halted for two clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.”

3-40 In the

EECR” to “4. Write a lo gical on e to the EEMWE bit in EECR (to be a ble to wr ite a l ogical one to the EEMWE bit, t he EEWE bit must be written to zero in the same cycle).”

3-41 In the

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four clock cycles before the next instruction is executed.”

3-47 In the

“N/A”.

3-49 in the 3-54 in the 3-67 Replace figure 34 by the one below:

EEPROM Read/Write Access

Bit1 - EEWE: EEPROM Write Enable

Bit 0 - EERE: EEPROM Read Enable

Analog Comparator Control and Status Register

Port B Input Pins Address - PINB Port D Input Pins Address - PIND

description,

description, change the Initial Values from “Hi-Z” to “N/A”. description, change the Initial Values of bits 0 to 6 from “Hi-Z” to “N/A”.

change

description,

“When the EEPROM is read or written, the CPU is

change

description, change the initial value of ACO from “0” to

“4. Write a logical one to the EEMWE bit in

“When EERE has been set, the CPU i s halt ed f or

Data Book Updates and Changes

Figure

53 Serial Programming and Verify

3-72: Replace the row bel ow in

ACIO

Analog Comparator Input Offset Voltage

by:

ACIO

Analog Comparator Input Offset Voltage

GND

CLOCK INPUT

DC characteristics

AT90S2313

RESET

XTAL1 GND

VCC

PB7 PB6 PB5

2.7 - 6.0

SCK MISO MOSI

VCC = 5V 40 mV

VCC = 5V Vin = VCC /2

40 mV

3-73 In first l ine of

are not tested during manufacturing.”.

3-84 In

Typical Characteristics

, replace “3-3-xx” and “3-3-3-xx” by “3-xx”.

, change “These data are characterized, but not tested.” to “These figures

AT90S/LS2323 and AT90S/LS2343

The latest data sheet on the web is rev. 1004B-04/99. The data sheet in the printed data book is rev. 1004B-04/99.

Changes in the AT90S/LS2323 and AT90S/LS2343 Data Sheet:

Page: Change or Add:

4-6 In the

4-7 In the

4-19 In Figure 20, add a box containin g “+1” as a n input to the summation operator. 4-25 In the first paragraph of

4-29 Table 9: remove this note: “Not e: When ch anging the ISC01/ ISC00 bit s, INT0 must be disabl ed by cl earing its Int er-

Pin Descriptions AT90S/LS2323

“Port B is a 3-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull -up resistors are activated.

Port B also serves the functions of various special features. Port pins can provide internal pull-up resistors (selected for each bit). The port B pins are tri-stated when a reset

condition becomes acti ve.”

Pin Descriptions AT90S/LS2343

“Port B is a 5-bit bi-directional I/O port with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low, will source current if the pull -up resistors are activated.

Port B also serves the functions of various special features. Port pins can provide internal pull-up resistors (selected for each bit). The port B pins are tri-stated when a reset

condition becomes acti ve.”

Watchdog Reset

pulse of 1 XTAL cycle duration.” by “When the Watchdog times out, it will generate a short reset pulse of 1 CPU clock cycle duration.”

rupt Enable bit in the GIMSK registe r. Otherwise an interrupt can occur when the bits are changed. ”

replace the description for

, replace “When the Watchdog times out, it will generate a short reset

Port B (PB2..PB0)

Port B (PB4..PB0)

4-34 In the note for Table 11, add “To avoid unintenti onal MCU resets, the Watchdog Timer should be disabled or reset

before changing the Watchdog Timer Prescale Select.” In

EEPROM Read/Write Access

two clock cycles before the next instruction is executed.” by “When the EEPROM is written, the CPU is halted for two clock cycles before t he ne xt instruction is executed. When it is read, the CPU is halted for 4 clock cycles.”.

4-35 In the

EECR” to “4. Write a logica l one to the EEMWE bit i n EECR (to be able to wri te a logical one to the EEMWE bit, the EEWE bit must be written to zero in the same cycle).”

In the two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four clock cycles before the next instruction is executed.”

4-37 in the

Bit1 - EEWE: EEPROM Write Enable

Bit 0 - EERE: EEPROM Read Enable

Port B Input Pins Address - PINB

Data Book Updates and Changes

, replace the 6th line “When the EEPROM is read or written, the CPU is halted for

description, change “4. Write a logical one to the EEMWE bit in

description,

description, change the Initial Values of bits 0-4 from “Hi-Z” to “N/A”.

change

“When EERE has been set, the CPU i s halt ed f or

Data Book Updates and Changes

4-38 Replace the secti on name “MISO - Port B, Bit 1” by “MISO/INT0 - Port B, Bit 1” 4-40 In

High-Voltage Serial Programming

“Power-up sequence: Apply 4.5 - 5.5V betwee n V Then, if the RCEN Fuse is not programmed; Toggle XTAL1/PB3 at least 4 times with minimum 100ns pulse-width.

Set PB3 to “0”. Wait at least 100ns. or if the RCEN Fuse is programmed; Set PB3 to “0”. Wait at least 4µs. In both cases; Then apply 12V to RESET

any instructions.”

4-40 In

High-Voltage Serial Programming

4-42 In table 16, replace the entries

Read Fuse and Lock bits (AT90S/ LS2323)

Read Fuse and Lock bits (AT90S/ LS2343)

PB0 PB1 PB2

0_0000_0100_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0100_00 0_0100_1100_00

x_xxxx_xxxx_xx

by the entries (Note: Bit 7 in the 4’th and 5’th column for PB1 has been inverted compared to the origi nal data book)

, replace item 1. by

and wait at least 100 ns before changing PB0. Wait 8 µs before giving

, replace in item 5 “Set PB5 to “1”.” by “Set RESET

0_0000_0000_00 0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0110_1000_00

x_xxxx_xxxx_xx

and GND. Set RESET and PB0 to “0” and wait at least 100 ns.

to “0”.”

0_0000_0000_00 0_0110_1100_00

xx_xxFx_xx

1_2

0_0000_0000_00 0_0110_1100_00

xx_xxRx_xx

1_2

Reading Fuse/Lock bit is programmed.

, S, F =’ 0’ means the

1, 2

, S, R =’ 0’ means the

1, 2

Read Fuse and Lock bits (AT90S/ LS2323)

Read Fuse and Lock bits (AT90S/ LS2343)

PB0 PB1 PB2

0_0000_0100_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0100_00 0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00 0_0111_1100_00

xx_xxFx_xx

1_2

0_0000_0000_00 0_0111_1100_00

xx_xxRx_xx

1_2

Reading Fuse/Lock bit is programmed.

, S, F =’ 0’ means the

1, 2

, S, R =’ 0’ means the

1, 2

4-43 In figure 35, remove “CLOCK INPUT”, “XTAL1/PB3” and the arrow connecting them. 4-49 In first l ine of

Typical Characteristics

, change “These data are characterized, but not tested.” to “These figures

are not tested during manufacturing.”.

4-59 In Register Summary, replace all “4-page” by “page”. In addition, for TIMSK; replace ”page 4 -15” by “page 4-28”,

for TIFR; replace “page 4-16” by “page 4-28”, for MCUCR; replace “page 4-16” by “page 4-29”, for MCUSR; replace “page 4-14” by “page 4-26”.

4-60 In Instruction Set Summary under BRANCH INSTRUCTIONS, replace

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC SBIS P, b Skip if Bit in I/O Register is Set if (R(b)=1) PC

PC + 2 or 3 None 1 / 2

←

PC + 2 or 3 None 1 / 2

←

PC + 2 or 3 None 1 / 2

←

PC + 2 or 3 None 1 / 2

←

PC + 2 or 3 None 1 / 2

←

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC

PC + 2 or 3 None 1 / 2 / 3

←

PC + 2 or 3 None 1 / 2 / 3

←

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1 / 2 / 3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC SBIS P, b Skip if Bit in I/O Register is Set if (R(b)=1) PC

PC + 2 or 3 None 1 / 2 / 3

←

PC + 2 or 3 None 1 / 2 / 3

←

Data Book Updates and Changes

AT90S/LS2333 and AT90S/LS4433

The latest data sheet on the web is rev. 1042D-04/99. The data sheet in the printed dat a b ook is rev. 1042D-04/99.

Changes in the AT90S/LS2333 and AT90S/LS4433 Data Sheet:

Page: Change or Add:

5-6 In “

5-15 In 5-28 Table 7: remove this note: “Note: When changing the ISC11/ISC10 bi ts, INT1 must be disabled by clearing its Inter-

5-34 In “

5-37 Before

5-39 In the note for Table 16, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

5-41 In the

Pin Descriptions

nected to Vcc via a low-pass filter.” to “This is the supply voltage for Port A and the A/D Convert er. If the ADC is not used, this pin must be connected to Vcc. If the ADC is used, this pin should be connected to Vcc via a low-pass filter.”

Figure 20

rupt Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are changed. ” Table 8: remove this note: “Note: W hen changi ng the I SC01/ISC00 bi ts, I NT0 must be dis abled by cl ear ing it s Inter -

rupt Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are changed. ”

Timer/Counter Control Register 1B - TCCR1B

set to divide by 8 from “...C-1 | C, 0, 0, 0, 0, 0, 0, 0, 0 | ...” to “...C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ...”

use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because the up-counting and downcounting values are reached simultaneously. When the prescaler is in use (CS12..CS10 ≠ 001 or 000), the PWM output goes active when the counter reaches the TOP value, but the down-counting compare match is not i nterpreted to be reached before the next time the counter reaches the TOP-value, making a one- period PWM pulse.”

before changing the Watchdog Timer Prescale Select.”

EECR” to “4. Write a logical one to the EEMWE bit i n EECR (to be able to writ e a logical one to the EEMWE bit , the EEWE bit must be written to zero in the same cycle).”

, add a box containing “+1” as an input to the summation operator.

table 14

Bit1 - EEWE: EEPROM Write Enable

”,

, add paragraph “Note: If the compare register contains the TOP value and the prescaler is not in

, change “This is the supply vo ltage f or the A/D Conver ter. It should be externally con -

AVCC

”, bit3 -

description, change “4. Write a logical one to the EEMWE bit in

, change the count sequence when prescaler is

CTC1

5-47..50 In the 5-50 In last line, replace “UBRRH” by “UBRRHI”. 5-52 In “ 5-59 In “ 5-60 In 5-61 In the 5-66 In the

5-68 In the 5-80 In “

Analog Comparator Control and Status Register - ACSR ADC Noise Canceling Techniques

Figure 49

Port B Input Pins Address - PINB Port C Input Pins Address - PINC

Values “Q” to “0” (zero).

Port D Input Pins Address - PIND

Serial Downloading

description, replace “USR” by “UCSRA” and “UCR” by “UCSRB” everywhere.

UART

” item 3, replace “Figure 47” by “Fi gure 49”.

, replace the resistor by a 10 µH inductor. Change capacitor value from 10 nF to 100 nF.

description, change the Ini tial Values from “Hi-Z” to “N/A”. description, change the Initial Values from “Hi-Z” to “N/A”. Change Initial

description, change the Ini tial Values from “Hi-Z” to “N/A”.

”, replace Figure 66 by the figu re below.

”, the initia l va l ue o f

ACO

is “N/A”.

Figure 66. Serial Progr amming and Verify

GND

AT90S2333/4433

RESET

VCC

PB7 PB6 PB5

2.7 - 6.0V

SCK MISO MOSI

5-86 Replace the row below in

ACIO

Analog Comparator Input Offset Voltage

by:

ACIO

5-86 In “ 5-88 In first line of

Analog Comparator Input Offset Voltage

DC Characteristics

Typical Characteristics

”, footnote 4, r eplace “IOL” by “IOH” everywhere.

are not tested during manufacturing.”.

CLOCK INPUT

DC characteristics

XTAL1 GND

VCC = 5V 40 mV

VCC = 5V Vin = VCC /2

40 mV

, change “These data are characterized, but not tested.” to “These figures

Data Book Updates and Changes

AT90S4414/8515

The latest data sheet on the web is rev. 0841E-04/99. The data sheet in the printed dat a b ook is rev. 0841E-04/99.

Changes in the AT90S4414/8515 Data Sheet:

Page: Change or Add:

Data Book Updates and Changes

6-17 In 6-29 Table 6: remove this note: “Note: When changing the ISC11/ISC10 bi ts, INT1 must be disabled by clearing its Inter-

6-30 Table 7: remove this note: “Note: W hen changi ng the I SC01/ISC00 bi t s, INT0 must be dis able d by clear ing it s Inter -

6-39 Before

6-41 In the note for Table 15, add “To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset

6-42 In the

6-43 In the

Figure 19

rupt Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are changed. ”

before changing the Watchdog Timer Prescale Select.” In the

halted for two clock cycles before the next instruction is executed.” to “When the EEPROM is written, the CPU is halted for two clock cycles bef ore the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.”

EECR” to “4. Write a log ica l one to t he EEMWE bit in EECR (t o be able t o writ e a logic al one to t he EEMWE bit , the EEWE bit must be written to zero in the same cycle).”

two clock cycles before the next instruction is executed.” to “When EERE has been set, the CPU is halted for four clock cycles before the next instructi on is executed.”

, add a box containing “+1” as an input to the summation operator.

table 14

EEPROM Read/Write Access

Bit1 - EEWE: EEPROM Write Enable description, change

Bit 0 - EERE: EEPROM Read Enable

, add paragraph “Note: If the compare register contains the TOP value and the prescaler is not in

description,

change

“When the EEPROM is read or written, the CPU is

change

“When EERE has been set, the CPU i s halt ed fo r

“4. Write a logical one to the EEMWE bit in

6-54 In the

6-57 in the 6-59 in the 6-64 in the 6-66 in the 6-79 Replace

Analog Comparator Control and Status Register

“N/A”.

Port A Input Pins Address - PINA Port B Input Pins Address - PINB Port C Input Pins Address - PINC Port D Input Pins Address - PIND

figure 64

description, change the ini tial value of ACO from “0” to

description, change the Initial Values from “Hi-Z” to “N/A”. description, change the Initial Values from “Hi-Z” to “N/A”. description, change the Initial Values from “Hi-Z” to “N/A”. description, change the Initial Values from “Hi-Z” to “N/A”.

by the one below:

Figure

64 Serial Programming and Verify

6-84: Replace the row below in

ACIO

Analog Comparator Input Offset Voltage

by:

ACIO

6-88 In first line of

Analog Comparator Input Offset Voltage

Typical Characteristics

are not tested during manufacturing.”.

GND

CLOCK INPUT

DC characteristics

AT90S4414/8515

RESET

XTAL1 GND

VCC

PB7 PB6 PB5

2.7 - 6.0

SCK MISO MOSI

VCC = 5V 40 mV

VCC = 5V Vin = VCC /2

40 mV

, change “These data are characterized, but not tested.” to “These figures

6-98 In

, replace all “6-6-xx” by “6-xx”.

Data Book Updates and Changes

AT90S/LS4434 and AT90S/LS8535

The latest data sheet on the web is rev. 1041E-04/99. The data sheet in the printed dat a b ook is rev. 1041E-04/99.

Changes in the AT90S/LS4434 and AT90S/LS8535 Data Sheet:

Page: Change or Add:

7-6 In “

7-15 In 7-27 In “

7-29 Table 9: remove this note: “Note: When changing the ISC11/ISC10 bi ts, INT1 must be disabled by clearing its Inter-

7-30 In the

7-30 At the end of the

7-36 In “

Pin Descriptions

Figure 19

Timer/Counter Inter rupt Flag Regi ster - TIFR

to “Bit 6 - TOV2: T imer /Counter2 Overflow Flag”.

rupt Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are changed. ” Table 10: remove this note: “Note: When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its

Interrupt Enable bit in the GIMSK register. Otherwise an interrupt can occur when the bits are changed.”

to “Note th at when a level triggered interrupt is use d for wake-up from power down, the low level must be held for a time longer than the reset delay time- out period t

chronously, Power Down Mode is recom mended instead of Power Save Mode because the contents of the registers in the asynchronous timer should be considered undefined after wake up in Power Save Mode, even if AS2 is

0.”

Timer/Counter Control Register 1B - TCCR1B

set to divide by 8 from “...C-1 | C, 0, 0, 0, 0, 0, 0, 0, 0 | ...” to “...C-1 | C, 0, 0, 0, 0, 0, 0, 0 | ...”

, add a box containing “+1” as an input to the summation operator.

Power Down Mode

”,

Power Save Mode

, change “This is the supply vo ltage f or the A/D Conver ter. It should be externally con -

AVCC

section, replace paragraph 2 (“Note that if a level triggered interrupt... ...on page 7-98.”)

”, change heading “Bit 6 - T OV2: Timer/Counter0 Overflow Flag”

.”

TOUT

section, add the paragraph “If the asynchronous timer is NOT clocked asyn-

”, bit3 -

, change the count sequence when prescaler is

CTC1

7-39 Before

7-45 Replace last paragraph on page:

“When asynchronous operation is selected, the 32 kHz oscillator for Timer/Counter2 is always running, except in power down mode. After a power up reset or wake-up from power down, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. Therefore, the content of all Timer/Counter2 regist ers must be considered lost after a wake-up from power down, due to the unstable clock signal. The user is advised to wait for at least one second before usi ng Timer/Counter2 after power-up or wake-up from power down.”

by “When the asynchronous operation is selected, the 32kHZ oscillator for Timer/Counter2 is always running, except

in power down mode. After a power up reset or wake-up from power down, the user should be aware of the fact that this osci llator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from power down. The contents of all Timer /Counter2 reg-

table 16

, add paragraph “Note: If the compare register contains the TOP value and the prescaler is not in

+ 29 hidden pages