ATMEL ATxmega64A1 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• High-performance, Low-power 8/16-bit AVR XMEGA Microcontroller
• Non-Volatile Program and Data Memories
– 64K - 384K Bytes of In-System Self-Programmable Flash
– 4K - 8K Bytes Boot Section with Independent Lock Bits
– 2K - 4K Bytes EEPROM
– 4K - 32K Bytes Internal SRAM
External Bus Interface for up to 16M bytes SRAM
External Bus Interface for up to 128M bit SDRAM
• Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Eight 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Four Timer/Counters with 2 Output Compare or Input Capture channels
High-Resolution Extension on all Timer/Counters
Advanced Waveform Extension on two Timer/Counters
– Eight USARTs
IrDA modulation/demodulation for one USART
– Four Two-Wire Interfaces with dual address match (I
– Four SPI (Serial Peripheral Interface) peripherals
– AES and DES Crypto Engine
– 16-bit Real Time Counter with separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– Two Two-channel, 12-bit, 1 Msps Digital to Analog Converters
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
• Special Microcontroller Features
– Power -on Reset and Pr ogrammab le Brown-out Detection
– Internal and External Clock Options with PLL and Prescaler
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, P ower-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for programming, test and debugging
PDI (Program and Debug Interface) for programming and debugging
• I/O and Pac kages
– 78 Programmable I/O Lines
– 100 - lead TQFP
– 100 - ball CBGA
• Operating Voltage
– 1.6 – 3.6V
• Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
2
C and SMBus compatible)
8/16-bit
XMEGA A1
Microcontroller
ATxmega384A1
ATxmega256A1
ATxmega192A1
ATxmega128A1
ATxmega64A1
Preliminary
Typical Applications
• Industrial control • Climate control • Hand-held battery applications
• Factory automation • ZigBee • Power tools
• Building control • Motor control • HVAC
• Board control • Networking • Metering
• White Goods • Optical • Medical Applicat ion s
8067C–AVR–05/08
‘
1. Ordering Information
XMEGA A1
Ordering Code Flash (B) E2 (B) SRAM (B) Speed (MHz) Power Supply Package
ATxmega384A1-AU 384K + 8K 4K 32K 32 1.6 - 3.6V
ATxmega256A1-AU 256K + 8K 4K 16K 32 1.6 - 3.6V
ATxmega192A1-AU 192K + 8K 2K 16K 32 1.6 - 3.6V
ATxmega128A1-AU 128K + 8K 2K 8K 32 1.6 - 3.6V
ATxmega64A1-AU 64K + 4K 2K 4K 32 1.6 - 3.6V
ATxmega384A1-AU 384K + 8K 4K 32K 32 1.6 - 3.6V
ATxmega256A1-CU 256K + 8K 4K 16K 32 1.6 - 3.6V
ATxmega192A1-CU 192K + 8K 2K 16K 32 1.6 - 3.6V
ATxmega128A1-CU 128K + 8K 2K 8K 32 1.6 - 3.6V
ATxmega64A1-CU 64K + 4K 2K 4K 32 1.6 - 3.6V
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see “Packaging information” on page 60.
Packa ge Type
100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100C1 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.88 mm, Chip Ball Grid Array (CBGA)
2. Pinout/Block Diagram
100A
100C1
(1)(2)(3)
Temp
-40° - 85°C
Figure 2-1. Block diagr am and T QF P -p inou t.
INDEX CORNER
PA6
PA7
GND
AVCC
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD0
PA5
PA4
9998979695949392919089888786858483828180797877
100
1
2
3
4
5
ADC A
6
DAC A
7
A
8
Port
AC A0
9
10
AC A1
11
12
ADC B
13
DAC B
14
B
15
Port
AC B0
16
17
AC B1
18
19
20
21
22
23
24
25
26272829303132333435363738394041424344454647484950
PD1
PD2
PA3
PD3
PA2
PD4
PA1
PD5
PA0
T/C0:1
Port C
PD6
AVCC
TWI
USART0:1
PD7
GND
PR1
Port R
OSC/CLK
Contro l
Power
Contro l
Reset
Contro l
Watchdog
SPI
VCC
GND
PR0
RESET/PDI
PDI
PQ3
PQ2
Q
Port
DATA BU
BOD POR
TEMP
CPU
DMA
Interrupt Controlle r
Event System ctrl
DATA BU
EVENT ROUTING NETWORK
TWI
SPI
T/C0:1
PE0
T/C0:1
USART0/1
PE1
PE2
PE3
PE4
PQ1
S
VREF
RTC
S
USART0:1
PE5
PQ0
FLASH
RAM
E2PROM
TWI
SPI
PE6
GND
PE7
VCC
OCD
T/C0:1
Port FPort EPort D
GND
PK7
VCC
PK6
PK5
PK4
PK3
PK2
PK1
76
75
PK0
74
VCC
73
GND
72
PJ7
71
PJ6
70
PJ5
69
PJ4
68
PJ3
67
PJ2
66
Port K
nterface
Port J
External Bus I
Port H
TWI
SPI
USART0:1
PF0
PF1
PF2
PF3
PF4
PF5
PJ1
65
PJ0
64
VCC
63
GND
62
PH7
61
PH6
60
PH5
59
PH4
58
PH3
57
PH2
56
PH1
55
PH0
54
VCC
53
GND
52
PF7
51
PF6
Note: For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 48.
8067C–AVR–05/08
2
Figure 2-2. CBGA-pinout
A
B
C
D
E
F
G
H
J
K
A
B
C
D
E
F
G
H
J
K
Top view
Bottom view
XMEGA A1
1 2345678910
10987654321
Table 2-1. CBGA-pinout
1 2 3 4 56 78910
A PK0 VCC GND PJ3 GND VCC PH1 GND VCC PF7
B PK3 PK2 PK1 PJ4 PH7 PH4 PH2 PH0 PF6 PF5
C VCC PK5 PK4 PJ5 PJ0 PH5 PH3 PF2 PF3 VCC
D GND PK6 PK7 PJ6 PJ1 PH6 PF0 PF1 PF4 GND
TOSC1/
E
F
G GND PA1 PA4 PB3 PB4 PC1 PC6 PD7 PD6 GND
H AVCC PA2 PA5 PB2 PB5 PC0 PC5 PD5 PD4 PD3
J PA0 PA3 PB0 PB1 PB6 PC3 PC4 PC7 PD2 PD1
K PA6 PA7 GND AVCC PB7 VCC GND VCC GND PD0
PQ0
XTAL1/
PR1
TOSC2/
PQ1
XTAL2/
PR0
.
PQ2 PJ7 PJ2 PE7 PE6 PE5 PE4 PE3
RESET/
PDI_CLK
PDI_DATA PQ3 PC2 PE2 PE1 PE0 VCC
8067C–AVR–05/08
3
3. Overview
XMEGA A1
The XMEGA A1 is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR
instructions in a single clock cycle, the XMEGA A1 achieves throughputs approaching 1 Million
Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA A1 devices provides the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 78 general purpose
I/O lines, 16-bit Real Time Counter (RTC), eight flexible 16-bit Timer/Counters with compare
modes and PWM, eight USARTs, four Two Wire Serial Interfaces (TWIs), four Serial Peripheral
Interfaces (SPIs), AES and DES crypto engine, two 8-channel, 12-bit ADCs with optional differential input with programmable gain, two 2-channel, 12-bit DACs, four analog comparators with
window mode, programmable Watchdog Timer with seperate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
®
enhanced RISC architecture. By executing powerful
The XMEGA A1 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asyn chrono us Real Time Counte r continue s to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock to each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-den sity nonvolat ile memory technolog y. The program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download th e application program to the Fla sh
memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flas h, th e Atmel XMEGA A1 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
The XMEGA A1 devices is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, programmers, and
evaluation kits.
8067C–AVR–05/08
4
3.1 Block Diagram
Figure 3-1. XMEGA A1 Block Diagram
PR[0..1]
XTAL1
XMEGA A1
PQ[0..3]
TOSC1
PA[0..7]
PB[0..7]/
JTAG
DACA
PORT A (8)
ACA
ADCA
AREFA
Internal
Reference
AREFB
ADCB
ACB
PORT B (8)
DACB
XTAL2
EVENT ROUTING NETWORK
Event System
Controller
DMA
Controller
BUS
Controller
DES
AES
TOSC2
Oscillator
Circuits/
Clock
PORT R (2)
PORT Q (4)
DATA BUS
SRAM
CPU
NVM Controller
Flash EEPROM
Generation
Oscillator
Control
Controller
Prog/Debug
Controller
Interrupt
Controller
Sleep
OCD
Real Time
Counter
Watchdog
Oscillator
Watchdog
Timer
Power
Supervision
POR/BOD &
RESET
PDI
JTAG
EBI
PORT B
PORT K (8)
PORT J (8)
PORT H (8)
VCC
GND
RESET/
PDI_CLK
PDI_DATA
PK[0..7]
PJ[0..7]
PH[0..7]
8067C–AVR–05/08
IRCOM
TCC0:1
USARTC0:1
PORT C (8)
PC[0..7]
SPIC
DATA BUS
EVENT ROUTING NETWORK
TWIC
PORT D (8)
SPID
TCD0:1
PD[0..7] PE[0..7] PF[0..7]
TWID
USARTD0:1
PORT E (8) PORT F (8)
TCE0:1
SPIE
USARTE0:1
TWIE
SPIF
TCF0:1
TWIF
USARTF0:1
5
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1 Recommended reading
• XMEGA A Manual
• XMEGA A Application Notes
This device data sheet only contains part specific inf ormation and a short de scription of each
peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth.
The XMEGA A application notes contain example code and show applied use of the modules
and peripherals.
The XMEGA A Manual and Application Notes are available from http:// www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
XMEGA A1
8067C–AVR–05/08
6
6. AVR CPU
6.1 Features
6.2 Overview
XMEGA A1
• 8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in SRAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16M Bytes of program and data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Support for 8-, 16- and 32-bit Arithmetic
• Configuration Change Protection of system critical features
The XMEGA A1 uses the 8/16-bit AVR CPU. The main function of the CPU is program exec ution. The CPU must therefore be able to access memories, per form calculations and control
peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 7 shows
the CPU block diagram.
Figure 6-1. CPU block diagram
Program
Counter
OCD
STATUS/
CONTROL
Peripheral
Module 1
Peripheral
Module 2
DATA BUS
Flash
Program
Memory
Instruction
Register
Instruction
Decode
ALU
DATA BUS
32 x 8 General
Purpose
Registers
Multiplier/
DES
EEPROM PMICSRAM
8067C–AVR–05/08
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This
7
concept enables instructions to be executed in every clock cycle. The pr ogram memory is InSystem Self-Programmable Flash memory.
6.3 Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU cycle, the operation is performed on two Register File operands, and the result is stored
back in the Register File.
Six of the 32 registers can be used as three 16-bit address register pointers for data space
addressing - enabling efficient address calculations. One of these address pointers can also be
used as an address pointer for look up tables in Flash progra m memory.
6.4 ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
XMEGA A1
6.5 Program Flow
The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient
implementation of 32-bit aritmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequent ly the Stack size is o nly limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessib le in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five differe n t addr es s ing mode s su pp or te d in th e A V R CPU.
8067C–AVR–05/08
8
7. Memories
7.1 Features
7.2 Overview
XMEGA A1
• Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section fo r application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte or page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all peripherals and modules
16-bit accessible General Purpose Register for global variables or flags
– External Memory support
– Bus arbitration
Safe and deterministic handling of CPU and DMA Controller priority
– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access
Simultaneous bus access for CPU and DMA Controller
• Two Signature Row Flash Memories
– Factory programmed data
Oscillator calibration bytes
Serial number
Device ID for each device type
– User programmable memory
One flash page in size
Data is kept after normal chip erase
The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A1 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configurations are shown in “Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software.
7.3 In-System Programmable Flash Program Memory
The XMEGA A1 devices contains On-chip In-System Programmable Flash memory for program
storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each
Flash address location is 16 bits.
8067C–AVR–05/08
9
XMEGA A1
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictio ns on write or rea d/write ope rations. The Sto re Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash
memory.
A third section inside the Application section is referred to as the Application Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software.
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
0
2EFFF / 1EFFF / 16FFF / EFFF / 77FF
2F000 / 1F000 / 17000 / F000 / 7800
2FFFF / 1FFFF / 17FFF / FFFF / 7FFF
30000 / 20000 / 18000 / 10000 / 8000
30FFF / 20FFF / 18FFF / 10FFF / 87FF
Application Section
(384K/256K/192K/128K/64K)
...
Application Table Section
(8K/8K/8K/8K/4K)
Boot Section
(8K/8K/8K/8K/4K)
The Application Table Section and Boot Section can also be used for general application
software.
7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 10 . To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address ATxmega192A1 Byte Address ATxmega128A1 Byte Address ATxmega64A1
1000
17FF 17FF 17FF
2000
5FFF 3FFF 2FFF
6000
FFFFFF FFFFFF FFFFFF
8067C–AVR–05/08
0
FFF FFF FFF
I/O Registers
(4KB)
EEPROM
(2K)
RESERVED RESERVED RESERVED
Internal SRAM
(16K)
External Memory
(0 to 16 MB)
1000
2000
4000
0
I/O Registers
Internal SRAM
Externa l Memory
(0 to 16 MB)
(4KB)
EEPROM
(2K)
(8K)
1000
2000
3000
0
I/O Registers
EEPROM
Internal SRAM
External Memory
(0 to 16 MB)
(4KB)
(2K)
(4K)
10
XMEGA A1
Byte Address ATxmega384A1 Byte Address ATxmega256A1
0
I/O Registers
FFF FFF
(4KB)
0
I/O Registers
(4KB)
7.4.1 I/O Memory
1000
EEPROM
(4K)
1FFF 1FFF
2000
9FFF 5FFF
10000
FFFFFF FFFFFF
Internal SRAM
(32K)
External Memory
(0 to 16 MB)
1000
2000
6000
EEPROM
(4K)
Internal SRAM
(16K)
External Memory
(0 to 16 MB)
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpo se registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using th e SBIS and SBIC instructions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Periph-
eral Module Address Map” on page 54.
7.4.2 SRAM Data Memory
The XMEGA A1 devices has internal SRAM memory for data storage.
7.4.3 EEPROM Data Memory
The XMEGA A1 devices has internal EEPROM mem ory for non-volatile data storage. It is
addressable either in a separate data space or it can be m emory mapped into the normal d ata
memory space. The EEPROM memory supports both byte and page access.
8067C–AVR–05/08
11
7.4.4 EBI - External Bus Interface
Supports SRAM up to
•
– 512K Bytes using 2-port EBI
– 16M Bytes using 3-port EBI
• Supports SDRAM up to
– 128M bit using 3-port EBI
• Four software configurable Chip Selects
• Software configurable Wait State insertion
• Clocked from the Peripheral 2x Clock at up to two times the CPU clock speed
The External Bus Interface (EBI) is the interface for connecting external peripheral and memory
to the data memory space. The XMEGA A1 has 3 ports that can be used fo r the EBI. It can in terface external SRAM, SDRAM, and/or peripherals such as LCD displays and other memory
mapped devices..
The address space, and the number of pins used, for the external memory is selectable from
256 bytes (8-bit) and up to 16M bytes (24-bit). Various multiplexing modes for address and data
lines can be selected for optimal use of pins when more or less pins is ava ilab l e for the EB I.
Each of the four chip selects has seperate configuration, and can be configured for SRAM ,
SRAM Low Pin Count (LPC) or SDRAM. The data memory address space associated for each
chip select is decided by a configurable base address and address size for each chip celect.
XMEGA A1
For SDRAM both 4-bit SDRAM is supported, and SDRAM configurations such as CAS Latency
and Refresh rate is configurable in software.
The EBI is clocked from the Peripheral 2x Clock, running up to two times faster than the CPU
and supporting speeds of up to 64 MHz.
8067C–AVR–05/08
12
7.5 Signature Rows
The Non Volatile Memory has two sections that are not affected by chip erase. Each section is
one flash page in size, and is used for parameter storage.
One section is for factory programmed device ID, serial number, and calibration data for functions such as the oscillators. The device ID for the available XMEGA A1 devices is shown in
Table 7-1 on page 13. Some of the calibration values will be automatically loaded to the corre-
sponding module or peripheral unit during reset. Th is section can not be erased , and it can be
read from application software and external programming.
Table 7-1. Device ID bytes for XMEGA A1 devices.
XMEGA A1
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega64A1 4E 96 1E
ATxmega128A1 4C 97 1E
ATxmega192A1 4E 97 1E
ATxmega256A1 46 98 1E
ATxmega384A1 TBD TBD TBD
The other section is fully accessible (read and write) from application software and external
interface programming. This is meant to be used to store data that should not be erased during
chip erase or on-chip debug sessions. This section can only be erased using a dedicated erase
command.
8067C–AVR–05/08
13
XMEGA A1
7.6 Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Devices Flash Page Size FWORD FPAGE Application Boot
Size (Bytes) (words) Size No of Pages Size No of Pages
ATxmega64A1 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16
ATxmega128A1 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16
ATxmega192A1 192K + 8K 256 Z[8:1] Z[18:9] 192K 384 8K 16
ATxmega256A1 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16
ATxmega384A1 384K + 8K 256 Z[8:1] Z[19:9] 384K 768 8K 16
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A1 devices.
EEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n]) is used for addressing. The most significant bits in the address ( E2PAGE)
gives the page number and the least significant address bits (E2BYTE) gives the byte in the
page.
Table 7-3. Number of Bytes and Pages in the EEPROM.
Devices EEPROM Page Size E2BYTE E2PAGE No of Pages
Size (Bytes) (Bytes)
ATxmega64A1 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A1 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192A1 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256A1 4K 32 ADDR[4:0] ADDR[11:5] 128
ATxmega384A1 4K 32 ADDR[4:0] ADDR[11:5] 128
8067C–AVR–05/08
14
8. DMAC - Direct Memory Access Controller
8.1 Features
• Allows High-speed data transfer
– From memory to peripheral
– From memory to memory
– From peripheral to memory
– From peripheral to peripheral
• 4 Channels
• From 1 byte and up to 16M bytes transfers in a single transaction
• Multiple addressing modes for source and destination address
–Increment
– Decrement
– Static
• 1, 2, 4, or 8 byte Burst Transfers
• Programmable priority between channels
8.2 Overview
The XMEGA A1 has a Direct Memory Access (DMA) Controller to move data between memori es
and peripherals in the data space. The DMA controller uses the same data bus as the CPU to
transfer data.
XMEGA A1
It has 4 channels that can be configured independently. Each DMA channel can perform data
transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to
repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be
configured to access the source and destination memory a ddress with i ncrementing, d ecrementing or static addressing. The addressing is independent for source and destination address.
When the transaction is complete the original source and destination address can automatically
be reloaded to be ready for the next transaction.
The DMAC can access all the peripherals through thei r I/ O m emory r egist ers, a nd th e DMA m ay
be used for automatic transfer of data to/from communication modules, as well as automatic
data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or
from port pins. A wide range of transfer triggers is available from the peripherals, Event System
and software. Each DMA channel has different transfer triggers.
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa.
The DMA controller can read from memory mapped EEPROM, but it cannot write to the
EEPROM or access the Flash.
8067C–AVR–05/08
15
9. Event System
9.1 Features
9.2 Overview
• Inter-peripheral communication and signalling with minimum latency
• CPU and DMA independent operation
• 8 Event Channels allows for up to 8 signals to be routed at the same time
• Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADCx)
– Analog Comparators (ACx)
– Ports (PORTx)
– System Clock (Clk
– Software (CPU)
SYS
)
• Events can be used by
– Timer/Counters (TCxn)
– Analog to Digital Converters (ADCx)
– Digital to Analog Converters (DACx)
– Ports (PORTx)
– DMA Controller (DMAC)
– IR Communication Module (IRCOM)
• The same event can be used by multiple peripherals for synchronized timing
• Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
• Functions in Active and Idle mode
XMEGA A1
8067C–AVR–05/08
The Event System is a set of features for inter-peripheral communication. It enab les the possibility for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 9-1 on page 17 shows a basic
block diagram of the Event System with the Event Routin g Networ k an d the pe ripher als t o wh ich
it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
16
Figure 9-1. Event system block diagram.
XMEGA A1
PORTx
ADCx
ClkSYS
CPU
RTC
Event Routing
Network
DACx
ACx
DMACIRCOM
T/Cxn
The Event Routing Network can directly connect togethe r ADCs, DACs, Analog Comparators
(ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU).
All events from all peripherals are always ro ut ed into th e Eve nt Rou tin g Netw or k. T his con sist of
eight multiplexers where each can be configured in software to select which event to be routed
into that event channel. All eight event channels are connected to the peripherals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
8067C–AVR–05/08
17
10. System Clock and Clock options
10.1 Features
• Fast start-up time
• Safe run-time clock switching
• Internal Oscillators:
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32 kHz calibrated RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator
• External clock options
– 0.4 - 16 MHz Crystal Oscillator
– 32 kHz Crystal Oscillator
– External clock
• PLL with internal and external clock options with 2 to 31x multiplication
• Clock Prescalers with 2 to 2048x division
• Fast peripheral clock running at 2 and 4 times the CPU clock speed
• Automatic Run-Time Calibration of internal oscillators
• Crystal Oscillator failure detection
10.2 Overview
XMEGA A1
XMEGA A1 has an advanced clock system, supporting a lar ge numbe r of clo ck sources. It in corporates both integrated oscillators, external crystal oscillators and resonators. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a
wide range of clock frequencies from the clock source input.
It is possible to switch between clock sources from software during run-time. After reset the
device will always start up running from the 2 Mhz internal oscillator.
A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 19 shows the principal clock system in XMEGA A1.
8067C–AVR–05/08
18
Figure 10-1. Clock system overview
32 kHz ULP
Internal Oscillator
32.768 kHz
Calibrated Internal
Oscillator
clk
clk
XMEGA A1
ULP
WDT/BOD
RTC
RTC
2 MHz
Run-Time Calibrated
Internal Oscillator
32 MHz
Run-time Calibrated
Internal Oscillator
32.768 KHz
Crystal Oscillator
0.4 - 16 MHz
Crystal Oscillator
External
Clock Input
CLOCK CONTROL
UNIT
with PLL and
Prescaler
clk
clk
PERIPHERALS
PER
INTERRUPT
NVM MEMORY
CPU
ADC
DAC
PORTS
...
DMA
EVSYS
RAM
CPU
FLASH
EEPROM
Each clock source is briefly described in the following sub-sections.
10.3 Clock Options
10.3.1 32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumptio n clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
10.3.2 32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during protection to provide a default frequency which is close to its nominal
frequency.
8067C–AVR–05/08
19
10.3.3 32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be
used as system clock source or as asynchronous clock source for the Real Time Counter.
10.3.4 0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400 kHz to 16 MHz.
10.3.5 2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during protection to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a
source for calibrating the frequency run-time to compensate for temperature and voltage drift
hereby optimizing the accuracy of the oscillator.
10.3.6 32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during protection to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a
source for calibrating the frequency run-time to compensate for temperature and voltage drift
hereby optimizing the accuracy of the oscillator.
XMEGA A1
10.3.7 External Clock input
The external clock input gives the possibility to connect a clock from an external source.
10.3.8 PLL with Multiplication factor 2 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 2 to 31. In combination with the prescalers, this gives a wide range of o utput frequencies f rom all clock sources.
8067C–AVR–05/08
20
11. Power Management and Sleep Modes
11.1 Features
• 5 sleep modes
–Idle
– Power-down
–Power-save
–Standby
– Extended standby
• Power Reduction registers to disable clocks to unused peripherals
11.2 Overview
The XMEGA A1 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the
CPU is executing application code. The application code decides when and what sleep mode to
enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode.
XMEGA A1
11.3 Sleep Modes
11.3.1 Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from
all enabled interrupts will wake the device.
11.3.2 Power-down Mode
In Power-down mode all system clock sources, and the asynchronous Real Time Counter ( RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts, e.g pin change.
11.3.3 Power-save Mode
Power-save mode is identical to Power-down, with one exception: If the RTC is enable d, it will
keep running during sleep and the device can also wake up from RTC interrupts.
11.3.4 Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
11.3.5 Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonato rs are used.
8067C–AVR–05/08
21
12. System Control and Reset
12.1 Features
• Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscillator
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– JTAG Reset
– PDI reset
– Software reset
• Asynchronous reset
– No running clock in the device is required for reset
• Reset status register
12.2 Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not re se t. Ap plication execution starts from the Reset Vector. The instru ction placed at the Reset Vector should
be an Absolute Jump (JMP) instruction to the reset handling routine. By defau lt t he Reset Vector
address is the lowest Flash program memory address , ‘0’, but it is possible to move the Reset
Vector to the first address in the Boot Section.
XMEGA A1
The I/O ports of the AVR are immediately tri-stated when a reset source goes active.
The reset functionality is asynchronous, so no running clock is require d to reset the device.
After the device is reset, the reset source can be determined by the application by reading the
Reset Status Register.
12.3 Reset Sources
12.3.1 Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
12.3.2 External Reset
The MCU is reset when a low level is present on the RESET pin.
12.3.3 Watchdog Reset
The MCU is reset when the Watchdog Timer period exp ires and the Wat chdog Reset is enable d.
The Watchdog Timer runs from a dedicated oscillator independen t of the System Clock. For
more details see “WDT - Watchdog Timer” on page 23.
12.3.4 Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
8067C–AVR–05/08
22
12.3.5 JTAG reset
The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains
of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details.
12.3.6 PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
12.3.7 Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
12.4 WDT - Watchdog Timer
12.4.1 Features
11 selectable timeout periods, from 8 ms to 8s.
•
• Two operation modes
– Standard mode
– Window mode
• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
• Configuration lock to prevent unwanted changes
12.4.2 Overview
XMEGA A1
The XMEGA A1 has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable time-out period, the microcontroller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevent microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Application software can set the minimum and maximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety, the WDT also has an Always-on mode. This mode is enabled by programming a fuse. In Always-on mode, application software can not disable t he WDT.
8067C–AVR–05/08
23
13. PMIC - Programmable Multi-level Interrupt Controller
13.1 Features
• Separate interrupt vector for each interrupt
• Short, predictable interrupt response time
• Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
• Interrupt vectors can be moved to the start of the Boot Section
13.2 Overview
XMEGA A1 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both lowand medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
XMEGA A1
13.3 Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address a nd the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA A1 devices are shown
in Table 13-1. Offset addresses for each interrupt available in the peripheral are described for
each peripheral in the XMEGA A manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word address.
Table 13-1. Reset and Interrupt Vectors
Program Address
(Base Address) Source Interrupt Description
0x000 RESET
0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI)
0x004 PORTC_INT_base Port C Interrupt base
0x008 PORTR_INT_base Port R Interrupt base
0x00C DMA_INT_base DMA Controller Interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base
0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base
0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base
0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base
0x030 SPIC_INT_vect SPI on port C Interrupt vector
0x032 USARTC0_INT_base USART 0 on port C Interrupt base
0x038 USARTC1_INT_base USART 1 on port C Interrupt base
0x03E AES_INT_vect AES Interrupt vector
8067C–AVR–05/08
24
Loading...