ATMEL ATxmega256A3 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• High-performance, Low-power AVR 8/16-bit XMEGA Microcontroller
• Non-volatile Program and Data Memories
– 64K - 256K Bytes of In-System Self-Programmable Flash
– 4K - 8K Boot Code Section with Independent Lock Bits
– 2K - 4K Bytes EEPROM
– 4K - 16K Bytes Internal SRAM
External Bus Interface for up to 16M bytes SRAM
External Bus Interface for up to 128M Bytes SDRAM
• Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Seven 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Three Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Seven USARTs
IrDA Extension on 1 USART
– AES and DES Crypto Engine
– Two Two-wire Interfaces with dual address match(I
– Three SPI (Serial Peripheral Interfaces)
– 16-bit Real Time Counter with Separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– One Two-channel, 12-bit, 1 Msps Digital to Analog Converter
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming
PDI (Program and Debug Interface) for programming, test and debugging
• I/O and Packages
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad MLF
• Operating Voltage
– 1.6 – 3.6V
• Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
2
C and SMBus compatible)
8/16-bit
XMEGA A3
Microcontroller
ATxmega256A3
ATxmega192A3
ATxmega128A3
ATxmega64A3
Preliminary
Typical Applications
• Industrial control • Climate control • Hand-held battery applications
• Factory automation • ZigBee • Power tools
• Building control • Motor control • HVAC
• Board control • Networking • Metering
• White Goods • Optical • Medical Applications
8068C–AVR–06/08
1. Ordering Information
XMEGA A3
Ordering Code Flash (B) E2 (B) SRAM (B) Speed (MHz) Power Supply Package
ATxmega256A3-AU 256K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega192A3-AU 192K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega128A3-AU 128K + 8K 2K 8K 32 1.8 - 3.6V
ATxmega64A3-AU 64K + 4K 2K 4K 32 1.8 - 3.6V
ATxmega256A3-MU 256K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega192A3-MU 192K + 8K 4K 16K 32 1.8 - 3.6V
ATxmega128A3-MU 128K + 8K 2K 8K 32 1.8 - 3.6V
ATxmega64A3-MU 64K + 4K 2K 4K 32 1.8 - 3.6V
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see ”Packaging information” on page 63.
2. Pinout/Block Diagram
Package Type
64A
64M1
Figure 2-1. Block diagram and TQFP-pinout.
64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
64A
64M1
(1)(2)(3)
Tem p
-40° - 85°C
INDEX CORNER
PA 3
PA 4
PA 5
PA 6
PA 7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
PR1
PR0
RESET/PDI_CLK
PDI_DATA
PF7
PA 2
PA 1
PA 0
AVCC
GND
PF6
646362616059585756555453525150
1
2
3
4
5
6
7
8
9
10
11
12
13
ADC A
A
t
AC A0
Por
AC A1
ADC B
DAC B
B
Por t
AC B0
AC B1
Port R
OSC/CLK
Control
Power
Control
Reset
Control
Watchdog
EVENT ROUTING NETWORK
DATA BU S
VREF
BOD POR
TEMP
RTC
CPU
DMA
Interrupt Controller
Event System ctrl
DATA BU S
14
15
16
T/C0:1
USART0:1
SPI
TWI
USART0:1
T/C0:1
T/C0:1
Port C Port D Port E Port F
USART0:1
SPI
171819202122232425262728293031
PD0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD1
VCC
FLASH
RAM
E2PROM
SPI
TWI
PD2
GND
OCD
PD3
T/C0
PF5
PD4
PF4
USART0
PD5
PF3
49
32
PD6
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PF2
PF1
PF0
VCC
GND
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VCC
GND
PD7
Note: 1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 48.
8068C–AVR–06/08
2
3. Overview
XMEGA A3
The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR
instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million
Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.
The XMEGA A3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose
I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare
modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional
differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this
can also be used for On-chip Debug and programming.
®
enhanced RISC architecture. By executing powerful
The XMEGA A3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and
all peripherals to continue functioning. The Power-down mode saves the SRAM and register
contents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock for each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader
running in the device can use any interface to download the application program to the Flash
memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an
8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many
embedded applications.
The XMEGA A3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
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3
3.1 Block Diagram
Figure 3-1. XMEGA A3 Block Diagram
XMEGA A3
PR[0..1]
XTAL1
XTAL2
PA[0..7]
PB[0..7]/
JTAG
PORT A (8)
ACA
ADCA
AREFA
Internal
Reference
AREFB
ADCB
ACB
PORT B (8)
DACB
Event System
Controller
DMA
Controller
BUS
Controller
DES
AES
Oscillator
Circuits/
Clock
PORT R (2)
DATA BUS
SRAM
CPU
NVM Controller
Flash EEPROM
Generation
Prog/Debug
Oscillator
Control
Sleep
Controller
Controller
OCD
Interrupt
Controller
Real Time
Counter
Watchdog
Oscillator
Watchdog
Timer
Power
Supervision
POR/BOD &
RESET
PDI
JTAG
USARTF0
TCF0
PORT B
VCC
GND
RESET/
PDI_CLK
PDI_DATA
PF[0..7]
PORT F (8)
8068C–AVR–06/08
IRCOM
TCC0:1
USARTC0:1
PORT C (8)
PC[0..7]
DATA BUS
EVENT ROUTING NETWORK
SPIC
TWIC
PORT D (8)
PD[0..7]
SPID
TCD0:1
USARTD0:1
PORT E (8)
TCE0:1
PE[0..6]
SPIE
TWIE
USARTE0:1
To Clock
Generator
TOSC1
TOSC2
4
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1 Recommended reading
• XMEGA A Manual
• XMEGA A Application Notes
This device data sheet only contains part specific information and a short description of each
peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth.
The XMEGA A application notes contain example code and show applied use of the modules
and peripherals.
The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
XMEGA A3
8068C–AVR–06/08
5
6. AVR CPU
6.1 Features
6.2 Overview
XMEGA A3
• 8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in RAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16M bytes of program and data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Support for 8-, 16- and 32-bit Arithmetic
• Configuration Change Protection of system critical features
The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure correct program execution. The CPU must therefore be able to access memories, perform
calculations and control peripherals. Interrupt handling is described in a separate section. Figure
6-1 on page 6 shows the CPU block diagram.
Figure 6-1. CPU block diagram
Program
Counter
OCD
STATUS/
CONTROL
Peripheral
Module 1
Peripheral
Module 2
DATA BUS
Flash
Program
Memory
Instruction
Register
Instruction
Decode
ALU
DATA BUS
32 x 8 General
Purpose
Registers
Multiplier/
DES
EEPROM PMICSRAM
8068C–AVR–06/08
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
6
This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Re-programmable Flash memory.
6.3 Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer for look up tables in Flash program memory.
6.4 ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
XMEGA A3
6.5 Program Flow
The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
8068C–AVR–06/08
7
7. Memories
7.1 Features
7.2 Overview
XMEGA A3
• Flash Program Memory
– One linear address space
– In-System programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte or page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status register for all peripherals and modules
16-bit accessible General Purpose Register for global variables or flags
– External Memory support
– Bus arbitration
Safe and deterministic handling of CPU and DMA Controller priority
– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access
Simultaneous bus access for CPU and DMA Controller
• Calibration Row Memory for factory programmed data
Oscillator calibration bytes
Serial number
Device ID for each device type
• User Signature Row
One flash page in size
Can be read and written from software
Data is kept after Chip Erase
8068C–AVR–06/08
The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configurations are shown in ”Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software.
8
7.3 In-System Programmable Flash Program Memory
The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program
storage, see Figure 7-1 on page 9. Since all AVR instructions are 16- or 32-bits wide, each Flash
address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash
memory.
A third section inside the Application section is referred to as the Application Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software.
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
XMEGA A3
0
1EFFF / 16FFF / EFFF / 77FF
1F000 / 17000 / F000 / 7800
1FFFF / 17FFF / FFFF / 7FFF
20000 / 18000 / 10000 / 8000
20FFF / 18FFF / 10FFF / 87FF
Application Section
(256K/192K/128K/64K)
...
Application Table Section
(8K/8K/8K/4K)
Boot Section
(8K/8K/8K/4K)
The Application Table Section and Boot Section can also be used for general application
software.
8068C–AVR–06/08
9
XMEGA A3
7.4 Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 10. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3
0
FFF FFF FFF
1000
1FFF
2000
5FFF 3FFF 2FFF
6000
FFFFFF FFFFFF FFFFFF
I/O Registers
(4KB)
EEPROM
(4K)
Internal SRAM
(16K)
External Memory
(0 - 16 MB)
0
1000
17FF 17FF
2000
4000
I/O Registers
(4KB)
EEPROM
(2K)
RESERVED RESERVED
Internal SRAM
(8K)
External Memory
(0 - 16 MB)
Byte Address ATxmega256A3
1000
2000
3000
0
FFF
1000
1FFF
2000
5FFF
6000
FFFFFF
0
I/O Registers
EEPROM
Internal SRAM
External Memory
(0 - 16 MB)
I/O Registers
(4KB)
EEPROM
Internal SRAM
(16K)
External Memory
(0 - 16 MB)
(4KB)
(2K)
(4K)
(4K)
8068C–AVR–06/08
10
7.4.1 I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the ”Periph-
eral Module Address Map” on page 53.
7.4.2 SRAM Data Memory
The XMEGA A3 devices has internal SRAM memory for data storage.
7.4.3 EEPROM Data Memory
XMEGA A3
The XMEGA A3 devices has internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
8068C–AVR–06/08
11
7.5 Calibration Row
The Calibration Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators, device ID, and a factory programmed serial
number that is unique for each device. The device ID for the available XMEGA A3 devices is
shown in Table 7-1 on page 12. Some of the calibration values will be automatically loaded to
the corresponding module or peripheral unit during reset. The Calibration Row can not be written
or erased. It can be read from application software and external programming.
Table 7-1. Device ID bytes for XMEGA A3 devices.
7.6 User Signature Row
XMEGA A3
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega64A3 42 96 1E
ATxmega128A3 42 97 1E
ATxmega192A3 44 97 1E
ATxmega256A3 42 98 1E
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. The User Signature Row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers, random number seeds etc. This section is not erased by Chip Erase, and requires a
dedicated erase command. This ensures parameter storage during multiple program/erase session and On-Chip Debug sessions.
8068C–AVR–06/08
12
XMEGA A3
7.7 Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 13 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Devices Flash Page Size FWORD FPAGE Application Boot
Size (Bytes) (words) Size No of Pages Size No of Pages
ATxmega64A3 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16
ATxmega128A3 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16
ATxmega192A3 192K + 8K 256 Z[8:1] Z[18:9] 192K 384 8K 16
ATxmega256A3 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16
Table 7-3 on page 13 shows EEPROM memory organization for the XMEGA A3 devices.
EEEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n] is used for addressing. The most significant bits in the address (E2PAGE)
gives the page number and the least significant address bits (E2BYTE) gives the byte in the
page.
Table 7-3. Number of bytes and Pages in the EEPROM.
Devices EEPROM Page Size E2BYTE E2PAGE No of Pages
Size (Bytes) (Bytes)
ATxmega64A3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega192A3 2K 32 ADDR[4:0] ADDR[10:5] 64
ATxmega256A3 4K 32 ADDR[4:0] ADDR[11:5] 128
8068C–AVR–06/08
13
8. DMAC - Direct Memory Access Controller
8.1 Features
• Allows High-speed data transfer
– From memory to peripheral
– From memory to memory
– From peripheral to memory
– From peripheral to peripheral
• 4 Channels
• From 1 byte and up to 16 M bytes transfers in a single transaction
• Multiple addressing modes for source and destination address
–Increment
– Decrement
– Static
• 1, 2, 4, or 8 bytes Burst Transfers
• Programmable priority between channels
8.2 Overview
The XMEGA A3 has a Direct Memory Access (DMA) Controller to move data between memories
and peripherals in the data space. The DMA controller uses the same data bus as the CPU to
transfer data.
XMEGA A3
It has 4 channels that can be configured independently. Each DMA channel can perform data
transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to
repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be
configured to access the source and destination memory address with incrementing, decrementing or static addressing. The addressing is independent for source and destination address.
When the transaction is complete the original source and destination address can automatically
be reloaded to be ready for the next transaction.
The DMAC can access all the peripherals through their I/O memory registers, and the DMA may
be used for automatic transfer of data to/from communication modules, as well as automatic
data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or
from port pins. A wide range of transfer triggers is available from the peripherals, Event System
and software. Each DMA channel has different transfer triggers.
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa.
The DMA controller can read from memory mapped EEPROM, but it cannot write to the
EEPROM or access the Flash.
8068C–AVR–06/08
14
9. Event System
9.1 Features
9.2 Overview
• Inter-peripheral communication and signalling with minimum latency
• CPU and DMA independent operation
• 8 Event Channels allows for up to 8 signals to be routed at the same time
• Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADCx)
– Analog Comparators (ACx)
– Ports (PORTx)
– System Clock (Clk
– Software (CPU)
SYS
)
• Events can be used by
– Timer/Counters (TCxn)
– Analog to Digital Converters (ADCx)
– Digital to Analog Converters (DACx)
– Ports (PORTx)
– DMA Controller (DMAC)
– IR Communication Module (IRCOM)
• The same event can be used by multiple peripherals for synchronized timing
• Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
• Functions in Active and Idle mode
XMEGA A3
8068C–AVR–06/08
The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 9-1 on page 16 shows a basic
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
15
Figure 9-1. Event system block diagram.
XMEGA A3
PORTx
ADCx
ClkSYS
CPU
RTC
Event Routing
Network
DACx
ACx
DMACIRCOM
T/Cxn
The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators
(ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU).
All events from all peripherals are always routed into the Event Routing Network. This consist of
eight multiplexers where each can be configured in software to select which event to be routed
into that event channel. All eight event channels are connected to the peripherals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
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10. System Clock and Clock options
10.1 Features
• Fast start-up time
• Safe run-time clock switching
• Internal Oscillators:
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32 kHz calibrated RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator
• External clock options
– 0.4 - 16 MHz Crystal Oscillator
– 32 kHz Crystal Oscillator
– External clock
• PLL with internal and external clock options with 2 to 31x multiplication
• Clock Prescalers with 2 to 2048x division
• Fast peripheral clock running at 2 and 4 times the CPU clock speed
• Automatic Run-Time Calibration of internal oscillators
• Crystal Oscillator failure detection
10.2 Overview
XMEGA A3
XMEGA A3 has an advanced clock system, supporting a large number of clock sources. It incorporates both integrated oscillators, external crystal oscillators and resonators. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a
wide range of clock frequencies from the clock source input.
It is possible to switch between clock sources from software during run-time. After reset the
device will always start up running from the 2 Mhz internal oscillator.
A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 18 shows the principal clock system in XMEGA A3.
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Figure 10-1. Clock system overview
32 kHz ULP
Internal Oscillator
32.768 kHz
Calibrated Internal
Oscillator
clk
clk
XMEGA A3
ULP
WDT/BOD
RTC
RTC
2 MHz
Run-Time Calibrated
Internal Oscillator
CLOCK CONTROL
32 MHz
Run-time Calibrated
Internal Oscillator
UNIT
with PLL and
clk
Prescaler
32.768 KHz
Crystal Oscillator
0.4 - 16 MHz
Crystal Oscillator
clk
External
Clock Input
Each clock source is briefly described in the following sub-sections.
PERIPHERALS
PER
INTERRUPT
NVM MEMORY
CPU
ADC
DAC
PORTS
...
DMA
EVSYS
RAM
CPU
FLASH
EEPROM
10.3 Clock Options
10.3.1 32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
10.3.2 32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during protection to provide a default frequency which is close to its nominal
frequency.
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10.3.3 32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be
used as system clock source or as asynchronous clock source for the Real Time Counter.
10.3.4 0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400 kHz to 16 MHz.
10.3.5 2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during protection to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a
source for calibrating the frequency run-time to compensate for temperature and voltage drift
hereby optimizing the accuracy of the oscillator.
10.3.6 32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during protection to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a
source for calibrating the frequency run-time to compensate for temperature and voltage drift
hereby optimizing the accuracy of the oscillator.
XMEGA A3
10.3.7 External Clock input
The external clock input gives the possibility to connect a clock from an external source.
10.3.8 PLL with Multiplication factor 2 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 2 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
• 5 sleep modes
–Idle
– Power-down
–Power-save
–Standby
– Extended standby
• Power Reduction registers to disable clocks to unused peripherals
11.2 Overview
The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the
CPU is executing application code. The application code decides when and what sleep mode to
enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode.
XMEGA A3
11.3 Sleep Modes
11.3.1 Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from
all enabled interrupts will wake the device.
11.3.2 Power-down Mode
In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts, e.g pin change.
11.3.3 Power-save Mode
Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will
keep running during sleep and the device can also wake up from RTC interrupts.
11.3.4 Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
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11.3.5 Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonators are used.
XMEGA A3
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12. System Control and Reset
12.1 Features
• Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscillator
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– JTAG Reset
– PDI reset
– Software reset
• Asynchronous reset
– No running clock in the device is required for reset
• Reset status register
12.2 Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should
be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector
address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset
Vector to the first address in the Boot Section.
XMEGA A3
The I/O ports of the AVR are immediately tri-stated when a reset source goes active.
The reset functionality is asynchronous, so no running clock is required to reset the device.
After the device is reset, the reset source can be determined by the application by reading the
Reset Status Register.
12.3 Reset Sources
12.3.1 Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
12.3.2 External Reset
The MCU is reset when a low level is present on the RESET pin.
12.3.3 Watchdog Reset
The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.
The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For
more details see ”WDT - Watchdog Timer” on page 23.
12.3.4 Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
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