Atmel ATxmega128A4U Datasheet

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8/16-bit Atmel XMEGA Microcontroller

ATxmega128A4U, ATxmega64A4U*,

ATxmega32A4U, ATxmega16A4U

*Preliminary

Features

z High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller

z Nonvolatile program and data memories

z 16K - 128KB of in-system self-programmable flash z 4K - 8KB boot section z 1K - 2KB EEPROM z 2K - 8KB internal SRAM

z Peripheral Features

z Four-channel DMA controller z Eight-channel event system z Five 16-bit timer/counters

z Three timer/counters with 4 output compare or input capture channels z Two timer/counters with 2 output compare or input capture channels z High-resolution extensions on all timer/counters z Advanced waveform extension (AWeX) on one timer/counter

z One USB device interface

z USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant

z 32 Endpoints with full configuration flexibility z Five USARTs with IrDA support for one USART z Two Two-wire interfaces with dual address match (I z Two serial peripheral interfaces (SPIs) z AES and DES crypto engine z CRC-16 (CRC-CCITT) and CRC-32 (IEEE z 16-bit real time counter (RTC) with separate oscillator z One twelve-channel, 12-bit, 2msps Analog to Digital Converter z One two-channel, 12-bit, 1msps Digital to Analog Converter z Two Analog Comparators with window compare function, and current sources z External interrupts on all general purpose I/O pins z Programmable watchdog timer with separate on-chip ultra low power oscillator z QTouch

z Special microcontroller features

z Power-on reset and programmable brown-out detection z Internal and external clock options with PLL and prescaler z Programmable multilevel interrupt controller z Five sleep modes z Programming and debug interfaces

z I/O and packages

z 34 Programmable I/O pins z 44 - lead TQFP z 44 - pad VQFN/QFN z 49 - ball VFBGA

z Operating voltage

z 1.6 – 3.6V

z Operating frequency

z 0 – 12MHz from 1.6V z 0 – 32MHz from 2.7V

library support

z Capacitive touch buttons, sliders and wheels

z PDI (program and debug interface)

C and SMBus compatible)

802.3) generator

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1. Ordering Information

Ordering code Flash (bytes) EEPROM (bytes) SRAM (bytes) Speed (MHz) Power supply Package

ATxmega128A4U-AU 128K + 4K 2K 8K

ATxmega128A4U-AUR

ATxmega64A4U-AU 64K + 4K 2K 4K

ATxmega64A4U-AUR

ATxmega32A4U-AU 128K + 4K 2K 4K

ATxmega32A4U-AUR

ATxmega16A4U-AU 16K + 4K 2K 2K

ATxmega16A4U-AUR

ATxmega128A4U-MH 128K + 4K 2K 8K

ATxmega128A4U-MHR

ATxmega64A4U-MH 64K + 4K 2K 4K

ATxmega64A4U-MHR

ATxmega32A4U-MH 128K + 4K 2K 4K

ATxmega32A4U-MHR

ATxmega16A4U-MH 16K + 4K 2K 2K

ATxmega16A4U-MHR

ATxmega128A4U-CU 128K + 8K 2K 8K

ATxmega128A4U-CUR

ATxmega64A4U-CU 64K + 4K 2K 4K

ATxmega64A4U-CUR

ATxmega32A4U-CU 128K + 4K 1K 4K

ATxmega32A4U-CUR

ATxmega16A4U-CU 16K + 4K 1K 2K

ATxmega16A4U-CUR

(4)

128K + 4K 2K 8K

64K + 4K 4K 4K

128K + 4K 2K 4K

16K + 4K 2K 2K

128K + 4K 2K 8K

64K + 4K 4K 4K

128K + 4K 2K 4K

16K + 4K 2K 2K

128K + 8K 2K 8K

64K + 4K 2K 4K

128K + 4K 1K 4K

16K + 4K 1K 2K

32 1.6 - 3.6V

44A

44M1

49C2

(1)(2)(3)

Tem p.

-40°C - 85°C

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For packaging information, see “Instruction Set Summary” on page 62.

4. Tape and Reel

Package Type

44A 44-Lead, 10 x 10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)

44M1 44-Pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, t hermally enhanced plastic very thin quad no lead package (VQFN)

PW 44-Pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)

49C2 49-Ball (7 x 7 Array), 0.65mm Pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA)

Typical Applications

Industrial control Climate control Low power battery applications

Factory automation RF and ZigBee

Power tools

Building control USB connectivity HVAC

Board control Sensor control Utility metering

White goods Optical Medical applications

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2. Pinout/Block Diagram

PA0

PA1

PA2

PA3

PA4

PB0

PB1

PB3

PB2

PA7

PA6

PA5

GND

VCC

PC0

VDD

GND

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PD0

PD1

PD2

PD3

PD4

PD5

PD6

VCC

GND

PD7

PE0

PE1

PE2

PE3

RESET/PDI

PDI

PR0

PR1

AVCC

GND

Power

Supervision

Port A

EVENT ROUTING NETWORK

DMA

Controller

BUS

matrix

SRAMFLASH

ADC

AC0:1

OCD

Port EPort D

Prog/Debug

Interface

EEPROM

Port C

TC0:1

Event System

Controller

Watchdog

Timer

Watchdog

OSC/CLK

Control

Real Time

Counter

Interrupt

Controller

DATA BUS

Port R

USART0:1

TWI

SPI

TC0:1

USART0:1

SPI

TC0

USART0

TWI

Port B

DAC

AREF

Sleep

Controller

Reset

Controller

IRCOM

Crypto /

CRC

USB

CPU

Internal

references

Internal

oscillators

XOSC TOSC

Digital function

Analog function / Oscillators

Programming, debug, test

External clock / Crystal pins

General Purpose I /O

Ground

Power

Figure 2-1. Block Diagram and QFN/TQFP pinout

Note: 1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55.

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Figure 2-2. BGA pinout

Top view

1 234567

Bottom view

7654321

Table 2-1. BGA pinout

1 2 3 4 5 6 7

A PA3 AV CC GND PR1 PR0 PDI_DATA PE3

B PA4 PA1 PA0 GND

RESET/

PDI_CLK

PE2 VCC

C PA5 PA2 PA6 PA7 GND PE1 GND

D PB1 PB2 PB3 PB0 GND PD7 PE0

E GND GND PC3 GND PD4 PD5 PD6

F VCC PC0 PC4 PC6 PD0 PD1 PD3

G PC1 PC2 PC5 PC7 GND VCC PD2

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3. Overview

The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.

The AVR XMEGA A4U devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable multilevel interrupt controller, 34 general purpose I/O lines, 16-bit real-time counter (RTC); five flexible, 16-bit timer/counters with compare and PWM channels; five USARTs; two two-wire serial interfaces (TWIs); one full speed USB 2.0 interface; two serial peripheral interfaces (SPIs); AES and DES cryptographic engine; one twelve-channel, 12bit ADC with programmable gain; one 2-channel 12-bit DAC; two analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.

The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.

The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode.

Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers.

The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications.

All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.

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3.1 Block Diagram

Power Supervision POR/BOD &

RESET

PORT A (8)

PORT B (8)

DMA

Controller

SRAM

ADCA

ACA

DACB

OCD

Int. Refs.

PDI

PA[0..7]

PB[0..7]

Watchdog

Timer

Watchdog

Oscillator

Interrupt

Controller

DATA BUS

Prog/Debug

Controller

VCC

GND

Oscillator

Circuits/

Clock

Generation

Oscillator

Control

Real Time

Counter

Event System

Controller

AREFA

AREFB

PDI_DATA

RESET/ PDI_CLK

Sleep

Controller

DES

CRC

PORT C (8)

PC[0..7]

TCC0:1

USARTC0:1

TWIC

SPIC

PD[0..7] PE[0..3]

PORT D (8)

TCD0:1

USARTD0:1

SPID

TCE0

USARTE0

TWIE

PORT E (4)

Tempref

AES

USB

PORT R (2)

DATA BUS

NVM Controller

MORPEEhsalF

IRCOM

BUS Matrix

CPU

EVENT ROUTING NETWORK

XTAL1/ TOSC1

XTAL2/ TOSC2

PR[0..1]

TOSC1 (optional)

TOSC2

(optional)

Digital function

Analog function

Programming, debug, test

Oscillator/Crystal/Cloc k

General Purpose I/O

Figure 3-1. XMEGA A4U Block Diagram

XMEGA A4U [DATASHEET]

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4. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

http://www.atmel.com/avr.

4.1 Recommended reading

z Atmel AVR XMEGA AU manual

z XMEGA application notes

This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals.

All documentation are available from www.atmel.com/avr.

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5. Capacitive touch sensing

The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide -

also available for download from the Atmel website.

(AKS®) technology for unambiguous detection of key

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6. AVR CPU

6.1 Features

• 8/16-bit, high-performance Atmel AVR RISC CPU

– 142 instructions – Hardware multiplier

• 32x8-bit registers directly connected to the ALU

• Stack in RAM

• Stack pointer accessible in I/O memory space

• Direct addressing of up to 16MB of program memory and 16MB of data memory

• True 16/24-bit access to 16/24-bit I/O registers

• Efficient support for 8-, 16-, and 32-bit arithmetic

• Configuration change protection of system-critical features

6.2 Overview

All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable

Multilevel Interrupt Controller” on page 28.

6.3 Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.

Figure 6-1. Block diagram of the AVR CPU architecture.

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The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations.

The memory spaces are linear. The data memory space and the program memory space are two different memory spaces.

The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be memory mapped in the data memory.

All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.

The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.

Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.

The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for safe storing of nonvolatile data in the program memory.

6.4 ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format.

6.4.1 Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers:

z Multiplication of unsigned integers

z Multiplication of signed integers

z Multiplication of a signed integer with an unsigned integer

z Multiplication of unsigned fractional numbers

z Multiplication of signed fractional numbers

z Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

6.5 Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched.

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Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU.

6.6 Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software.

The status register is accessible in the I/O memory space.

6.7 Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.

During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction.

The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction.

To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write.

After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-3 on page 15.

6.8 Register File

The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes:

z One 8-bit output operand and one 8-bit result input

z Two 8-bit output operands and one 8-bit result input

z Two 8-bit output operands and one 16-bit result input

z One 16-bit output operand and one 16-bit result input

Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory.

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7. Memories

7.1 Features

• Flash program memory

– One linear address space – In-system programmable – Self-programming and boot loader support – Application section for application code – Application table section for application code or data storage – Boot section for application code or boot loader code – Separate read/write protection lock bits for all sections – Built in fast CRC check of a selectable flash program memory section

• Data memory

– One linear address space – Single-cycle access from CPU – SRAM – EEPROM

Byte and page accessible Optional memory mapping for direct load and store

– I/O memory

Configuration and status registers for all peripherals and modules 16 bit-accessible general purpose registers for global variables or flags

– Bus arbitration

Deterministic priority handling between CPU, DMA controller, and other bus masters

– Separate buses for SRAM, EEPROM and I/O memory

Simultaneous bus access for CPU and DMA controller

• Production signature row memory for factory programmed data

– ID for each microcontroller device type – Serial number for each device – Calibration bytes for factory calibrated peripherals

• User signature row

– One flash page in size – Can be read and written from software – Content is kept after chip erase

7.2 Overview

The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software.

A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer.

The available memory size configurations are shown in Flash memory signature row for calibration data, device identification, serial number etc.

“Ordering Information” on page 2. In addition, each device has a

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7.3 Flash Program Memory

The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device.

All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section.

The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory.

Figure 7-1. Flash Program Memory (Hexadecimal address).

ATxmega128A4U ATxmega64A4U ATxmega32A4U ATxmega16A4U

Word Address

0 0 0 0

EFFF / 77FF / 37FF / 17FF

F000 / 7800 / 3800 / 1800

FFFF / 7FFF / 3FFF / 1FFF

10000 / 8000 / 4000 / 2000

10FFF / 87FF / 47FF / 27FF

7.3.1 Application Section

The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section.

7.3.2 Application Table Section

The application table section is a part of the application section of the flash memory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here.

Application Section

(128K/64K/32K/16K)

...

Application Table Section

(4K/4K/4K/4K)

Boot Section

(8K/4K/4K/4K)

7.3.3 Boot Loader Section

While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here.

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7.3.4 Production Signature Row

The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical

Characteristics” on page 71.

The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-2.

The production signature row cannot be written or erased, but it can be read from application software and external programmers.

Figure 7-2. Device ID bytes for Atmel AVR XMEGA A4U devices.

Device Device ID bytes

ATxmega16A4U 41 94 1E

ATxmega32A4U 41 95 1E

ATxmega64A4U 46 96 1E

ATxmega128A4U 46 97 1E

Byte 2 Byte 1 Byte 0

7.3.5 User Signature Row

The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions.

7.4 Fuses and Lock bits

The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, JTAG enable, and JTAG user ID.

The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased.

An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.

Both fuses and lock bits are reprogrammable like the flash program memory.

7.5 Data Memory

The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 7-3. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices.

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Figure 7-3. Data memory map (Hexadecimal address).

Byte Address ATxmega64A4U Byte Address ATxmega32A4U Byte Address ATxmega16A4U

I/O Registers (4K)

FFF FFF FFF

1000

EEPROM (2K)

17FF 13FF 13FF

RESERVED RESERVED RESERVED

2000

Internal SRAM (4K)

2FFF 2FFF 27FF

Byte Address ATxmega128A4U

I/O Registers (4K)

FFF

1000

EEPROM (2K)

17FF

RESERVED

2000

Internal SRAM (8K)

3FFF

1000

2000

I/O Registers (4K)

EEPROM (1K)

Internal SRAM (4K)

I/O Registers (4K)

1000

EEPROM (1K)

2000

Internal SRAM (2K)

7.6 EEPROM

All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000.

7.7 I/O Memory

The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F, single-cycle instructions for manipulation and checking of individual bits are available.

The I/O memory address for all peripherals and modules in XMEGA A4U is shown in the “Peripheral Module Address

Map” on page 60.

7.7.1 General Purpose I/O Registers

The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

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7.8 Data Memory and Bus Arbitration

Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memory sections at the same time.

7.9 Memory Timing

Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing.

7.10 Device ID and Revision

Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device.

7.11 I/O Memory Protection

Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism.

7.12 Flash and EEPROM Page Size

The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM.

Table 7-1 on page 16 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and

erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page.

Table 7-1. Number of words and pages in the flash.

Devices PC size Flash size Page Size FWORD FPAGE Application Boot

bits bytes words Size

ATxmega16A4U 14 16K + 4K 128 Z[6:0] Z[13:7] 16K 64 4K 16

ATxmega32A4U 15 32K + 4K 128 Z[6:0] Z[14:7] 32K 128 4K 16

ATxmega64A4U 16 64K + 4K 128 Z[6:0] Z[15:7] 64K 256 4K 16

ATxmega128A4U 17 128K + 8K 128 Z[8:0] Z[16:7] 128K 512 8K 32

No of pages

Size

No of pages

Table 7-2 shows EEPROM memory organization for the Atmel AVR XMEGA A4U devices. EEEPROM write and erase

operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.

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Table 7-2. Number of bytes and pages in the EEPROM.

Devices EEPROM Page Size E2BYTE E2PAGE No of Pages

Size bytes

ATxmega16A4U 1K 32 ADDR[4:0] ADDR[10:5] 32

ATxmega32A4U 1K 32 ADDR[4:0] ADDR[10:5] 32

ATxmega64A4U 2K 32 ADDR[4:0] ADDR[10:5] 64

ATxmega128A4U 2K 32 ADDR[4:0] ADDR[10:5] 64

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8. DMAC – Direct Memory Access Controller

8.1 Features

• Allows high speed data transfers with minimal CPU intervention

– from data memory to data memory – from data memory to peripheral – from peripheral to data memory – from peripheral to peripheral

• Four DMA channels with separate

– transfer triggers – interrupt vectors – addressing modes

• Programmable channel priority

• From 1 byte to 16MB of data in a single transaction

– Up to 64KB block transfers with repeat – 1, 2, 4, or 8 byte burst transfers

• Multiple addressing modes

– Static –Incremental – Decremental

• Optional reload of source and destination addresses at the end of each

–Burst –Block – Transaction

• Optional interrupt on end of transaction

• Optional connection to CRC generator for CRC on DMA data

8.2 Overview

The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The four DMA channels enable up to four independent and parallel transfers.

The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from communication modules. The DMA controller can also read from memory mapped EEPROM.

Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events can trigger DMA transfers.

The four DMA channels have individual configuration and control settings. This include source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction is complete or when the DMA controller detects an error on a DMA channel.

To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa.

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9. Event System

9.1 Features

• System for direct peripheral-to-peripheral communication and signaling

• Peripherals can directly send, receive, and react to peripheral events

– CPU and DMA controller independent operation – 100% predictable signal timing – Short and guaranteed response time

• Eight event channels for up to eight different and parallel signal routing configurations

• Events can be sent and/or used by most peripherals, clock system, and software

• Additional functions include

– Quadrature decoders – Digital filtering of I/O pin state

• Works in active mode and idle sleep mode

9.2 Overview

The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It also allows for synchronized timing of actions in several peripheral modules.

A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software.

Figure 9-1 on page 19 shows a basic diagram of all connected peripherals. The event system can directly connect

together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller). Events can also be generated from software and the peripheral clock.

Figure 9-1. Event system overview and connected peripherals.

ADC

DAC

CPU /

Software

Event Routing Network

System

Controller

Port pins

Event

DMA

Controller

IRCOM

clk

PER

Prescaler

Real Time

Counter

Timer /

Counters

USB

The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.

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10. System Clock and Clock options

10.1 Features

• Fast start-up time

• Safe run-time clock switching

• Internal oscillators:

– 32MHz run-time calibrated and tuneable oscillator – 2MHz run-time calibrated oscillator – 32.768kHz calibrated oscillator – 32kHz ultra low power (ULP) oscillator with 1kHz output

• External clock options

– 0.4MHz - 16MHz crystal oscillator – 32.768kHz crystal oscillator – External clock

• PLL with 20MHz - 128MHz output frequency

– Internal and external clock options and 1x to 31x multiplication – Lock detector

• Clock prescalers with 1x to 2048x division

• Fast peripheral clocks running at two and four times the CPU clock

• Automatic run-time calibration of internal oscillators

• External oscillator and PLL lock failure detection with optional non-maskable interrupt

10.2 Overview

Atmel AVR XMEGA A4U devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails.

When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time.

Figure 10-1 on page 21 presents the principal clock system in the XMEGA A4U family of devices. Not all of the clocks

need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in “Power Management and Sleep Modes” on page 23.

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Figure 10-1. The clock system, clock sources and clock distribution.

Real Time

Counter

Peripherals

RAM AVR CPU

Non-Volatile

Memory

Watchdog

Timer

Brown-out

Detector

System Clock Prescalers

USB

Prescaler

System Clock Multiplexer

(SCLKSEL)

PLLSRC

RTCSRC

DIV32

32 kHz

Int. ULP

32.768 kHz Int. OSC

32.768 kHz TOSC

2 MHz

Int. Osc

32 MHz Int. Osc

0.4 – 16 MHz XTAL

DIV32

DIV4

XOSCSEL

PLL

USBSRC

TOSC1

TOSC2

XTAL1

XTAL2

clk

SYS

clk

RTC

clk

PER2

clk

PER

clk

CPU

clk

PER4

clk

USB

10.3 Clock Sources

The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources, DFLLs and PLL, are turned off by default.

The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet.

10.3.1 32kHz Ultra Low Power Internal Oscillator

This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a

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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC.

10.3.2 32.768kHz Calibrated Internal Oscillator

This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output.

10.3.3 32.768kHz Crystal Oscillator

A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.

10.3.4 0.4 - 16MHz Crystal Oscillator

This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.

10.3.5 2MHz Run-time Calibrated Internal Oscillator

The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.

10.3.6 32MHz Run-time Calibrated Internal Oscillator

The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The production signature row contains 48MHz calibration values intended used when the oscillator is used a full-speed USB clock source.

10.3.7 External Clock Sources

The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a

32.768kHz crystal oscillator.

10.3.8 PLL with 1x-31x Multiplication Factor

The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.

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11. Power Management and Sleep Modes

11.1 Features

• Power management for adjusting power consumption and functions

• Five sleep modes

–Idle –Power down – Power save –Standby – Extended standby

• Power reduction register to disable clock and turn off unused peripherals in active and idle modes

11.2 Overview

Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.

All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode.

In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone.

11.3 Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts.

The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector.

11.3.1 Idle Mode

In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled interrupt will wake the device.

11.3.2 Power-down Mode

In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.

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11.3.3 Power-save Mode

Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.

11.3.4 Standby Mode

Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.

11.3.5 Extended Standby Mode

Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.

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12. System Control and Reset

12.1 Features

• Reset the microcontroller and set it to initial state when a reset source goes active

• Multiple reset sources that cover different situations

–Power-on reset – External reset – Watchdog reset – Brownout reset – PDI reset – Software reset

• Asynchronous operation

– No running system clock in the device is required for reset

• Reset status register for reading the reset source from the application code

12.2 Overview

The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed.

After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section.

The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software.

The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on.

12.3 Reset Sequence

A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again:

z Reset counter delay

z Oscillator startup

z Oscillator calibration

If another reset requests occurs during this process, the reset sequence will start over again.

12.4 Reset Sources

12.4.1 Power-on Reset

A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and reaches the POR threshold voltage (V

The POR is also activated to power down the device properly when the V

The V

level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.

POT

), and this will start the reset sequence.

POT

falls and drops below the V

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12.4.2 Brownout Detection

The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled.

12.4.3 External Reset

The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET

pin threshold voltage, V

held as long as the pin is kept low. The RESET

12.4.4 Watchdog Reset

The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 27.

12.4.5 Software Reset

The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued.

12.4.6 Program and Debug Interface Reset

The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers.

, for longer than the minimum pulse period, t

RST

pin includes an internal pull-up resistor.

. The reset will be

EXT

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13. WDT – Watchdog Timer

13.1 Features

• Issues a device reset if the timer is not reset before its timeout period

• Asynchronous operation from dedicated oscillator

• 1kHz output of the 32kHz ultra low power oscillator

• 11 selectable timeout periods, from 8ms to 8s

• Two operation modes:

– Normal mode – Window mode

• Configuration lock to prevent unwanted changes

13.2 Overview

The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code.

The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.

The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail.

The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available.

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14. Interrupts and Programmable Multilevel Interrupt Controller

14.1 Features

• Short and predictable interrupt response time

• Separate interrupt configuration and vector address for each interrupt

• Programmable multilevel interrupt controller

– Interrupt prioritizing according to level and vector address – Three selectable interrupt levels for all interrupts: low, medium and high – Selectable, round-robin priority scheme within low-level interrupts – Non-maskable interrupts for critical functions

• Interrupt vectors optionally placed in the application section or the boot loader section

14.2 Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time.

Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.

14.3 Interrupt vectors

The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA A4U devices are shown in Table 14-1 on page 29. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page 29. The program address is the word address.

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Table 14-1. Reset and interrupt vectors

Program address

(base address) Source Interrupt description

0x000 RESET

0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI)

0x004 PORTC_INT_base Port C interrupt base

0x008 PORTR_INT_base Port R interrupt base

0x00C DMA_INT_base DMA controller interrupt base

0x014 RTC_INT_base Real time counter interrupt base

0x018 TWIC_INT_base Two-Wire Interface on Port C interrupt base

0x01C TCC0_INT_base Timer/counter 0 on port C interrupt base

0x028 TCC1_INT_base Timer/counter 1 on port C interrupt base

0x030 SPIC_INT_vect SPI on port C interrupt vector

0x032 USARTC0_INT_base USART 0 on port C interrupt base

0x038 USARTC1_INT_base USART 1 on port C interrupt base

0x03E AES_INT_vect AES interrupt vector

0x040 NVM_INT_base Nonvolatile Memory interrupt base

0x044 PORTB_INT_base Port B interrupt base

0x056 PORTE_INT_base Port E interrupt base

0x05A TWIE_INT_base Two-wire Interface on Port E interrupt base

0x05E TCE0_INT_base Timer/counter 0 on port E interrupt base

0x06A TCE1_INT_base Timer/counter 1 on port E interrupt base

0x074 USARTE0_INT_base USART 0 on port E interrupt base

0x080 PORTD_INT_base Port D interrupt base

0x084 PORTA_INT_base Port A interrupt base

0x088 ACA_INT_base Analog Comparator on Port A interrupt base

0x08E ADCA_INT_base Analog to Digital Converter on Port A interrupt base

0x09A TCD0_INT_base Timer/counter 0 on port D interrupt base

0x0A6 TCD1_INT_base Timer/counter 1 on port D interrupt base

0x0AE SPID_INT_vector SPI on port D interrupt vector

0x0B0 USARTD0_INT_base USART 0 on port D interrupt base

0x0B6 USARTD1_INT_base USART 1 on port D interrupt base

0x0FA USB_INT_base USB on port D interrupt base

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15. I/O Ports

15.1 Features

• 34 general purpose input and output pins with individual configuration

• Output driver with configurable driver and pull settings:

–Totem-pole – Wired-AND –Wired-OR – Bus-keeper – Inverted I/O

• Input with synchronous and/or asynchronous sensing with interrupts and events

– Sense both edges – Sense rising edges – Sense falling edges – Sense low level

• Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations

• Optional slew rate control

• Asynchronous pin change sensing that can wake the device from all sleep modes

• Two port interrupts with pin masking per I/O port

• Efficient and safe access to port pins

– Hardware read-modify-write through dedicated toggle/clear/set registers – Configuration of multiple pins in a single operation – Mapping of port registers into bit-accessible I/O memory space

• Peripheral clocks output on port pin

• Real-time counter clock output to port pin

• Event channels can be output on port pin

• Remapping of digital peripheral pin functions

– Selectable USART, SPI, and timer/counter input/output pin locations

15.2 Overview

One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running.

All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin.

The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs.

The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR.

15.3 Output Driver

All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission.

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15.3.1 Push-pull

INn

OUTn

DIRn

INn

OUTn

DIRn

INn

OUTn

DIRn

Figure 15-1. I/O configuration - Totem-pole.

15.3.2 Pull-down

Figure 15-2. I/O configuration - Totem-pole with pull-down (on input).

15.3.3 Pull-up

Figure 15-3. I/O configuration - Totem-pole with pull-up (on input).

15.3.4 Bus-keeper

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.

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Figure 15-4. I/O configuration - Totem-pole with bus-keeper.

INn

OUTn

DIRn

INn

OUTn

INn

OUTn

15.3.5 Others

Figure 15-5. Output configuration - Wired-OR with optional pull-down.

Figure 15-6. I/O configuration - Wired-AND with optional pull-up.

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15.4 Input sensing

INVERTED I/O

Int errupt

Cont rol

IREQ

Event

Synchroni zer

INn

EDGE

DETECT

Asynchronous sensi ng

Synchronous sensing

EDGE

DETECT

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7.

Figure 15-7. Input sensing system overview.

When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.

15.5 Alternate Port Functions

Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin.

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16. TC0/1 – 16-bit Timer/Counter Type 0 and 1

16.1 Features

• Five 16-bit timer/counters

– Three timer/counters of type 0 – Two timer/counters of type 1 – Split-mode enabling two 8-bit timer/counter from each timer/counter type 0

• 32-bit timer/counter support by cascading two timer/counters

• Up to four compare or capture (CC) channels

– Four CC channels for timer/counters of type 0 – Two CC channels for timer/counters of type 1

• Double buffered timer period setting

• Double buffered capture or compare channels

• Waveform generation:

– Frequency generation – Single-slope pulse width modulation – Dual-slope pulse width modulation

• Input capture:

– Input capture with noise cancelling – Frequency capture – Pulse width capture – 32-bit input capture

• Timer overflow and error interrupts/events

• One compare match or input capture interrupt/event per CC channel

• Can be used with event system for:

– Quadrature decoding – Count and direction control –Capture

• Can be used with DMA and to trigger DMA transactions

• High-resolution extension

– Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)

• Advanced waveform extension:

– Low- and high-side output with programmable dead-time insertion (DTI)

• Event controlled fault protection for safe disabling of drivers

16.2 Overview

Atmel AVR XMEGA devices have a set of five flexible 16-bit Timer/Counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.

A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time.

A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations.

There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each.

Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-

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side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can

AWeX

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

Waveform

Generation

Buffer

Comparator

Hi-Res

Fault

Protection

Capture

Control

Base Counter

Counter

Control Logic

Timer Period

Prescaler

Dead-Time

Insertion

Pattern

Generation

clk

PER4

PORT

Event

System

clk

PER

Timer/Counter

also generate a synchronized bit pattern across the port pins.

The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 37 for more details.

The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution

Extension” on page 38 for more details.

Figure 16-1. Overview of a Timer/Counter and closely related peripherals.

PORTC and PORTD each has one Timer/Counter 0 and one Timer/Counter1. PORTE has one Timer/Conter0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1 and TCE0, respectively.

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17. TC2 - Timer/Counter Type 2

17.1 Features

• Six eight-bit timer/counters

– Three Low-byte timer/counter – Three High-byte timer/counter

• Up to eight compare channels in each Timer/Counter 2

– Four compare channels for the low-byte timer/counter – Four compare channels for the high-byte timer/counter

• Waveform generation

– Single slope pulse width modulation

• Timer underflow interrupts/events

• One compare match interrupt/event per compare channel for the low-byte timer/counter

• Can be used with the event system for count control

• Can be used to trigger DMA transactions

17.2 Overview

There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM channels.

The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always counting down.

PORTC, and PORTD each has one Timer/Counter 2.

Notation of these are TCC2 (Time/Counter C2) and TCD2, respectively.

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18. AWeX – Advanced Waveform Extension

18.1 Features

• Waveform output with complementary output from each compare channel

• Four dead-time insertion (DTI) units

– 8-bit resolution – Separate high and low side dead-time setting – Double buffered dead time – Optionally halts timer during dead-time insertion

• Pattern generation unit creating synchronised bit pattern across the port pins

– Double buffered pattern generation – Optional distribution of one compare channel output across the port pins

• Event controlled fault protection for instant and predictable fault triggering

18.2 Overview

The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for use with different types of motor control and other power control applications. It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins.

Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the noninverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting.

The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed.

The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers.

The AWeX is available for TCC0. The notation of this is AWEXC.

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19. Hi-Res – High Resolution Extension

19.1 Features

• Increases waveform generator resolution up to 8x (three bits)

• Supports frequency, single-slope PWM, and dual-slope PWM generation

• Supports the AWeX when this is used for the same timer/counter

19.2 Overview

The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter.

The hi-res extension uses the peripheral 4x clock (Clk peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled.

There are three hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD and PORTE. The notation of these are HIRESC, HIRESD and HIRESE, respectively.

PER4

). The system clock prescalers must be configured so the

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20. RTC – 16-bit Real-Time Counter

32.768kHz Crystal Osc

32.768kHz Int. Osc

TOSC1

TOSC2

External Clock

DIV32

32kHz int ULP (DIV32)

RTCSRC

10-bit

prescaler

clk

RTC

CNT

PER

COMP

”match”/

Compare

TOP/

Overflow

20.1 Features

• 16-bit resolution

• Selectable clock source

– 32.768kHz external crystal – External clock – 32.768kHz internal oscillator – 32kHz internal ULP oscillator

• Programmable 10-bit clock prescaling

• One compare register

• One period register

• Clear counter on period overflow

• Optional interrupt/event on overflow and compare match

20.2 Overview

The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.

The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz internal ULP oscillator.

The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value.

Figure 20-1. Real-time counter overview.

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21. USB – Universal Serial Bus Interface

21.1 Features

• One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface

• Integrated on-chip USB transceiver, no external components needed

• 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints

– One input endpoint per endpoint address – One output endpoint per endpoint address

• Endpoint address transfer type selectable to

– Control transfers – Interrupt transfers – Bulk transfers – Isochronous transfers

• Configurable data payload size per endpoint, up to 1023 bytes

• Endpoint configuration and data buffers located in internal SRAM

– Configurable location for endpoint configuration data – Configurable location for each endpoint's data buffer

• Built-in direct memory access (DMA) to internal SRAM for:

– Endpoint configurations – Reading and writing endpoint data

• Ping-pong operation for higher throughput and double buffered operation

– Input and output endpoint data buffers used in a single direction – CPU/DMA controller can update data buffer during transfer

• Multipacket transfer for reduced interrupt load and software intervention

– Data payload exceeding maximum packet size is transferred in one continuous transfer – No interrupts or software interaction on packet transaction level

• Transaction complete FIFO for workflow management when using multiple endpoints

– Tracks all completed transactions in a first-come, first-served work queue

• Clock selection independent of system clock source and selection

• Minimum 1.5MHz CPU clock required for low speed USB operation

• Minimum 12MHz CPU clock required for full speed operation

• Connection to event system

• On chip debug possibilities during USB transactions

21.2 Overview

The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.

The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it supports data payloads up to 1023 bytes.

No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place.

To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication.

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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers.

For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode.

PORTD has one USB. Notation of this is USB.

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22. TWI – Two-Wire Interface

22.1 Features

• Two Identical two-wire interface peripherals

• Bidirectional, two-wire communication interface

– Phillips I – System Management Bus (SMBus) compatible

• Bus master and slave operation supported

– Slave operation – Single bus master operation – Bus master in multi-master bus environment – Multi-master arbitration

• Flexible slave address match functions

– 7-bit and general call address recognition in hardware – 10-bit addressing supported – Address mask register for dual address match or address range masking – Optional software address recognition for unlimited number of addresses

• Slave can operate in all sleep modes, including power-down

• Slave address match can wake device from all sleep modes

• 100kHz and 400kHz bus frequency support

• Slew-rate limited output drivers

• Input filter for bus noise and spike suppression

• Support arbitration between start/repeated start and data bit (SMBus)

• Slave arbitration allows support for address resolve protocol (ARP) (SMBus)

C compatible

22.2 Overview

The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.

A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.

The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity.

The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead.

The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes.

It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different V the TWI bus.

PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.

voltage than used by

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23. PI – Serial Peripheral Interface

23.1 Features

• Two Identical SPI peripherals

• Full-duplex, three-wire synchronous data transfer

• Master or slave operation

• Lsb first or msb first data transfer

• Eight programmable bit rates

• Interrupt flag at the end of transmission

• Write collision flag to indicate data collision

• Wake up from idle sleep mode

• Double speed master mode

23.2 Overview

The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several microcontrollers. The SPI supports full-duplex communication.

A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.

PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID.

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24. USART

24.1 Features

• Five identical USART peripherals

• Full-duplex operation

• Asynchronous or synchronous operation

– Synchronous clock rates up to 1/2 of the device clock frequency – Asynchronous clock rates up to 1/8 of the device clock frequency

• Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits

• Fractional baud rate generator

– Can generate desired baud rate from any system clock frequency – No need for external oscillator with certain frequencies

• Built-in error detection and correction schemes

– Odd or even parity generation and parity check – Data overrun and framing error detection – Noise filtering includes false start bit detection and digital low-pass filter

• Separate interrupts for

– Transmit complete – Transmit data register empty – Receive complete

• Multiprocessor communication mode

– Addressing scheme to address a specific devices on a multidevice bus – Enable unaddressed devices to automatically ignore all frames

• Master SPI mode

– Double buffered operation – Operation up to 1/2 of the peripheral clock frequency

• IRCOM module for IrDA compliant pulse modulation/demodulation

24.2 Overview

The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled.

The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation.

When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings.

An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2Kbps.

PORTC and PORTD each has two USARTs. PORTE has one USART. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1 and USARTE0, respectively.

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25. IRCOM – IR Communication Module

25.1 Features

• Pulse modulation/demodulation for infrared communication

• IrDA compatible for baud rates up to 115.2Kbps

• Selectable pulse modulation scheme

– 3/16 of the baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled

• Built-in filtering

• Can be connected to and used by any USART

25.2 Overview

Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.

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26. AES and DES Crypto Engine

26.1 Features

• Data Encryption Standard (DES) CPU instruction

• Advanced Encryption Standard (AES) crypto module

• DES Instruction

– Encryption and decryption – DES supported – Encryption/decryption in 16 CPU clock cycles per 8-byte block

• AES crypto module

– Encryption and decryption – Supports 128-bit keys – Supports XOR data load mode to the state memory – Encryption/decryption in 375 clock cycles per 16-byte block

26.2 Overview

The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.

DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.

The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.

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27. CRC – Cyclic Redundancy Check Generator

27.1 Features

• Cyclic redundancy check (CRC) generation and checking for

– Communication data – Program or data in flash memory – Data in SRAM and I/O memory space

• Integrated with flash memory, DMA controller and CPU

– Continuous CRC on data going through a DMA channel – Automatic CRC of the complete or a selectable range of the flash memory – CPU can load data to the CRC generator through the I/O interface

• CRC polynomial software selectable to

– CRC-16 (CRC-CCITT) – CRC-32 (IEEE 802.3)

• Zero remainder detection

27.2 Overview

A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data.

Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2 bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRCCCITT) and CRC-32 (IEEE 802.3).

z CRC-16:

-n

of all longer error

Polynomial: x16+x12+x5+1

Hex value: 0x1021

z CRC-32:

Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1

Hex value: 0x04C11DB7

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28. ADC – 12-bit Analog to Digital Converter

28.1 Features

• One Analog to Digital Converter (ADC)

• 12-bit resolution

• Up to two million samples per second

– Two inputs can be sampled simultaneously using ADC and 1x gain stage – Four inputs can be sampled within 1.5µs –Down to 2.5µs conversion time with 8-bit resolution –Down to 3.5µs conversion time with 12-bit resolution

• Differential and single-ended input

– Up to 12 single-ended inputs – 12x4 differential inputs without gain – 8x4 differential inputs with gain

• Built-in differential gain stage

1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options

–

• Single, continuous and scan conversion options

• Four internal inputs

– Internal temperature sensor – DAC output

voltage divided by 10

–V

– 1.1V bandgap voltage

• Four conversion channels with individual input control and result registers

– Enable four parallel configurations and results

• Internal and external reference options

• Compare function for accurate monitoring of user defined thresholds

• Optional event triggered conversion for accurate timing

• Optional DMA transfer of conversion results

• Optional interrupt/event on compare result

28.2 Overview

The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to two million samples per second (msps). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.

This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at a low system clock frequency. It also means that a new input can be sampled and a new ADC conversion started while other ADC conversions are still ongoing. This removes dependencies between sample rate and propagation delay.

The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start control. The ADC can then keep and use four parallel configurations and results, and this will ease use for applications with high data throughput or for multiple modules using the ADC independently. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.

Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The output from the DAC, V

The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required.

/10 and the bandgap voltage can also be measured by the ADC.

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Figure 28-1. ADC overview.

CH1 Result

CH0 Result

CH2 Result

Compare

< >

Threshold

(Int Req)

Internal 1.00V

Internal VCC/1.6V

AREFA AREFB

INP

INN

Internal

signals

Internal VCC/2

Internal

signals

CH3 Result

ADC0

ADC7

ADC4

ADC7

ADC0

ADC3

•

Int. signals

Reference Voltage

½x - 64x

•

ADC0

ADC11

•

Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and the gain stage has 1x gain setting. Four inputs can be sampled within 1.5µs without any intervention by the application.

The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5µs for 12-bit to 2.5µs for 8-bit result.

ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number).

PORTA has one ADC. Notation of this peripheral is ADCA.

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29. DAC – 12-bit Digital to Analog Converter

DAC0

DAC1

CTRLA

CH1DATA

CH0DATA

Trigger

Internal Output enable

Enable

Internal 1.00V

AREFA AREFB

Reference

selection

AVCC

Output Driver

D A T A

Int. driver

D A T A

CTRLB

DMA req

(Data Empty)

DMA req

(Data Empty)

Select

Enable

To AC/ADC

29.1 Features

• One Digital to Analog Converter (DAC)

• 12-bit resolution

• Two independent, continuous-drive output channels

• Up to one million samples per second conversion rate per DAC channel

• Built-in calibration that removes:

– Offset error –Gain error

• Multiple conversion trigger sources

– On new available data – Events from the event system

• High drive capabilities and support for

– Resistive loads – Capacitive loads – Combined resistive and capacitive loads

• Internal and external reference options

• DAC output available as input to analog comparator and ADC

• Low-power mode, with reduced drive strength

• Optional DMA transfer of data

29.2 Overview

The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in calibration system can remove offset and gain error when loaded with calibration values from software.

Figure 29-1. DAC overview.

A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.

The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

voltage references can be used. The DAC output is also internally available for use as input to the analog comparator or ADC.

PORTB has one DAC. Notation of this peripheral is DACB.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

30. AC – Analog Comparator

30.1 Features

• Two Analog Comparators (ACs)

• Selectable propagation delay versus current consumption

• Selectable hysteresis

–No –Small –Large

• Analog comparator output available on pin

• Flexible input selection

– All pins on the port – Output from the DAC – Bandgap reference voltage – A 64-level programmable voltage scaler of the internal V

• Interrupt and event generation on:

– Rising edge – Falling edge – Toggle

• Window function interrupt and event generation on:

– Signal above window – Signal inside window – Signal below window

• Constant current source with configurable output pin selection

voltage

30.2 Overview

The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change.

Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of these parameters may be adjusted in order to achieve the optimal operation for each application.

The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The analog comparator output state can also be output on a pin for use by external devices.

A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications.

The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level.

PORTA has one AC pair. Notation is ACA.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Figure 30-1. Analog comparator overview.

Voltage Scaler

ACnMUXCTRL

ACnCTRL

Interrupt

Mode

Enable

Hysteresis

DAC

Bandgap

AC1OUT

WINCTRL

Interrupt

Sensititivity

Control

Window

Function

Events

Interrupts

AC0OUT

Pin Input

AC0

AC1

Input signal

Upper limit of window

Lower limit of window

Interrupt

sensitivity

control

Interrupts

Events

The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in

Figure 30-2.

Figure 30-2. Analog comparator window function.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

31. Programming and Debugging

31.1 Features

• Programming

– External programming through PDI interface

Minimal protocol overhead for fast operation Built-in error detection and handling for reliable operation

– Boot loader support for programming through any communication interface

• Debugging

– Nonintrusive, real-time, on-chip debug system – No software or hardware resources required from device except pin connection – Program flow control

Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor – Unlimited number of user program breakpoints – Unlimited number of user data breakpoints, break on:

Data location read, write, or both read and write

Data location content equal or not equal to a value

Data location content is greater or smaller than a value

Data location content is within or outside a range – No limitation on device clock frequency

• Program and Debug Interface (PDI)

– Two-pin interface for external programming and debugging – Uses the Reset pin and a dedicated pin – No I/O pins required during programming or debugging

31.2 Overview

The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device.

The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row.

Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level.

Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer, which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std.

1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the PDI physical layer.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

32. Pinout and Pin Functions

The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time.

32.1 Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function.

32.1.1 Operation/Power Supply

GND Ground

Digital supply voltage

Analog supply voltage

32.1.2 Port Interrupt functions

SYNC Port pin with full synchronous and limited asynchronous interrupt function

ASYNC Port pin with full synchronous and full asynchronous interrupt function

32.1.3 Analog functions

ACn Analog Comparator input pin n

ACnOUT Analog Comparator n Output

ADCn Analog to Digital Converter input pin n

DACn Digital to Analog Converter output pin n

REF

Analog Reference input pin

32.1.4 Timer/Counter and AWEX functions

OCnxLS Output Compare Channel x Low Side for Timer/Counter n

OCnxHS Output Compare Channel x High Side for Timer/Counter n

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

32.1.5 Communication functions

SCL Serial Clock for TWI

SDA Serial Data for TWI

SCLIN Serial Clock In for TWI when external driver interface is enabled

SCLOUT Serial Clock Out for TWI when external driver interface is enabled

SDAIN Serial Data In for TWI when external driver interface is enabled

SDAOUT Serial Data Out for TWI when external driver interface is enabled

XCKn Transfer Clock for USART n

RXDn Receiver Data for USART n

TXDn Transmitter Data for USART n

SS Slave Select for SPI

MOSI Master Out Slave In for SPI

MISO Master In Slave Out for SPI

SCK Serial Clock for SPI

D- Data- for USB

D+ Data+ for USB

32.1.6 Oscillators, Clock and Event

TOSCn Timer Oscillator pin n

XTALn Input/Output for Oscillator pin n

CLKOUT Peripheral Clock Output

EVOUT Event Channel Output

RTCOUT RTC Clock Source Output

32.1.7 Debug/System functions

RESET Reset pin

PDI_CLK Program and Debug Interface Clock pin

PDI_DATA Program and Debug Interface Data pin

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

32.2 Alternate Pin Functions

The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions.

For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply.

Table 32-1. Port A - alternate functions.

PORT A PIN # INTERRUPT ADCA

POS/GAINPOS

GND 38

AVC C 39

PA0 40 SYNC ADC0 ADC0 AC0 AC0 AREF

PA1 41 SYNC ADC1 ADC1 AC1 AC1

PA2 42 SYNC/ASYNC ADC2 ADC2 AC2

PA3 43 SYNC ADC3 ADC3 AC3 AC3

PA4 44 SYNC ADC4 ADC4 AC4

PA5 1 SYNC ADC5 ADC5 AC5 AC5

PA6 2 SYNC ADC6 ADC6 AC6 AC1OUT

PA7 3 SYNC ADC7 ADC7 AC7 AC0OUT

ADCA

NEG

ADCA

GAINNEG

ACA

POS

ACA

NEG

ACA

OUT

REFA

Table 32-2. Port B - alternate functions.

PORT B PIN # INTERRUPT ADCA

POS

PB0 4 SYNC ADC8 AREF

DACB REFB

PB1 5 SYNC ADC9

PB2 6 SYNC/ASYNC ADC10 DAC0

PB3 7 SYNC ADC11 DAC1

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 32-3. Port C - alternate functions.

PORT C PIN # INTERRUPT TCC0

(1)(2)

AWEXC TCC1

USART

(3)

SPIC

(4)

TWIC CLOCKOUT

GND 8

VCC 9

PC0 10 SYNC OC0A OC0ALS SDA

PC1 11 SYNC OC0B OC0AHS XCK0 SCL

PC2 12

SYNC/ASYN

OC0C OC0BLS RXD0

PC3 13 SYNC OC0D OC0BHS TXD0

PC4 14 SYNC OC0CLS OC1A SS

PC5 15 SYNC OC0CHS OC1B XCK1 MOSI

PC6 16 SYNC OC0DLS RXD1 MISO clk

PC7 17 SYNC OC0DHS TXD1 SCK clk

Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port

2. If TC0 is configured as TC2 all eight pins can be used for PWM output.

3. Pin mapping of all USART0 can optionally be moved to high nibble of port.

4. Pins MOSI and SCK for all SPI can optionally be swapped.

5. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.

6. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.

RTC

PER

(5)

EVENTOUT

EVOUT

(6)

Table 32-4. Port D - alternate functions.

PORT D PIN # INTERRUPT TCD0 TCD1 USB USARTD0 USARTD1 SPID CLOCKOUT EVENTOUT

GND 18

VCC 19

PD0 20 SYNC OC0A

PD1 21 SYNC OC0B XCK0

PD2 22 SYNC/ASYNC OC0C RXD0

PD3 23 SYNC OC0D TXD0

PD4 24 SYNC OC1A SS

PD5 25 SYNC OC1B XCK1 MOSI

PD6 26 SYNC D- RXD1 MISO

PD7 27 SYNC D+ TXD1 SCK clk

PER

EVOUT

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 32-5. Port E - alternate functions.

PORT E PIN # INTERRUPT TCE0 USARTE0 TWIE

PE0 28 SYNC OC0A SDA

PE1 29 SYNC OC0B XCK0 SCL

GND 30

VCC 31

PE2 32 SYNC/ASYNC OC0C RXD0

PE3 33 SYNC OC0D TXD0

Table 32-6. Port R - alternate functions.

PORT R PIN # INTERRUPT PDI XTAL TOSC

PDI 34 PDI_DATA

RESET 35 PDI_CLOCK

PRO 36 SYNC XTAL2 TOSC2

PR1 37 SYNC XTAL1 TOSC1

Note: 1. TOSC pins can optionally be moved to PE2/PE3.

(1)

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

33. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A4U. For complete register description and summary for each peripheral module, refer to the XMEGA AU manual.

Table 33-1. Peripheral module address map.

Base address Name Description

0x0000 GPIO General Purpose IO Registers

0x0010 VPORT0 Virtual Port 0

0x0014 VPORT1 Virtual Port 1

0x0018 VPORT2 Virtual Port 2

0x001C VPORT3 Virtual Port 2

0x0030 CPU CPU

0x0040 CLK Clock Control

0x0048 SLEEP Sleep Controller

0x0050 OSC Oscillator Control

0x0060 DFLLRC32M DFLL for the 32MHz Internal RC Oscillator

0x0068 DFLLRC2M DFLL for the 2MHz RC Oscillator

0x0070 PR Power Reduction

0x0078 RST Reset Controller

0x0080 WDT Watch-Dog Timer

0x0090 MCU MCU Control

0x00A0 PMIC Programmable MUltilevel Interrupt Controller

0x00B0 PORTCFG Port Configuration

0x00C0 AES AES Module

0x00D0 CRC CRC Module

0x0100 DMA DMA Module

0x0180 EVSYS Event System

0x01C0 NVM Non Volatile Memory (NVM) Controller

0x0200 ADCA Analog to Digital Converter on port A

0x0380 ACA Analog Comparator pair on port A

0x0400 RTC Real Time Counter

0x0480 TWIC Two Wire Interface on port C

0x04A0 TWIE Two Wire Interface on port E

0x04C0 USB Universal Serial Bus Interface

0x0600 PORTA Port A

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Base address Name Description

0x0620 PORTB Port B

0x0640 PORTC Port C

0x0660 PORTD Port D

0x0680 PORTE Port E

0x07E0 PORTR Port R

0x0800 TCC0 Timer/Counter 0 on port C

0x0840 TCC1 Timer/Counter 1 on port C

0x0880 AWEXC Advanced Waveform Extension on port C

0x0890 HIRESC High Resolution Extension on port C

0x08A0 USARTC0 USART 0 on port C

0x08B0 USARTC1 USART 1 on port C

0x08C0 SPIC Serial Peripheral Interface on port C

0x08F8 IRCOM Infrared Communication Module

0x0900 TCD0 Timer/Counter 0 on port D

0x0940 TCD1 Timer/Counter 1 on port D

0x0990 HIRESD High Resolution Extension on port D

0x09A0 USARTD0 USART 0 on port D

0x09B0 USARTD1 USART 1 on port D

0x09C0 SPID Serial Peripheral Interface on port D

0x0A00 TCE0 Timer/Counter 0 on port E

0x0A80 AWEXE Advanced Waveform Extensionon port E

0x0A90 HIRESE High Resolution Extension on port E

0x0AA0 USARTE0 USART 0 on port E

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

34. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

Arithmetic and Logic Instructions

ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1

ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1

ADIW Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2

SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1

SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1

SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1

SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1

SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1

ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1

OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1

ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1

EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1

COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1

NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1

INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1

DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1

SER Rd Set Register Rd ← $FF None 1

MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2

MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2

MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2

FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2

FMULS Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2

FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2

DES K Data Encryption if (H = 0) then R15:R0

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC(15:0)

EIJMP Extended Indirect Jump to (Z) PC(15:0)

JMP k Jump PC ← k None 3

RCALL k Relative Call Subroutine PC ← PC + k + 1 None 2 / 3

else if (H = 1) then R15:R0←←

Branch instructions

PC(21:16)←←Z,0

PC(21:16)←←Z,EIND

Encrypt(R15:R0, K) Decrypt(R15:R0, K)

None 2

1/2

(1)

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Mnemonics Operands Description Operation Flags #Clocks

ICALL Indirect Call to (Z) PC(15:0)

EICALL Extended Indirect Call to (Z) PC(15:0)

PC(21:16)←←Z,0

PC(21:16)←←Z,EIND

None 2 / 3

None 3

CALL k call Subroutine PC ← k None 3 / 4

RET Subroutine Return PC ← STACK None 4 / 5

RETI Interrupt Return PC ← STACK I 4 / 5

(1)

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None 2 / 3 / 4

SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None 2 / 3 / 4

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1 / 2

Data transfer instructions

MOV Rd, Rr Copy Register Rd ← Rr None 1

MOVW Rd, Rr Copy Register Pair Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← K None 1

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Mnemonics Operands Description Operation Flags #Clocks

LDS Rd, k Load Direct from data space Rd ← (k) None 2

LD Rd, X Load Indirect Rd ← (X) None 1

LD Rd, X+ Load Indirect and Post-Increment RdX←←(X)

LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1,

Rd ← (X)←←

X + 1

X - 1 (X)

None 1

None 2

LD Rd, Y Load Indirect Rd ← (Y) ← (Y) None 1

LD Rd, Y+ Load Indirect and Post-Increment RdY←←(Y)

LD Rd, -Y Load Indirect and Pre-Decrement YRd←←Y - 1

Y + 1

(Y)

None 1

None 2

LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 1

LD Rd, Z+ Load Indirect and Post-Increment RdZ←←(Z),

LD Rd, -Z Load Indirect and Pre-Decrement ZRd←←Z - 1,

Z+1

(Z)

None 1

None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

STS k, Rr Store Direct to Data Space (k) ← Rd None 2

ST X, Rr Store Indirect (X) ← Rr None 1

ST X+, Rr Store Indirect and Post-Increment (X)X←←Rr,

ST -X, Rr Store Indirect and Pre-Decrement X

(X)←←

X + 1

X - 1, Rr

None 1

None 2

ST Y, Rr Store Indirect (Y) ← Rr None 1

ST Y+, Rr Store Indirect and Post-Increment (Y)Y←←Rr,

ST -Y, Rr Store Indirect and Pre-Decrement Y

(Y)←←

Y + 1

Y - 1, Rr

None 1

None 2

STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 1

ST Z+, Rr Store Indirect and Post-Increment (Z)Z←←Rr

Z + 1

None 1

ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z - 1 None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

(1)(2)

(1)

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Increment RdZ←←(Z),

Z + 1

None 3

ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3

ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3

ELPM Rd, Z+ Extended Load Program Memory and Post-

Increment

RdZ←←(RAMPZ:Z),

Z + 1

None 3

SPM Store Program Memory (RAMPZ:Z) ← R1:R0 None -

SPM Z+ Store Program Memory and Post-Increment

by 2

(RAMPZ:Z)Z←←R1:R0,

Z + 2

None -

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Mnemonics Operands Description Operation Flags #Clocks

IN Rd, A In From I/O Location Rd ← I/O(A) None 1

OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 1

POP Rd Pop Register from Stack Rd ← STACK None 2

XCH Z, Rd Exchange RAM location Tem p

LAS Z, Rd Load and Set RAM location Te mp

LAC Z, Rd Load and Clear RAM location Te mp

LAT Z, Rd Load and Toggle RAM location Te mp

Rd (Z)

← ← ←

Rd, (Z), Te mp

Rd, (Z), Te m p v (Z )

Rd, (Z), ($FFh – Rd)

Rd, (Z), Te mp ⊕ (Z)

None 2

z (Z)

None 2

(1)

Bit and bit-test instructions

LSL Rd Logical Shift Left Rd(n+1)

LSR Rd Logical Shift Right Rd(n)

ROL Rd Rotate Left Through Carry Rd(0)

ROR Rd Rotate Right Through Carry Rd(7)

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1

CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1 C 1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1 N 1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1 Z 1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1 I 1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1 S 1

CLS Clear Signed Test Flag S ← 0 S 1

Rd(n+1)

Rd(0)

Rd(7)

Rd(n)

←

Rd(n),

← ←

← ← ←

0, Rd(7)

Rd(n+1), 0, Rd(0)

C, Rd(n), Rd(7)

C, Rd(n+1), Rd(0)

Z,C,N,V,H 1

Z,C,N,V 1

Z,C,N,V,H 1

Z,C,N,V 1

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Mnemonics Operands Description Operation Flags #Clocks

SEV Set Two’s Complement Overflow V ← 1 V 1

CLV Clear Two’s Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1 T 1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1 H 1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

MCU control instructions

BREAK Break (See specific descr. for BREAK) None 1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep) None 1

WDR Watchdog Reset (see specific descr. for WDR) None 1

Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the

external RAM interface.

2. One extra cycle must be added when accessing Internal SRAM.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

35. Packaging information

35.1 44A

PIN 1 IDENTIFIER

PIN 1

E1 E

0°~7°

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10mm maximum.

TITLE

2325 Orchard Parkway

San Jose, CA 95131

44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,

0.8 mm lead pitch, thin profile plastic quad flat package (TQFP)

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 11.75 12.00 12.25

D1 9.90 10.00 10.10 Note 2

E 11.75 12.00 12.25

E1 9.90 10.00 10.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

NOM

MAX

NOTE

2010-10-20

DRAWING NO.

44A

REV.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

35.2 PW

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

35.3 44M1

Marked Pin# 1 ID

SEATING PLANE

TOP VIEW

Pin #1 Corner

SIDE VIEW

1 2 3

BOTTOM VIEW

Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.

TITLE

Package Drawing Contact: packagedrawings@atmel.com

44M1, 44-pad, 7 x 7 x 1.0mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (VQFN)

Option A

Option B

Option C

Pin #1 Triangle

Pin #1 Chamfer (C 0.30)

Pin #1 Notch (0.20 R)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

A 0.80 0.90 1.00

A1 – 0.02 0.05

A3 0.20 REF

b 0.18 0.23 0.30

6.90 7.00 7.10

D2 5.00 5.20 5.40

6.90 7.00 7.10

E2 5.00 5.20 5.40

e 0.50 BSC

L 0.59 0.64 0.69

K 0.20 0.26 0.41

DRAWING NO.GPC

MAX

NOTE

9/26/08

44M1ZWS H

REV.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

35.4 49C2

TITLE

DRAWING NO. GPC

REV.

Package Drawing Contact: packagedrawings@atmel.com

49C2 CBD A

49C2, 49-ball (7 x 7 array), 0.65mm pitch,

5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA)

3/14/08

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

A – – 1.00

A1 0.20 – –

A2 0.65 – –

D 4.90 5.00 5.10

D1 3.90 BSC

E 4.90 5.00 5.10

E1 3.90 BSC

b 0.30 0.35 0.40

e 0.65 BSC

TOP VIEW

SIDE VIEW

A1 BALL ID

1 2 3 4 5 6

0.10

49 - Ø0.35 ±0.05

A1 BALL CORNER

BOTTOM VIEW

b e

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36. Electrical Characteristics

All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given.

36.1 ATxmega16A4U

36.1.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 36-1 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 36-1. Absolute maximum ratings.

Symbol Parameter Condition Min. Typ. Max. Units

VCC

GND

Power supply voltage -0.3 4 V

Current into a VCC pin 200

Current out of a Gnd pin 200

Pin voltage with respect to Gnd and V

I/O pin sink/source current -25 25 mA

Storage temperature -65 150

Junction temperature 150

36.1.2 General Operating Ratings

The device must operate within the ratings listed in Table 36-2 in order for all other electrical characteristics and typical characteristics of the device to be valid.

Table 36-2. General operating conditions.

Symbol Parameter Condition Min. Typ. Max. Units

Power supply voltage 1.60 3.6

Analog supply voltage 1.60 3.6

Temperature range -40 85

Junction temperature -40 105

-0.5 VCC+0.5 V

°C

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 36-3. Operating voltage and frequency.

1.8

MHz

2.7

3.6

1.6

Safe Operating Area

Symbol Parameter Condition Min. Typ. Max. Units

VCC = 1.6V 0 12

Clk

CPU

CPU clock frequency

VCC = 2.7V 0 32

MHz

VCC = 3.6V 0 32

The maximum CPU clock frequency depends on VCC. As shown in Figure 36-1 the Frequency vs. VCC curve is linear

VCC = 1.8V 0 12

between 1.8V < V

<2.7V.

Figure 36-1. Maximum Frequency vs. VCC.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.3 Current consumption

Table 36-4. Current consumption for Active mode and sleep modes.

Symbol Parameter Condition Min. Typ . Max. Units

32kHz, Ext. Clk

VCC = 1.8V 40

VCC = 3.0V 80

µA

Active power consumption

1MHz, Ext. Clk

VCC = 1.8V 230

(1)

VCC = 3.0V 480

VCC = 1.8V 430 600

2MHz, Ext. Clk

0.9 1.4

VCC = 3.0V

32MHz, Ext. Clk 9.6 12

VCC = 1.8V 2.4

32kHz, Ext. Clk

VCC = 3.0V 3.9

VCC = 1.8V 62

Idle power consumption

1MHz, Ext. Clk

(1)

VCC = 3.0V 118

µA

VCC = 1.8V 125 225

2MHz, Ext. Clk

240 350

32MHz, Ext. Clk 3.8 5.5 mA

T=25°C

VCC = 3.0V

0.1 1.0

VCC = 3.0V

T=85°C 1.2 4.5

Power-down power consumption

WDT and Sampled BOD enabled, T=25°C

1.3 3.0

VCC = 3.0V

WDT and Sampled BOD enabled, T = 85°C

2.4 6.0

Power-save power consumption

(2)

Reset power consumption

Notes: 1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

RTC from low power 32.768kHz TOSC, T = 25°C

Current through RESET pin substracted

VCC = 1.8V 1.2

VCC = 3.0V 1.3

VCC = 1.8V 0.6 2.0

VCC = 3.0V 0.7 2.0

VCC = 1.8V 0.8 3.0

VCC = 3.0V 1.0 3.0

VCC = 3.0V 320

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

µA

Table 36-5. Current consumption for modules and peripherals.

Symbol Parameter Condition

ULP oscillator 1.0

32.768kHz int. oscillator 27

2MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference 115

32MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference 460

PLL

20x multiplication factor,

32MHz int. osc. DIV4 as reference

Watchdog timer 1.0

Continuous mode 138

BOD

Sampled mode, includes ULP oscillator 1.2

Internal 1.0V reference 100

Temperature sensor 95

ADC

250ksps

= Ext ref

REF

(1)

Min. Typ . Max. Units

270

µA

220

3.0

CURRLIMIT = LOW 2.6

CURRLIMIT = MEDIUM 2.1

CURRLIMIT = HIGH 1.6

DAC

250ksps V

= Ext ref

REF

No load

Normal mode 1.9

Low Power mode 1.1

High speed mode 330

Low power mode 130

DMA 615kbps between I/O registers and SRAM 108

Timer/counter 16

USART Rx and Tx enabled, 9600 BAUD 2.5

Flash memory and EEPROM programming 4.0 8.0 mA

Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC= 3.0V, Clk

without prescaling, T = 25°C unless other conditions are given.

= 1MHz external clock

SYS

µA

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.4 Wake-up time from sleep modes

Wakeup request

Clock output

Wakeup time

Table 36-6. Device wake-up time from sleep modes with various system clock sources.

Symbol Parameter Condition Min. Typ.

External 2MHz clock 2.0

Wake-up time from idle, standby, and extended standby mode

wakeup

Wake-up time from power-save and power-down mode

Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and modules start

execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 36-2. Wake-up time definition.

32.768kHz internal oscillator 120

2MHz internal oscillator 2.0

32MHz internal oscillator 0.2

External 2MHz clock 4.5

32.768kHz internal oscillator 320

2MHz internal oscillator 9.0

32MHz internal oscillator 5.0

(1)

Max. Units

µs

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.5 I/O Pin Characteristics

The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification.

Table 36-7. I/O pin characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

(1)

I/O pin source/sink current -20 20 mA

(2)

VCC = 2.7 - 3.6V 2.0 VCC+0.3

High level input voltage

Low level input voltage

High level output voltage

VCC = 2.0 - 2.7V 0.7*V

VCC = 1.6 - 2.0V 0.7*V

VCC+0.3

VCC = 2.7- 3.6V -0.3 0.3*V

VCC = 2.0 - 2.7V -0.3 0.3*V

VCC = 1.6 - 2.0V -0.3 0.3*V

VCC = 3.0 - 3.6V IOH = -2mA 2.4 0.94*V

IOH = -1mA 2.0 0.96*V

VCC = 2.3 - 2.7V

IOH = -2mA 1.7 0.92*V

VCC = 3.3V IOH = -8mA 2.6 2.9

VCC = 3.0V IOH = -6mA 2.1 2.6

VCC = 1.8V IOH = -2mA 1.4 1.6

VCC = 3.0 - 3.6V IOL = 2mA 0.05*V

IOL = 1mA 0.03*V

VCC = 2.3 - 2.7V

IOL = 2mA 0.06*V

Low level output voltage

VCC = 3.3V IOL = 15mA 0.4 0.76

0.4

0.7

VCC = 3.0V IOL = 10mA 0.3 0.64

VCC = 1.8V IOL = 5mA 0.2 0.46

Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.

Input leakage current T = 25°C <0.001 0.1 µA

Pull/buss keeper resistor 24 kΩ

Rise time No load

The sum of all I The sum of all I The sum of all I

2. The sum of all I The sum of all I The sum of all I The sum of all I

for PORTC must not exceed 200mA.

for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

for PORTA and PORTB must not exceed 100mA.

for PORTC must not not exceed 200mA.

for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

4.0

slew rate limitation 7.0

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.6 ADC characteristics

Table 36-8. Power supply, reference and input range.

Symbol Parameter Condition Min. Ty p . Max. Units

REF

sample

AREF

Analog supply voltage VCC- 0.3 VCC+ 0.3

Reference voltage 1.0 AV

- 0.6

Input resistance Switched 4.0 kΩ

Input capacitance Switched 4.4 pF

Reference input resistance (leakage only) >10 MΩ

Reference input capacitance Static load 7.0 pF

Input range -0.1 AV

REF

Conversion range Single ended unsigned mode, Vinp -ΔV V

REF

+0.1

REF

-ΔV

ΔV Fixed offset voltage 190 LSB

Table 36-9. Clock and timing.

Symbol Parameter Condition Min. Ty p . Max. Units

Clk

ADC

ADC Clock frequency

Maximum is 1/4 of peripheral clock frequency

100 2000

kHz

Measuring internal signals 100 125

VConversion range Differential mode, Vinp - Vinn -V

ADC

Current limitation (CURRLIMIT) off 100 2000

CURRLIMIT = LOW 100 1500

Sample rate

CURRLIMIT = MEDIUM 100 1000

CURRLIMIT = HIGH 100 500

Sampling time 1/2 Clk

Conversion time (latency)

(RES+2)/2+(GAIN !=0) RES (Resolution) = 8 or 12

cycle 0.25 5 µs

ADC

5 8

Start-up time ADC clock cycles 12 24

After changing reference or input mode 7 7

ADC settling time

After ADC flush 1 1

ksps

Clk

ADC

cycles

Clk

ADC

cycles

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 36-10. Accuracy characteristics.

Symbol Parameter Condition

(2)

Min. Ty p. Max. Units

RES Resolution Programmable to 8 or 12 bit 8 12 12 Bits

INL

DNL

500ksps

VCC-1.0V < V

(1)

Integral non-linearity

VCC-1.0V < V

2000ksps

(1)

Differential non-linearity guaranteed monotonic <±0.8 <±1.0

< VCC-0.6V ±1.2 ±2.0

REF

All V

REF

< VCC-0.6V ±1.0 ±2.0

REF

All V

REF

±1.5 ±3.0

-1.0 mV

Offset error

Temperature drift <0.01 mV/K

Operating voltage drift <0.6 mV/V

External reference -1.0

Differential mode

AVCC/1.6 10

AVCC/2.0 8.0

Gain error

Bandgap ±5.0

Temperature drift <0.02 mV/K

Operating voltage drift <0.5 mV/V

lsb

Noise

Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V

Differential mode, shorted input 2msps, V

= 3.6V, Clk

= 16MHz

PER

REF

0.4

is used.

Table 36-11. Gain stage characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

sample

Input resistance Switched in normal mode 4.0 kΩ

Input capacitance Switched in normal mode 4.4 pF

Signal range Gain stage output 0 VCC- 0.6 V

Propagation delay ADC conversion rate 1.0

Sample rate Same as ADC 100 1000 kHz

INL

(1)

Integral non-linearity 500ksps

All gain settings

±1.5 ±4 lsb

mV rms

Clk

ADC

cycles

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Symbol Parameter Condition Min. Typ. Max. Units

1x gain, normal mode -0.8

Gain error

64x gain, normal mode -3.5

1x gain, normal mode -2

Offset error, input referred

64x gain, normal mode -4

Noise

1x gain, normal mode

= 3.6V

8x gain, normal mode 1.5

Ext. V

REF

0.5

64x gain, normal mode 11

Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

36.1.7 DAC Characteristics

Table 36-12. Power supply, reference and output range.

Symbol Parameter Condition Min. Typ. Max. Units

channel

REF

Analog supply voltage

External reference voltage 1.0 VCC- 0.6

DC output impedance 50 Ω

Linear output voltage range 0.15 AVCC-0.15 V

VCC-

0.3

VCC+ 0.3

%8x gain, normal mode -2.5

mV8x gain, normal mode -5

rms

AREF

Reference input resistance >10 MΩ

CAREF Reference input capacitance Static load 7 pF

Minimum resistance load 1.0 kΩ

100 pF

Maximum capacitance load

1000Ω serial resistance 1.0 nF

Operating within accuracy specification AVCC/1000

Output sink/source

Safe operation 10

Table 36-13. Clock and timing.

Symbol Parameter Condition Min. Typ . Max. Units

Fclk Conversion rate Fout=Fclk/4, Cload=100pF, maximum step size 0 1000 ksps

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 36-14. Accuracy characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

RES Input resolution 12 Bits

= 1.6V ±2.0 ±3

= 3.6V ±1.5 ±2.5

= 1.6V ±2.0 ±4

= 3.6V ±1.5 ±4

= 1.6V ±5.0

= 3.6V ±5.0

= 1.6V ±1.5 3.0

= 3.6V ±0.6 1.5

= 1.6V ±1.0 3.5

= 3.6V ±0.6 1.5

= 1.6V ±4.5

= 3.6V ±4.5

lsb

INL

DNL

(1)

Integral non-linearity

(1)

Differential non-linearity

REF

= Ext 1.0V

=AV

=INT1V

=Ext 1.0V

=AV

=INT1V

Gain error After calibration <4.0

Gain calibration step size 4.0

Gain calibration drift V

= Ext 1.0V <0.2 mV/K

REF

Offset error After calibration <1.0 lsb

Offset calibration step size 1.0

Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.8 Analog Comparator Characteristics

Table 36-15. Analog Comparator characteristics.

Symbol Parameter Condition Min. Typ . Max. Units

delay

off

hys1

hys2

hys3

Input offset voltage <±10 mV

Input leakage current <1.0 nA

Input voltage range -0.1 AV

AC startup time 100 µs

Hysteresis, none 0

mode = High Speed (HS) 13

Hysteresis, small

mode = Low Power (LP) 30

mode = HS 30

Hysteresis, large

mode = LP 60

VCC = 3.0V, T= 85°C mode = HS 30 90

mode = HS 30

Propagation delay

VCC = 3.0V, T= 85°C mode = LP 130 500

mode = LP 130

64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb

36.1.9 Bandgap and Internal 1.0V Reference Characteristics

Table 36-16. Bandgap and Internal 1.0V reference characteristics.

Symbol Parameter Condition Min. Typ . Max. Units

Startup time

As reference for ADC or DAC 1 Clk

As input voltage to ADC and AC 1.5

Bandgap voltage 1.1

INT1V Internal 1.00V reference T= 85°C, after calibration 0.99 1.0 1.01

Variation over voltage and temperature Relative to T= 85°C, VCC = 3.0V ±1.5 %

PER

+ 2.5µs

µs

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.10 Brownout Detection Characteristics

Table 36-17. Brownout detection characteristics.

Symbol Parameter Condition Min. Typ . Max. Units

BOD level 0 falling V

BOD level 1 falling V

BOD level 2 falling V

BOD level 3 falling V

BOT

BOD level 4 falling V

BOD level 5 falling V

BOD level 6 falling V

BOD level 7 falling V

1.60 1.62 1.72

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Continuous mode 0.4

BOD

HYST

Detection time

Sampled mode 1000

Hysteresis 1.2 %

36.1.11 External Reset Characteristics

Table 36-18. External reset characteristics.

Symbol Parameter Condition Min. Ty p. Max. Units

µs

EXT

RST

Minimum reset pulse width 95 1000 ns

Reset threshold voltage (VIH)

VCC = 2.7 - 3.6V 0.60×V

VCC = 1.6 - 2.7V 0.60×V

VCC = 2.7 - 3.6V 0.50×V

Reset threshold voltage (VIL)

VCC = 1.6 - 2.7V 0.40×V

Reset pin Pull-up Resistor 25 kΩ

36.1.12 Power-on Reset Characteristics

Table 36-19. Power-on reset characteristics.

Symbol Parameter Condition Min. Ty p. Max. Units

(1)

POT-

POT+

Note: 1. V

POR threshold voltage falling V

POR threshold voltage rising V

values are only valid when BOD is disabled. When BOD is enabled V

POT-

VCC falls faster than 1V/ms 0.4 1.0

= V

POT+

POT-

1.3 1.59

VVCC falls at 1V/ms or slower 0.8 1.0

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.13 Flash and EEPROM Memory Characteristics

Table 36-20. Endurance and data retention.

Symbol Parameter Condition Min. Typ. Max. Units

Write/Erase cycles

25°C 10K

85°C 10K

Flash

25°C 100

Data retention

55°C 25

25°C 80K

Write/Erase cycles

85°C 30K

EEPROM

25°C 100

Data retention

55°C 25

Table 36-21. Programming time.

Symbol Parameter Condition Min. Ty p .

Chip Erase 16KB Flash, EEPROM

(2)

and SRAM Erase 45

Page erase 4

Flash

Page write 4

Atomic page erase and write 8

Cycle

Yea r

Cycle

Yea r

(1)

Max. Units

Page erase 4

EEPROM

Page write 4

Atomic page erase and write 8

Notes: 1. Programming is timed from the 2MHz internal oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

36.1.14 Clock and Oscillator Characteristics

36.1.14.1Calibrated 32.768kHz Internal Oscillator characteristics

Table 36-22. 32.768kHz internal oscillator characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

Frequency 32.768 kHz

Factory calibration accuracy T = 85°C, V

= 3.0V -0.5 0.5

User calibration accuracy -0.5 0.5

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.14.2Calibrated 2MHz RC Internal Oscillator characteristics

Table 36-23. 2MHz internal oscillator characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

Frequency range

Factory calibrated frequency 2.0

Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5

DFLL calibration stepsize 0.21

DFLL can tune to this frequency over voltage and temperature

1.8 2.2 MHz

36.1.14.3Calibrated and tunable 32MHz internal oscillator characteristics

Table 36-24. 32MHz internal oscillator characteristics.

Symbol Parameter Condition Min. Typ . Max. Units

Frequency range

Factory calibrated frequency 32

Factory calibration accuracy T = 85°C, VCC= 3.0V -1.5 1.5

DFLL calibration step size 0.22

DFLL can tune to this frequency over voltage and temperature

30 55

MHz

%User calibration accuracy -0.2 0.2

36.1.14.432kHz Internal ULP Oscillator characteristics

Table 36-25. 32kHz internal ULP oscillator characteristics.

Symbol Parameter Condition Min. Typ . Max. Units

Output frequency 32 kHz

Accuracy -30 30 %

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.14.5Internal Phase Locked Loop (PLL) characteristics

IL1

IH1

Table 36-26. Internal PLL characteristics.

Symbo

Parameter Condition Min. Ty p. Max. Units

OUT

Input frequency Output frequency must be within f

Output frequency

(1)

VCC= 1.6 - 1.8V 20 48

VCC= 2.7 - 3.6V 20 128

OUT

0.4 64

MHz

Start-up time 25

µs

Re-lock time 25

Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

36.1.14.6External clock characteristics

Figure 36-3. External clock drive waveform

Table 36-27. External clock

(1)

for system clock.

Symbol Parameter Condition Min. Typ. Max. Units

1/t

Clock frequency

(2)

VCC = 1.6 - 1.8V 0 90

VCC = 2.7 - 3.6V 0 142

VCC = 1.6 - 1.8V 11

Clock period

VCC = 2.7 - 3.6V 7

VCC = 1.6 - 1.8V 4.5

CH/LH

IL/IH

Δt

Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

Clock high/low time

VCC = 2.7 - 3.6V 2.4

Low/high level input voltage See Table 36-6 on page 75 V

Change in period from one clock cycle to the next 10 %

2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

MHz

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.14.7External 16MHz crystal oscillator and XOSC characteristic

Table 36-28. External 16MHz crystal oscillator and XOSC characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

Cycle to cycle jitter

Long term jitter

Frequency error

Duty cycle

XOSCPWR=0

FRQRANGE=0 <10

FRQRANGE=1, 2, or 3 <1.0

XOSCPWR=1 <1.0

FRQRANGE=0 <6.0

XOSCPWR=0

FRQRANGE=1, 2, or 3 <0.5

XOSCPWR=1 <0.5

FRQRANGE=0 <0.1

XOSCPWR=0

FRQRANGE=1 <0.05

FRQRANGE=2 or 3 <0.005

XOSCPWR=1 <0.005

FRQRANGE=0 40

XOSCPWR=0

FRQRANGE=1 42

FRQRANGE=2 or 3 45

XOSCPWR=1 48

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Symbol Parameter Condition Min. Typ. Max. Units

XOSCPWR=0, FRQRANGE=0

0.4MHz resonator, CL=100pF

1MHz crystal, CL=20pF 8.7k

2.4k

2MHz crystal, CL=20pF 2.1k

XOSCPWR=0, FRQRANGE=1, CL=20pF

XOSCPWR=0, FRQRANGE=2, CL=20pF

XOSCPWR=0,

Negative impedance

(1)

FRQRANGE=3, CL=20pF

XOSCPWR=1, FRQRANGE=0, CL=20pF

2MHz crystal 4.2k

8MHz crystal 250

9MHz crystal 195

8MHz crystal 360

9MHz crystal 285

12MHz crystal 155

9MHz crystal 365

12MHz crystal 200

16MHz crystal 105

9MHz crystal 435

12MHz crystal 235

16MHz crystal 125

XOSCPWR=1, FRQRANGE=1, CL=20pF

XOSCPWR=1,

9MHz crystal 495

12MHz crystal 270

16MHz crystal 145

12MHz crystal 305 FRQRANGE=2, CL=20pF

XOSCPWR=1,

16MHz crystal 160

12MHz crystal 380 FRQRANGE=3, CL=20pF

XTAL1

XTAL2

LOAD

Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.

Parasitic capacitance XTAL1 pin

Parasitic capacitance XTAL2 pin

Parasitic capacitance load 3.07

16MHz crystal 205

5.4

7.1

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.14.8External 32.768kHz crystal oscillator and TOSC characteristics

2CSOT

CSOT

Device internal

External

32.768kHz crystal

Table 36-29. External 32.768kHz crystal oscillator and TOSC characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

ESR/R1

TOSC1

TOSC2

Recommended crystal equivalent series resistance (ESR)

Parasitic capacitance TOSC1 pin

Parasitic capacitance TOSC2 pin

Recommended safety factor

Note: 1. See Figure 36-4 for definition.

Figure 36-4. TOSC input capacitance.

Crystal load capacitance 6.5pF 60

Crystal load capacitance 9.0pF 35

5.4

Alternate TOSC location 4.0

7.1

Alternate TOSC location 4.0

capacitance load matched to crystal specification

kΩ

The parasitic capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without external capacitors.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.1.15 SPI Characteristics

MSB LSB

MOS

MIStMIH

SCKW

SCK

MOH

SCKF

SCKR

SCKW

MOSI

(Data Output)

MISO

(Data Input)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

MSB LSB

SIS

SIH

SSCKW

SSCK

SSH

SOSSH

SCKR

SCKF

SOS

SSS

SOSSS

MISO

(Data Output)

MOSI

(Data Input)

SCK

(CPOL = 1)

SCK

(CPOL = 0)

Figure 36-5. SPI timing requirements in master mode.

Figure 36-6. SPI timing requirements in slave mode.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 36-30. SPI timing characteristics and requirements.

HD;STA

SDA

SCL

LOW

HIGH

SU;STA

BUF

HD;DAT

SU;DAT

SU;STO

Symbol Parameter Condition Min. Typ. Max. Units

SCK

SCKW

SCKR

SCKF

MIS

MIH

MOS

MOH

SSCK

SSCKW

SSCKR

SSCKF

SIS

SIH

SSS

SSH

SOS

SOH

SOSS

SOSH

SCK period Master

(See Table 21-4 in

XMEGA AU Manual)

SCK high/low width Master 0.5*SCK

SCK rise time Master 2.7

SCK fall time Master 2.7

MISO setup to SCK Master 10

MISO hold after SCK Master 10

MOSI setup SCK Master 0.5*SCK

MOSI hold after SCK Master 1

Slave SCK Period Slave 4×t Clk

SCK high/low width Slave 2×t Clk

PER

SCK rise time Slave 1600

SCK fall time Slave 1600

MOSI setup to SCK Slave 3

MOSI hold after SCK Slave tClk

PER

SS setup to SCK Slave 21

SS hold after SCK Slave 20

MISO setup SCK Slave 8

MISO hold after SCK Slave 13

MISO setup after SS low Slave 11

MISO hold after SS high Slave 8

36.1.16 Two-Wire Interface Characteristics

Table 36-31 on page 91 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel

AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7 on page 90.

Figure 36-7. Two-wire interface bus timing.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 36-31. Two-wire interface characteristics.

0.4V–

3mA

--------------------------- -

100ns

-------------- -

300ns

-------------- -

Symbol Parameter Condition Min. Typ. Max. Units

hys

SCL

HD;STA

LOW

HIGH

SU;STA

HD;DAT

SU;DAT

SU;STO

BUF

Notes: 1. Required only for f

Input high voltage 0.7*V

Input low voltage 0.5 0.3*V

Hysteresis of Schmitt trigger inputs 0.05*V

Output low voltage 3mA, sink current 0 0.4

Rise time for both SDA and SCL 20+0.1C

Output fall time from V

Spikes suppressed by input filter 0 50

Input current for each I/O Pin 0.1VCC < VI < 0.9V

Capacitance for each I/O Pin 10 pF

SCL clock frequency f

Value of pull-up resistor

Hold time (repeated) START condition

Low period of SCL clock

High period of SCL clock

Set-up time for a repeated START condition

Data hold time

Data setup time

Setup time for STOP condition

Bus free time between a STOP and START condition

= Capacitance of one bus line in pF.

2. C

3. f

= Peripheral clock frequency.

PER

> 100kHz.

SCL

IHmin

to V

ILmax

(1)

(1)(2)

10pF < Cb < 400pF

(3)

>max(10f

PER

≤ 100kHz

SCL

> 100kHz

SCL

≤ 100kHz 4.0

SCL

> 100kHz 0.6

SCL

≤ 100kHz 4.7

SCL

> 100kHz 1.3

SCL

≤ 100kHz 4.0

SCL

> 100kHz 0.6

SCL

≤ 100kHz 4.7

SCL

> 100kHz 0.6

SCL

≤ 100kHz 0 3.45

SCL

> 100kHz 0 0.9

SCL

≤ 100kHz 250

SCL

> 100kHz 100

SCL

≤ 100kHz 4.0

SCL

> 100kHz 0.6

SCL

≤ 100kHz 4.7

SCL

> 100kHz 1.3

SCL

(2)

, 250kHz) 0 400 kHz

SCL

20+0.1C

(1)(2)

-10 10 µA

VCC+0.5

300

250

nst

µs

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.2 ATxmega32A4U

36.2.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 36-32 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Table 36-32. Absolute maximum ratings.

Symbol Parameter Condition Min. Typ. Max. Units

VCC

GND

Power supply voltage -0.3 4 V

Current into a VCC pin 200

Current out of a Gnd pin 200

Pin voltage with respect to Gnd and V

I/O pin sink/source current -25 25 mA

Storage temperature -65 150

Junction temperature 150

36.2.2 General Operating Ratings

The device must operate within the ratings listed in Table 36-33 in order for all other electrical characteristics and typical characteristics of the device to be valid.

Table 36-33. General operating conditions.

Symbol Parameter Condition Min. Typ. Max. Units

Power supply voltage 1.60 3.6

Analog supply voltage 1.60 3.6

Temperature range -40 85

Junction temperature -40 105

-0.5 VCC+0.5 V

°C

Table 36-34. Operating voltage and frequency.

Symbol Parameter Condition Min. Typ. Max. Units

VCC = 1.6V 0 12

VCC = 1.8V 0 12

Clk

CPU

CPU clock frequency

VCC = 2.7V 0 32

VCC = 3.6V 0 32

XMEGA A4U [DATASHEET]

MHz

8387C–AVR–3/12

The maximum CPU clock frequency depends on VCC. As shown in Figure 36-8 the Frequency vs. VCC curve is linear

1.8

MHz

2.7

3.6

1.6

Safe Operating Area

between 1.8V < V

<2.7V.

Figure 36-8. Maximum Frequency vs. VCC.

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.2.3 Current consumption

Table 36-35. Current consumption for Active mode and sleep modes.

Symbol Parameter Condition Min. Typ . Max. Units

32kHz, Ext. Clk

VCC = 1.8V 40

VCC = 3.0V 80

µA

Active power consumption

1MHz, Ext. Clk

VCC = 1.8V 230

(1)

VCC = 3.0V 480

VCC = 1.8V 430 600

2MHz, Ext. Clk

0.9 1.4

VCC = 3.0V

32MHz, Ext. Clk 9.6 12

VCC = 1.8V 2.4

32kHz, Ext. Clk

VCC = 3.0V 3.9

VCC = 1.8V 62

Idle power consumption

1MHz, Ext. Clk

(1)

VCC = 3.0V 118

µA

VCC = 1.8V 125 225

2MHz, Ext. Clk

240 350

32MHz, Ext. Clk 3.8 5.5 mA

T=25°C

VCC = 3.0V

0.1 1.0

VCC = 3.0V

T=85°C 1.2 4.5

Power-down power consumption

WDT and sampled BOD enabled, T=25°C

1.3 3.0

VCC = 3.0V

WDT and sampled BOD enabled, T = 85°C

2.4 6.0

Power-save power consumption

(2)

Reset power consumption

Notes: 1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

RTC from low power 32.768kHz TOSC, T = 25°C

Current through RESET pin substracted

VCC = 1.8V 1.2

VCC = 3.0V 1.3

VCC = 1.8V 0.6 2.0

VCC = 3.0V 0.7 2.0

VCC = 1.8V 0.8 3.0

VCC = 3.0V 1.0 3.0

VCC = 3.0V 320

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

µA

Table 36-36. Current consumption for modules and peripherals.

Symbol Parameter Condition

ULP oscillator 1.0

32.768kHz int. oscillator 27

2MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference 115

32MHz int. oscillator

DFLL enabled with 32.768kHz int. osc. as reference 460

PLL

20x multiplication factor,

32MHz int. osc. DIV4 as reference

Watchdog timer 1.0

Continuous mode 138

BOD

Sampled mode, includes ULP oscillator 1.2

Internal 1.0V reference 100

Temperature sensor 95

ADC

250ksps

= Ext ref

REF

(1)

Min. Typ . Max. Units

270

µA

220

3.0

CURRLIMIT = LOW 2.6

CURRLIMIT = MEDIUM 2.1

CURRLIMIT = HIGH 1.6

DAC

250ksps V

= Ext ref

REF

No load

Normal mode 1.9

Low power mode 1.1

High speed mode 330

Low power mode 130

DMA 615kbps between I/O registers and SRAM 108

Timer/counter 16

USART Rx and Tx enabled, 9600 BAUD 2.5

Flash memory and EEPROM programming 4.0 8.0 mA

Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC= 3.0V, Clk

without prescaling, T = 25°C unless other conditions are given.

= 1MHz external clock

SYS

µA

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.2.4 Wake-up time from sleep modes

Wakeup request

Clock output

Wakeup time

Table 36-37. Device wake-up time from sleep modes with various system clock sources.

Symbol Parameter Condition Min. Typ.

External 2MHz clock 2.0

Wake-up time from idle, standby, and extended standby mode

wakeup

Wake-up time from power-save and power-down mode

Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-9. All peripherals and modules start

execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 36-9. Wake-up time definition.

32.768kHz internal oscillator 120

2MHz internal oscillator 2.0

32MHz internal oscillator 0.2

External 2MHz clock 4.5

32.768kHz internal oscillator 320

2MHz internal oscillator 9.0

32MHz internal oscillator 5.0

(1)

Max. Units

µs

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.2.5 I/O Pin Characteristics

The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification.

Table 36-38. I/O pin characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

(1)

I/O pin source/sink current -20 20 mA

(2)

VCC = 2.7 - 3.6V 2.0 VCC+0.3

High level input voltage

Low level input voltage

High level output voltage

VCC = 2.0 - 2.7V 0.7×V

VCC = 1.6 - 2.0V 0.7×V

VCC+0.3

VCC = 2.7- 3.6V -0.3 0.3*V

VCC = 2.0 - 2.7V -0.3 0.3*V

VCC = 1.6 - 2.0V -0.3 0.3*V

VCC = 3.0 - 3.6V IOH = -2mA 2.4 0.94*V

IOH = -1mA 2.0 0.96*V

VCC = 2.3 - 2.7V

IOH = -2mA 1.7 0.92*V

VCC = 3.3V IOH = -8mA 2.6 2.9

VCC = 3.0V IOH = -6mA 2.1 2.6

VCC = 1.8V IOH = -2mA 1.4 1.6

VCC = 3.0 - 3.6V IOL = 2mA 0.05*V

IOL = 1mA 0.03*V

VCC = 2.3 - 2.7V

IOL = 2mA 0.06*V

Low level output voltage

VCC = 3.3V IOL = 15mA 0.4 0.76

0.4

0.7

VCC = 3.0V IOL = 10mA 0.3 0.64

VCC = 1.8V IOL = 5mA 0.2 0.46

Notes: 1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.

Input leakage current T = 25°C <0.001 0.1 µA

Pull/buss keeper resistor 24 kΩ

Rise time No load

The sum of all I The sum of all I The sum of all I

2. The sum of all I The sum of all I The sum of all I The sum of all I

for PORTC must not exceed 200mA.

for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

for PORTA and PORTB must not exceed 100mA.

for PORTC must not not exceed 200mA.

for PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

for PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

4.0

slew rate limitation 7.0

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

36.2.6 ADC characteristics

Table 36-39. Power supply, reference and input range.

Symbol Parameter Condition Min. Ty p . Max. Units

sample

REF

AREF

Analog supply voltage VCC- 0.3 VCC+ 0.3

Reference voltage 1 AV

- 0.6

Input resistance Switched 4.0 kΩ

Input capacitance Switched 4.4 pF

Reference input resistance (leakage only) >10 MΩ

Reference input capacitance Static load 7 pF

Input range -0.1 AV

REF

Conversion range Single ended unsigned mode, Vinp -ΔV V

REF

+0.1

REF

-ΔV

ΔV Fixed offset voltage 190 LSB

Table 36-40. Clock and timing.

Symbol Parameter Condition Min. Ty p . Max. Units

Clk

ADC

ADC clock frequency

Maximum is 1/4 of peripheral clock frequency

100 2000

kHz

Measuring internal signals 100 125

VConversion range Differential mode, Vinp - Vinn -V

ADC

Current limitation (CURRLIMIT) off 100 2000

CURRLIMIT = LOW 100 1500

Sample rate

CURRLIMIT = MEDIUM 100 1000

CURRLIMIT = HIGH 100 500

Sampling time 1/2 Clk

Conversion time (latency)

(RES+2)/2+(GAIN !=0) RES (Resolution) = 8 or 12

cycle 0.25 5 µs

ADC

5 8

Start-up time ADC clock cycles 12 24

After changing reference or input mode 7 7

ADC settling time

After ADC flush 1 1

ksps

Clk

ADC

cycles

Clk

ADC

cycles

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Table 36-41. Accuracy characteristics.

Symbol Parameter Condition

(2)

Min. Ty p. Max. Units

RES Resolution Programmable to 8 or 12 bit 8 12 12 Bits

INL

DNL

500ksps

VCC-1.0V < V

(1)

Integral non-linearity

VCC-1.0V < V

2000ksps

(1)

Differential non-linearity guaranteed monotonic <±0.8 <±1.0

< VCC-0.6V ±1.2 ±2.0

REF

All V

REF

< VCC-0.6V ±1.0 ±2.0

REF

All V

REF

±1.5 ±3.0

-1.0 mV

Offset error

Temperature drift <0.01 mV/K

Operating voltage drift <0.6 mV/V

External reference -1.0

Differential mode

AVCC/1.6 10

AVCC/2.0 8.0

Gain error

Bandgap ±5.0

Temperature drift <0.02 mV/K

Operating voltage drift <0.5 mV/V

lsb

Noise

Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V

Differential mode, shorted input 2msps, V

= 3.6V, Clk

= 16MHz

PER

REF

0.4

is used.

Table 36-42. Gain stage characteristics.

Symbol Parameter Condition Min. Typ. Max. Units

sample

Input resistance Switched in normal mode 4.0 kΩ

Input capacitance Switched in normal mode 4.4 pF

Signal range Gain stage output 0 VCC- 0.6 V

Propagation delay ADC conversion rate 1.0

Sample rate Same as ADC 100 1000 kHz

INL

(1)

Integral non-linearity 500ksps

All gain

settings

±1.5 ±4.0 lsb

mV rms

Clk

ADC

cycles

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

Symbol Parameter Condition Min. Typ. Max. Units

1x gain, normal mode -0.8

Gain error

64x gain, normal mode -3.5

1x gain, normal mode -2.0

Offset error, input referred

64x gain, normal mode -4.0

Noise

1x gain, normal mode

= 3.6V

8x gain, normal mode 1.5

Ext. V

REF

0.5

64x gain, normal mode 11

Note: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

36.2.7 DAC Characteristics

Table 36-43. Power supply, reference and output range.

Symbol Parameter Condition Min. Ty p. Max. Units

channel

REF

Analog supply voltage VCC- 0.3 VCC+ 0.3

External reference voltage 1.0 VCC- 0.6

DC output impedance 50 Ω

Linear output voltage range 0.15 AVCC-0.15 V

%8x gain, normal mode -2.5

mV8x gain, normal mode -5.0

rms

AREF

Reference input resistance >10 MΩ

CAREF Reference input capacitance Static load 7.0 pF

Minimum Resistance load 1.0 kΩ

100 pF

Maximum capacitance load

1000Ω serial resistance 1.0 nF

Operating within accuracy specification AVCC/1000

Output sink/source

Safe operation 10

Table 36-44. Clock and timing.

Symbol Parameter Condition Min. Typ. Max. Units

Fclk Conversion rate Fout=Fclk/4, Cload=100pF, maximum step size 0 1000 ksps

XMEGA A4U [DATASHEET]

8387C–AVR–3/12

100

Atmel ATxmega128A4U Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Ordering Information

2. Pinout/Block Diagram

3. Overview

3.1 Block Diagram

4. Resources

4.1 Recommended reading

5. Capacitive touch sensing

6. AVR CPU

6.1 Features

6.2 Overview

6.3 Architectural Overview

6.4 ALU - Arithmetic Logic Unit

6.4.1 Hardware Multiplier

6.5 Program Flow

6.6 Status Register

6.7 Stack and Stack Pointer

6.8 Register File

7. Memories

7.1 Features

7.2 Overview

7.3 Flash Program Memory

7.3.1 Application Section

7.3.2 Application Table Section

7.3.3 Boot Loader Section

7.3.4 Production Signature Row

7.3.5 User Signature Row

7.4 Fuses and Lock bits

7.5 Data Memory

7.6 EEPROM

7.7 I/O Memory

7.7.1 General Purpose I/O Registers

7.8 Data Memory and Bus Arbitration

7.9 Memory Timing

7.10 Device ID and Revision

7.11 I/O Memory Protection

7.12 Flash and EEPROM Page Size

8. DMAC – Direct Memory Access Controller

8.1 Features

8.2 Overview

9. Event System

9.1 Features

9.2 Overview

10. System Clock and Clock options

10.1 Features

10.2 Overview

10.3 Clock Sources

10.3.1 32kHz Ultra Low Power Internal Oscillator

10.3.2 32.768kHz Calibrated Internal Oscillator

10.3.3 32.768kHz Crystal Oscillator

10.3.4 0.4 - 16MHz Crystal Oscillator

10.3.5 2MHz Run-time Calibrated Internal Oscillator

10.3.6 32MHz Run-time Calibrated Internal Oscillator

10.3.7 External Clock Sources

10.3.8 PLL with 1x-31x Multiplication Factor

11. Power Management and Sleep Modes

11.1 Features

11.2 Overview

11.3 Sleep Modes

11.3.1 Idle Mode

11.3.2 Power-down Mode

11.3.3 Power-save Mode

11.3.4 Standby Mode

11.3.5 Extended Standby Mode

12. System Control and Reset

12.1 Features

12.2 Overview

12.3 Reset Sequence

12.4 Reset Sources

12.4.1 Power-on Reset

12.4.2 Brownout Detection

12.4.3 External Reset

12.4.4 Watchdog Reset

12.4.5 Software Reset

12.4.6 Program and Debug Interface Reset

13. WDT – Watchdog Timer