Atmel ATxmega256A3, ATxmega192A3, ATxmega128A3, ATxmega64A3 Datasheet

Features

• High-performance, Low-power 8/16-bit AVR XMEGA Microcontroller

• Non-volatile Program and Data Memories

– 64 KB - 256 KB of In-System Self-Programmable Flash – 4 KB - 8 KB Boot Code Section with Independent Lock Bits – 2 KB - 4 KB EEPROM – 4 KB - 16 KB Internal SRAM

• Peripheral Features

– Four-channel DMA Controller with support for external requests – Eight-channel Event System

– Seven 16-bit Timer/Counters

Four Timer/Counters with 4 Output Compare or Input Capture channels Three Timer/Counters with 2 Output Compare or Input Capture channels High Resolution Extensions on all Timer/Counters Advanced Waveform Extension on one Timer/Counter

– Seven USARTs

IrDA Extension on 1 USART – AES and DES Crypto Engine – Two Two-wire Interfaces with dual address match (I – Three SPI (Serial Peripheral Interfaces) – 16-bit Real Time Counter with Separate Oscillator – Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters – One Two-channel, 12-bit, 1 Msps Digital to Analog Converter – Four Analog Comparators with Window compare function – External Interrupts on all General Purpose I/O pins – Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal and External Clock Options with PLL – Programmable Multi-level Interrupt Controller – Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby – Advanced Programming, Test and Debugging Interfaces

JTAG (IEEE 1149.1 Compliant) Interface for test, debug and programming

PDI (Program and Debug Interface) for programming, test and debugging

• I/O and Packages

– 50 Programmable I/O Lines – 64-lead TQFP – 64-pad QFN

• Operating Voltage

– 1.6 – 3.6V

• Speed performance

– 0 – 12 MHz @ 1.6 – 3.6V – 0 – 32 MHz @ 2.7 – 3.6V

C and SMBus compatible)

8/16-bit XMEGA A3

Microcontroller

ATxmega256A3 ATxmega192A3 ATxmega128A3 ATxmega64A3

Preliminary

Typical Applications

• Industrial control • Climate control • Hand-held battery applications

• Factory automation • ZigBee • Power tools

• Building control • Motor control • HVAC

• Board control • Networking • Metering

• White Goods • Optical • Medical Applications

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1. Ordering Information

XMEGA A3

Ordering Code Flash E

ATxmega256A3-AU 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V

ATxmega192A3-AU 192 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V

ATxmega128A3-AU 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V

ATxmega64A3-AU 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V

ATxmega256A3-MH 256 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V

ATxmega192A3-MH 192 KB + 8 KB 4 KB 16 KB 32 1.6 - 3.6V

ATxmega128A3-MH 128 KB + 8 KB 2 KB 8 KB 32 1.6 - 3.6V

ATxmega64A3-MH 64 KB + 4 KB 2 KB 4 KB 32 1.6 - 3.6V

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For packaging information, see ”Errata” on page 93

SRAM Speed (MHz) Power Supply Package

64A

64M2

(1)(2)(3)

Tem p

-40°C - 85°C

64A

64M2

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Package Type

64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

64-Pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-Lead Package (QFN)

2. Pinout/Block Diagram

INDEX CORNER

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

1 2 3 4 5 6 7

9 10 11 12 13 14 15 16

PF2 PF1 PF0 VCC GND PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 VCC GND PD7

PA 3 PA 4 PA 5 PA 6

PA 7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

GND

VCC

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

VCC

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PA 2

PA 1

PA 0

AVCC

GND

PR1

PR0

RESET/PDI

PDI

PF7

PF6

VCC

GND

PF5

PF4

PF3

FLASH

RAM

E2PROM

DMA

Interrupt Controller

OCD

ADC A

ADC B

DAC B

AC A0

AC A1

AC B0

AC B1

Por t

Event System ctrl

Por t R

Power

Control

Reset

Control

Watchdog

OSC/CLK

Control

BOD POR

RTC

EVENT ROUTING NETWORK

DATA BU S

VREF

TEMP

Por t C Port D Port E Por t F

CPU

T/C0:1

USART0:1

SPI

TWI

T/C0:1

USART0:1

SPI

T/C0:1

USART0:1

SPI

TWI

T/C0

USART0

Figure 2-1. Block diagram and pinout.

XMEGA A3

Notes: 1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 49.

2. The large center pad underneath the TQFP package should be soldered to ground on the board to ensure good mechanical

stability.

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3. Overview

XMEGA A3

The XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.

The XMEGA A3 devices provide the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection.

The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this can also be used for On-chip Debug and programming.

enhanced RISC architecture. By executing powerful

The XMEGA A3 devices have five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all peripherals to continue functioning. The Power-down mode saves the SRAM and register contents but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further reduce power consumption, the peripheral clock for each individual peripheral can optionally be stopped in Active mode and Idle sleep mode.

The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader running in the device can use any interface to download the application program to the Flash memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications.

The XMEGA A3 devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.

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3.1 Block Diagram

PE[0..7]

PORT E (8)

TCE0:1

USARTE0:1

TWIE

SPIE

TCF0

USARTF0

PORT F (8)

Power Supervision POR/BOD &

RESET

PORT A (8)

PORT B (8)

DMA

Controller

BUS

Controller

SRAM

ADCA

ACA

DACB

ADCB

ACB

OCD

PDI

CPU

PA[0..7]

PB[0..7]/

JTAG

Watchdog

Timer

Watchdog Oscillato r

Interrupt

Controller

DATA BUS

Prog/Debug

Controller

VCC

GND

Oscillator

Circuits/

Clock

Generation

Oscillato r

Control

Real Time

Counter

Event System

Controller

JTAG

PDI_DATA

RESET/ PDI_CLK

PORT B

Sleep

Controller

Flash EEPROM

NVM Controller

DES

AES

IRCOM

PORT C (8)

PC[0..7]

TCC0:1

USARTC0:1

TWIC

SPIC

PD[0..7]

PORT R (2)

XTAL1

XTAL2

PR[0..1]

PORT D (8)

TCD0:1

USARTD0:1

SPID

TOSC1

TOSC2

EVENT ROUTING NETWORK

PF[0..7]

To Clock Generator

Int. Ref.

AREFA

AREFB

Tempref

VCC/10

Figure 3-1. XMEGA A3 Block Diagram

XMEGA A3

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4. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

4.1 Recommended reading

• XMEGA Manual

• XMEGA Application Notes

This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals.

The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.

5. Disclaimer

For devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology. Min. and Max values will be available after the device is characterized.

XMEGA A3

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6. AVR CPU

Flash

Program

Memory

Instruction

Decode

Program

Counter

OCD

32 x 8 General

Purpose

Registers

ALU

Multiplier/

DES

Instruction

STATUS/

CONTROL

Peripheral

Module 1

Peripheral

Module 2

EEPROM PMICSRAM

DATA BUS

6.1 Features

6.2 Overview

XMEGA A3

• 8/16-bit high performance AVR RISC Architecture

– 138 instructions – Hardware multiplier

• 32x8-bit registers directly connected to the ALU

• Stack in RAM

• Stack Pointer accessible in I/O memory space

• Direct addressing of up to 16M bytes of program and data memory

• True 16/24-bit access to 16/24-bit I/O registers

• Support for 8-, 16- and 32-bit Arithmetic

• Configuration Change Protection of system critical features

The XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations and control peripherals. Interrupt handling is described in a separate section. Figure

6-1 on page 7 shows the CPU block diagram.

Figure 6-1. CPU block diagram

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The AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory.

This concept enables instructions to be executed in every clock cycle. The program memory is In-System Re-programmable Flash memory.

6.3 Register File

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory.

6.4 ALU - Arithmetic Logic Unit

The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. After an arithmetic or logic operation, the Status Register is updated to reflect information about the result of the operation.

XMEGA A3

6.5 Program Flow

The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both signed and unsigned multiplication and fractional format.

When the device is powered on, the CPU starts to execute instructions from the lowest address in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to be fetched. After a reset, the PC is set to location ‘0’.

Program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number uses a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU.

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7. Memories

7.1 Features

7.2 Overview

XMEGA A3

• Flash Program Memory

– One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section for application code or bootloader code – Separate lock bits and protection for all sections – Built in fast CRC check of a selectable flash program memory section

• Data Memory

– One linear address space – Single cycle access from CPU – SRAM – EEPROM

Byte and page accessible Optional memory mapping for direct load and store

– I/O Memory

Configuration and Status registers for all peripherals and modules 16 bit-accessible General Purpose Register for global variables or flags

– Bus arbitration

Safe and deterministic handling of CPU and DMA Controller priority

– Separate buses for SRAM, EEPROM, I/O Memory and External Memory access

Simultaneous bus access for CPU and DMA Controller

• Production Signature Row Memory for factory programmed data

Device ID for each microcontroller device type Serial number for each device Oscillator calibration bytes ADC, DAC and temperature sensor calibration data

• User Signature Row

One flash page in size Can be read and written from software Content is kept after chip erase

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The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All three memory spaces are linear and require no paging. The available memory size configurations are shown in ”Ordering Information” on page 2. In addition each device has a Flash memory signature row for calibration data, device identification, serial number etc.

Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software.

7.3 In-System Programmable Flash Program Memory

The XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each Flash address location is 16 bits.

The Program Flash memory space is divided into Application and Boot sections. Both sections have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash memory.

A third section inside the Application section is referred to as the Application Table section which has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software.

Figure 7-1. Flash Program Memory (Hexadecimal address)

Word Add r ess

XMEGA A3

1EFFF / 16FFF / EFFF / 77FF

1F000 / 17000 / F000 / 7800

1FFFF / 17FFF / FFFF / 7FFF

20000 / 18000 / 10000 / 8000

20FFF / 18FFF / 10FFF / 87FF

Application Section

(256 KB/192 KB/128 KB/64 KB)

...

Application Table Section

(8 KB/8 KB/8 KB/4 KB)

Boot Section

(8 KB/8 KB/8 KB/4 KB)

The Application Table Section and Boot Section can also be used for general application software.

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XMEGA A3

7.4 Data Memory

The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all devices in the family is identical and with empty, reserved memory space for smaller devices.

Figure 7-2. Data Memory Map (Hexadecimal address)

Byte Address ATxmega192A3 Byte Address ATxmega128A3 Byte Address ATxmega64A3

FFF FFF FFF

1000

1FFF

2000

5FFF 3FFF 2FFF

I/O Registers

(4 KB)

EEPROM

(4 KB)

Internal SRAM

(16 KB)

1000

17FF 17FF

2000

I/O Registers

(4 KB)

EEPROM

(2 KB)

RESERVED RESERVED

Internal SRAM

(8 KB)

Byte Address ATxmega256A3

1000

2000

FFF

1000

1FFF

2000

5FFF

Internal SRAM

I/O Registers

Internal SRAM

I/O Registers

(4 KB)

EEPROM

(2 KB)

(4 KB)

EEPROM

(4 KB)

(16 KB)

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7.4.1 I/O Memory

All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory.

The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly.

I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers.

The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the ”Periph-

eral Module Address Map” on page 56.

7.4.2 SRAM Data Memory

The XMEGA A3 devices have internal SRAM memory for data storage.

7.4.3 EEPROM Data Memory

XMEGA A3

The XMEGA A3 devices have internal EEPROM memory for non-volatile data storage. It is addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access.

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7.5 Production Signature Row

The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules.

The production signature row also contains a device ID that identify each microcontroller device type, and a serial number that is unique for each manufactured device. The device ID for the available XMEGA A3 devices is shown in Table 7-1 on page 13. The serial number consist of the production LOT number, wafer number, and wafer coordinates for the device.

The production signature row can not be written or erased, but it can be read from both application software and external programming.

Table 7-1. Device ID bytes for XMEGA A3 devices.

ATxmega64A3 42 96 1E

ATxmega128A3 42 97 1E

ATxmega192A3 44 97 1E

XMEGA A3

Device Device ID bytes

Byte 2 Byte 1 Byte 0

7.6 User Signature Row

The User Signature Row is a separate memory section that is fully accessible (read and write) from application software and external programming. The user signature row is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers or identification numbers, random number seeds etc. This section is not erased by Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions.

ATxmega256A3 42 98 1E

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XMEGA A3

7.7 Flash and EEPROM Page Size

The Flash Program Memory and EEPROM data memory are organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM.

Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase

operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address bits (FWORD) gives the word in the page.

Table 7-2. Number of words and Pages in the Flash.

Devices Flash Page Size FWORD FPAGE Application Boot

Size (words) Size No of Pages Size No of Pages

ATxmega64A3 64 KB + 4 KB 128 Z[7:1] Z[16:8] 64K 256 4 KB 16

ATxmega128A3 128 KB + 8 KB 256 Z[8:1] Z[17:9] 128K 256 8 KB 16

ATxmega192A3 192 KB + 8 KB 256 Z[8:1] Z[18:9] 192K 384 8 KB 16

ATxmega256A3 256 KB + 8 KB 256 Z[8:1] Z[18:9] 256K 512 8 KB 16

Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A3 devices.

EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives the page number and the least significant address bits (E2BYTE) gives the byte in the page.

Table 7-3. Number of bytes and Pages in the EEPROM.

Devices EEPROM Page Size E2BYTE E2PAGE No of Pages

Size (Bytes)

ATxmega64A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64

ATxmega128A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64

ATxmega192A3 2 KB 32 ADDR[4:0] ADDR[10:5] 64

ATxmega256A3 4 KB 32 ADDR[4:0] ADDR[11:5] 128

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8. DMAC - Direct Memory Access Controller

8.1 Features

• Allows High-speed data transfer

– From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral

• 4 Channels

• From 1 byte and up to 16 M bytes transfers in a single transaction

• Multiple addressing modes for source and destination address

–Increment – Decrement – Static

• 1, 2, 4, or 8 bytes Burst Transfers

• Programmable priority between channels

8.2 Overview

The XMEGA A3 has a Direct Memory Access (DMA) Controller to move data between memories and peripherals in the data space. The DMA controller uses the same data bus as the CPU to transfer data.

XMEGA A3

It has 4 channels that can be configured independently. Each DMA channel can perform data transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be configured to access the source and destination memory address with incrementing, decrementing or static addressing. The addressing is independent for source and destination address. When the transaction is complete the original source and destination address can automatically be reloaded to be ready for the next transaction.

The DMAC can access all the peripherals through their I/O memory registers, and the DMA may be used for automatic transfer of data to/from communication modules, as well as automatic data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or from port pins. A wide range of transfer triggers is available from the peripherals, Event System and software. Each DMA channel has different transfer triggers.

To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa.

The DMA controller can read from memory mapped EEPROM, but it cannot write to the EEPROM or access the Flash.

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9. Event System

9.1 Features

9.2 Overview

• Inter-peripheral communication and signalling with minimum latency

• CPU and DMA independent operation

• 8 Event Channels allows for up to 8 signals to be routed at the same time

• Events can be generated by

– Timer/Counters (TCxn) – Real Time Counter (RTC) – Analog to Digital Converters (ADCx) – Analog Comparators (ACx) – Ports (PORTx) – System Clock (Clk – Software (CPU)

SYS

)

• Events can be used by

– Timer/Counters (TCxn) – Analog to Digital Converters (ADCx) – Digital to Analog Converters (DACx) – Ports (PORTx) – DMA Controller (DMAC) – IR Communication Module (IRCOM)

• The same event can be used by multiple peripherals for synchronized timing

• Advanced Features

– Manual Event Generation from software (CPU) – Quadrature Decoding – Digital Filtering

• Functions in Active and Idle mode

XMEGA A3

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The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more peripherals. What changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupts, CPU or DMA resources.

The indication of a change in a peripheral is referred to as an event, and is usually the same as the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 9-1 on page 17 shows a basic block diagram of the Event System with the Event Routing Network and the peripherals to which it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events.

The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals.

The Event System is functional in both Active and Idle modes.

Figure 9-1. Event system block diagram.

ADCx

DACx

Event Routing

Network

PORTx

CPU

ACx

RTC

T/Cxn

DMACIRCOM

ClkSYS

XMEGA A3

The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU).

All events from all peripherals are always routed into the Event Routing Network. This consist of eight multiplexers where each can be configured in software to select which event to be routed into that event channel. All eight event channels are connected to the peripherals that can use events, and each of these peripherals can be configured to use events from one or more event channels to automatically trigger a software selectable action.

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10. System Clock and Clock options

10.1 Features

• Fast start-up time

• Safe run-time clock switching

• Internal Oscillators:

– 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator – 32 kHz Ultra Low Power (ULP) oscillator

• External clock options

– 0.4 - 16 MHz Crystal Oscillator – 32.768 kHz Crystal Oscillator – External clock

• PLL with internal and external clock options with 2 to 31x multiplication

• Clock Prescalers with 2 to 2048x division

• Fast peripheral clock running at 2 and 4 times the CPU clock speed

• Automatic Run-Time Calibration of internal oscillators

• Crystal Oscillator failure detection

10.2 Overview

XMEGA A3

XMEGA A3 has an advanced clock system, supporting a large number of clock sources. It incorporates both integrated oscillators, external crystal oscillators and resonators. A high frequency Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a wide range of clock frequencies from the clock source input.

It is possible to switch between clock sources from software during run-time. After reset the device will always start up running from the 2 Mhz internal oscillator.

A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.

A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 19 shows the principal clock system in XMEGA A3.

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Figure 10-1. Clock system overview

32 MHz

Run-time Calibrated

Internal Oscillator

32 kHz ULP

Internal Oscillator

32.768 kHz

Calibrated Internal

Oscillator

32.768 KHz

Crystal Oscillator

0.4 - 16 MHz

Crystal Oscillator

2 MHz

Run-Time Calibrated

Internal Oscillator

External

Clock Input

CLOCK CONTROL

UNIT

with PLL and

Prescaler

WDT/BOD

clk

ULP

RTC

clk

RTC

EVSYS

PERIPHERALS

ADC

DAC

PORTS

...

clk

PER

DMA

INTERRUPT

RAM

NVM MEMORY

FLASH

EEPROM

CPU

clk

CPU

XMEGA A3

10.3 Clock Options

10.3.1 32 kHz Ultra Low Power Internal Oscillator

10.3.2 32.768 kHz Calibrated Internal Oscillator

Each clock source is briefly described in the following sub-sections.

The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock source for the Real Time Counter. This oscillator cannot be used as the system clock source, and it cannot be directly controlled from software.

The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for the Real Time Counter. It is calibrated during production to provide a default frequency which is close to its nominal frequency.

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10.3.3 32.768 kHz Crystal Oscillator

The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter.

10.3.4 0.4 - 16 MHz Crystal Oscillator

The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and crystals ranging from 400 kHz to 16 MHz.

10.3.5 2 MHz Run-time Calibrated Internal Oscillator

The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator.

10.3.6 32 MHz Run-time Calibrated Internal Oscillator

The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator.

XMEGA A3

10.3.7 External Clock input

The external clock input gives the possibility to connect a clock from an external source.

10.3.8 PLL with Multiplication factor 1 - 31x

The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.

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11. Power Management and Sleep Modes

11.1 Features

• 5 sleep modes

–Idle – Power-down –Power-save –Standby – Extended standby

• Power Reduction registers to disable clocks to unused peripherals

11.2 Overview

The XMEGA A3 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the CPU is executing application code. The application code decides when and which sleep mode to enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode.

In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. This reduces the power consumption in Active mode and Idle sleep mode.

XMEGA A3

11.3 Sleep Modes

11.3.1 Idle Mode

In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from all enabled interrupts will wake the device.

11.3.2 Power-down Mode

In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC) clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and asynchronous port interrupts, e.g pin change.

11.3.3 Power-save Mode

Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will keep running during sleep and the device can also wake up from RTC interrupts.

11.3.4 Standby Mode

Standby mode is identical to Power-down with the exception that all enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time when external crystals or resonators are used.

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11.3.5 Extended Standby Mode

Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals or resonators are used.

XMEGA A3

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12. System Control and Reset

12.1 Features

• Multiple reset sources for safe operation and device reset

– Power-On Reset – External Reset – Watchdog Reset

The Watchdog Timer runs from separate, dedicated oscillator

– Brown-Out Reset

Accurate, programmable Brown-Out levels – PDI reset – Software reset

• Asynchronous reset

– No running clock in the device is required for reset

• Reset status register

12.2 Resetting the AVR

During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset Vector to the first address in the Boot Section.

XMEGA A3

The I/O ports of the AVR are immediately tri-stated when a reset source goes active. The reset functionality is asynchronous, so no running clock is required to reset the device. After the device is reset, the reset source can be determined by the application by reading the Reset Status Register.

12.3 Reset Sources

12.3.1 Power-On Reset

The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.

12.3.2 External Reset

The MCU is reset when a low level is present on the RESET pin.

12.3.3 Watchdog Reset

The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled. The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For more details see ”WDT - Watchdog Timer” on page 24.

12.3.4 Brown-Out Reset

The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.

12.3.5 PDI reset

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The MCU can be reset through the Program and Debug Interface (PDI).

12.3.6 Software reset

The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.

13. WDT - Watchdog Timer

13.1 Features

• 11 selectable timeout periods, from 8 ms to 8s.

• Two operation modes

– Standard mode – Window mode

• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator

• Configuration lock to prevent unwanted changes

13.2 Overview

The XMEGA A3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on and if the Watchdog Timer is not reset within a software configurable time-out period, the microcontroller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset the WDT, and prevent microcontroller reset.

XMEGA A3

The WDT has a Window mode. In this mode the WDR instruction must be run within a specified period called a window. Application software can set the minimum and maximum limits for this window. If the WDR instruction is not executed inside the window limits, the microcontroller will be reset.

A protection mechanism using a timed write sequence is implemented in order to prevent unwanted enabling, disabling or change of WDT settings.

For maximum safety, the WDT also has an Always-on mode. This mode is enabled by programming a fuse. In Always-on mode, application software can not disable the WDT.

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14. PMIC - Programmable Multi-level Interrupt Controller

14.1 Features

• Separate interrupt vector for each interrupt

• Short, predictable interrupt response time

• Programmable Multi-level Interrupt Controller

– 3 programmable interrupt levels – Selectable priority scheme within low level interrupts (round-robin or fixed) – Non-Maskable Interrupts (NMI)

• Interrupt vectors can be moved to the start of the Boot Section

14.2 Overview

XMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can define three different priority levels for interrupts; high, medium or low. Medium level interrupts may interrupt low level interrupt service routines. High level interrupts may interrupt both lowand medium level interrupt service routines. Low level interrupts have an optional round robin scheme to make sure all interrupts are serviced within a certain amount of time.

The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).

XMEGA A3

14.3 Interrupt vectors

When an interrupt is serviced, the program counter will jump to the interrupt vector address. The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA A manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word address.

Table 14-1. Reset and Interrupt Vectors

Program Address

(Base Address) Source Interrupt Description

0x000 RESET

0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI)

0x004 PORTC_INT_base Port C Interrupt base

0x008 PORTR_INT_base Port R Interrupt base

0x00C DMA_INT_base DMA Controller Interrupt base

0x014 RTC_INT_base Real Time Counter Interrupt base

0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base

0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base

0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base

0x030 SPIC_INT_vect SPI on port C Interrupt vector

0x032 USARTC0_INT_base USART 0 on port C Interrupt base

0x03D USARTC1_INT_base USART 1 on port C Interrupt base

0x03E AES_INT_vect AES Interrupt vector

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Table 14-1. Reset and Interrupt Vectors (Continued)

Program Address

(Base Address) Source Interrupt Description

0x040 NVM_INT_base Non-Volatile Memory Interrupt base

0x044 PORTB_INT_base Port B Interrupt base

0x048 ACB_INT_base Analog Comparator on Port B Interrupt base

0x04E ADCB_INT_base Analog to Digital Converter on Port B Interrupt base

0x056 PORTE_INT_base Port E INT base

0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base

0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base

0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base

0x072 SPIE_INT_vect SPI on port E Interrupt vector

0x074 USARTE0_INT_base USART 0 on port E Interrupt base

0x07A USARTE1_INT_base USART 1 on port E Interrupt base

0x080 PORTD_INT_base Port D Interrupt base

0x084 PORTA_INT_base Port A Interrupt base

0x088 ACA_INT_base Analog Comparator on Port A Interrupt base

0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base

XMEGA A3

0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base

0x0A6 TCD1_INT_base Timer/Counter 1 on port D Interrupt base

0x0AE SPID_INT_vector SPI D Interrupt vector

0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base

0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base

0x0D0 PORTF_INT_base Port F Interrupt base

0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base

0x0EE USARTF0_INT_base USART 0 on port F Interrupt base

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15. I/O Ports

15.1 Features

15.2 Overview

XMEGA A3

• Selectable input and output configuration for each pin individually

• Flexible pin configuration through dedicated Pin Configuration Register

• Synchronous and/or asynchronous input sensing with port interrupts and events

– Sense both edges – Sense rising edges – Sense falling edges – Sense low level

• Asynchronous wake-up from all input sensing configurations

• Two port interrupts with flexible pin masking

• Highly configurable output driver and pull settings:

– Totem-pole – Pull-up/-down – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O

• Configuration of multiple pins in a single operation

• Read-Modify-Write (RMW) support

• Toggle/clear/set registers for Output and Direction registers

• Clock output on port pin

• Event Channel 7 output on port pin

• Mapping of port registers (virtual ports) into bit accessible I/O memory space

The XMEGA A3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins, ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asynchronous input sensing, pin change interrupts and configurable output settings. All functions are individual per pin, but several pins may be configured in a single operation.

15.3 I/O configuration

All port pins (Pn) have programmable output configuration. In addition, all port pins have an inverted I/O function. For an input, this means inverting the signal between the port pin and the pin register. For an output, this means inverting the output signal between the port register and the port pin. The inverted I/O function can be used also when the pin is used for alternate functions.

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15.3.1 Push-pull

INn

OUTn

DIRn

INn

OUTn

DIRn

INn

OUTn

DIRn

15.3.2 Pull-down

XMEGA A3

Figure 15-1. I/O configuration - Totem-pole

Figure 15-2. I/O configuration - Totem-pole with pull-down (on input)

15.3.3 Pull-up

15.3.4 Bus-keeper

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Figure 15-3. I/O configuration - Totem-pole with pull-up (on input)

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.

15.3.5 Others

INn

OUTn

DIRn

INn

OUTn

INn

OUTn

XMEGA A3

Figure 15-4. I/O configuration - Totem-pole with bus-keeper

Figure 15-5. Output configuration - Wired-OR with optional pull-down

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Figure 15-6. I/O configuration - Wired-AND with optional pull-up

15.4 Input sensing

IN V ERT ED I/O

Interrupt

Control

IR E Q

Event

Synchronizer

INn

EDGE

DETECT

Asynchronous sen sing

Synchronous sen sing

EDGE

DETECT

XMEGA A3

• Sense both edges

• Sense rising edges

• Sense falling edges

• Sense low level

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 30.

Figure 15-7. Input sensing system overview

When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.

15.5 Port Interrupt

Each port has two interrupts with separate priority and interrupt vector. All pins on the port can be individually selected as source for each of the interrupts. The interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt.

15.6 Alternate Port Functions

In addition to the input/output functions on all port pins, most pins have alternate functions. This means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on

page 49 shows which modules on peripherals that enable alternate functions on a pin, and

which alternate functions that are available on a pin.

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16. T/C - 16-bits Timer/Counter with PWM

16.1 Features

• Seven 16-bit Timer/Counters

– Four Timer/Counters of type 0 – Three Timer/Counters of type 1

• Four Compare or Capture (CC) Channels in Timer/Counter 0

• Two Compare or Capture (CC) Channels in Timer/Counter 1

• Double Buffered Timer Period Setting

• Double Buffered Compare or Capture Channels

• Waveform Generation:

– Single Slope Pulse Width Modulation – Dual Slope Pulse Width Modulation – Frequency Generation

• Input Capture:

– Input Capture with Noise Cancelling – Frequency capture – Pulse width capture – 32-bit input capture

• Event Counter with Direction Control

• Timer Overflow and Timer Error Interrupts and Events

• One Compare Match or Capture Interrupt and Event per CC Channel

• Supports DMA Operation

• Hi-Resolution Extension (Hi-Res)

• Advanced Waveform Extension (AWEX)

XMEGA A3

16.2 Overview

XMEGA A3 has seven Timer/Counters, four Timer/Counter 0 and three Timer/Counter 1. The difference between them is that Timer/Counter 0 has four Compare/Capture channels, while Timer/Counter 1 has two Compare/Capture channels.

The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of Timer and Compare registers are double buffered to ensure glitch free operation. Single slope PWM, dual slope PWM and frequency generation waveforms can be generated using the Compare Channels.

Through the Event System, any input pin or event in the microcontroller can be used to trigger input capture, hence no dedicated pins is required for this. The input capture has a noise canceller to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width measurements.

A wide range of interrupt or event sources are available, including T/C Overflow, Compare match and Capture for each Compare/Capture channel in the T/C.

PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1 and TCF0, respectively.

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XMEGA A3

AWeX

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

Waveform

Generation

Buffer

Comparator

Hi-Res

Fault

Protection

Capture

Control

Base Counter

Counter

Control Logic

Timer Period

Prescaler

DTI

Dead-Time

Insertion

Pattern

Generation

clk

PER4

PORT

Event

System

clk

PER

Timer/Counter

Figure 16-1. Overview of a Timer/Counter and closely related peripherals

The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on

page 34 for more details.

The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See ”AWEX - Advanced

Waveform Extension” on page 33 for more details.

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17. AWEX - Advanced Waveform Extension

17.1 Features

• Output with complementary output from each Capture channel

• Four Dead Time Insertion (DTI) Units, one for each Capture channel

• 8-bit DTI Resolution

• Separate High and Low Side Dead-Time Setting

• Double Buffered Dead-Time

• Event Controlled Fault Protection

• Single Channel Multiple Output Operation (for BLDC motor control)

• Double Buffered Pattern Generation

17.2 Overview

The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for

example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.

Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output with dead time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. Optionally the final output can be inverted by using the invert I/O setting for the port pin.

XMEGA A3

The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the waveform generator output from Compare Channel A can be distributed to, and override all port pins. W hen the Pattern Generator unit is enabled, the DTI unit is bypassed.

The Fault Protection unit is connected to the Event System. This enables any event to trigger a fault condition that will disable the AWEX output. Several event channels can be used to trigger fault on several different conditions.

The AWEX is available for TCC0. The notation of this is AWEXC.

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18. Hi-Res - High Resolution Extension

18.1 Features

• Increases Waveform Generator resolution by 2-bits (4x)

• Supports Frequency, single- and dual-slope PWM operation

• Supports the AWEX when this is enabled and used for the same Timer/Counter

18.2 Overview

The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running at four times the CPU clock speed will be as input to the Timer/Counter.

The High Resolution Extension can also be used when an AWEX is enabled and used with a Timer/Counter.

XMEGA A3 devices have four Hi-Res Extensions that each can be enabled for each Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are HIRESC, HIRESD, HIRESE and HIRESF, respectively.

XMEGA A3

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19. RTC - Real-Time Counter

10-bit

prescaler

Counter

Period

Compare

Overflow

Compare Matc h

1.024 kHz

32.768 kHz

19.1 Features

• 16-bit Timer

• Flexible Tick resolution ranging from 1 Hz to 32.768 kHz

• One Compare register

• One Period register

• Clear timer on Overflow or Compare Match

• Overflow or Compare Match event and interrupt generation

19.2 Overview

The XMEGA A3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the 32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare register. For details, see Figure 19-1.

A wide range of Resolution and Time-out periods can be configured using the RTC. With a maximum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1 second, the maximum time-out period is over 18 hours (65536 seconds).

XMEGA A3

Figure 19-1. Real-time Counter overview

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20. TWI - Two Wire Interface

20.1 Features

• Two Identical TWI peripherals

• Simple yet Powerful and Flexible Communication Interface

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space Allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up when in Sleep Mode

• I

C and System Management Bus (SMBus) compatible

20.2 Overview

The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock (SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 individually addressable devices. Since it is a multi-master bus, one or more devices capable of taking control of the bus can be connected.

XMEGA A3

The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.

PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.

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21. SPI - Serial Peripheral Interface

21.1 Features

• Three Identical SPI peripherals

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

21.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer between different devices. Devices can communicate using a master-slave scheme, and data is transferred both to and from the devices simultaneously.

PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID, and SPIE respectively.

XMEGA A3

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22. USART

22.1 Features

22.2 Overview

XMEGA A3

• Seven Identical USART peripherals

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation

• Master or Slave Clocked Synchronous Operation

• High-resolution Arithmetic Baud Rate Generator

• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

• Odd or Even Parity Generation and Parity Check Supported by Hardware

• Data OverRun Detection

• Framing Error Detection

• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter

• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

• Multi-processor Communication Mode

• Double Speed Asynchronous Communication Mode

• Master SPI mode for SPI communication

• IrDA support through the IRCOM module

The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication module. The USART supports full duplex communication, and both asynchronous and clocked synchronous operation. The USART can also be set in Master SPI mode to be used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both direction, enabling continued data transmission without any delay between frames. There are separate interrupt vectors for receive and transmit complete, enabling fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled.

One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2 kbps.

PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1 and USARTF0, respectively.

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23. IRCOM - IR Communication Module

23.1 Features

• Pulse modulation/demodulation for infrared communication

• Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps

• Selectable pulse modulation scheme

– 3/16 of baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled

• Built in filtering

• Can be connected to and used by one USART at a time

23.2 Overview

XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period, fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation disabled. There is one IRCOM available which can be connected to any USART to enable infrared pulse coding/decoding for that USART.

XMEGA A3

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24. Crypto Engine

24.1 Features

24.2 Overview

XMEGA A3

• Data Encryption Standard (DES) CPU instruction

• Advanced Encryption Standard (AES) Crypto module

• DES Instruction

– Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block

• AES Crypto Module

– Encryption and Decryption – Support 128-bit keys – Support XOR data load mode to the State memory for Cipher Block Chaining – Encryption/Decryption in 375 clock cycles per 16-byte block

The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used encryption standards. These are supported through an AES peripheral module and a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and DES encrypted communication and data storage.

DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte data blocks must be loaded into the Register file, and then DES must be executed 16 times to encrypt/decrypt the data block.

The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done and decrypted/encrypted data can be read out, and an optional interrupt can be generated. The AES Crypto Module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.

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25. ADC - 12-bit Analog to Digital Converter

25.1 Features

• Two ADCs with 12-bit resolution

• 2 Msps sample rate for each ADC

• Signed and Unsigned conversions

• 4 result registers with individual input channel control for each ADC

• 8 single ended inputs for each ADC

• 8x4 differential inputs for each ADC

• 4 internal inputs:

– Integrated Temperature Sensor – DAC Output – VCC voltage divided by 10 – Bandgap voltage

• Software selectable gain of 2, 4, 8, 16, 32 or 64

• Software selectable resolution of 8- or 12-bit.

• Internal or External Reference selection

• Event triggered conversion for accurate timing

• DMA transfer of conversion results

• Interrupt/Event on compare result

25.2 Overview

XMEGA A3

XMEGA A3 devices have two Analog to Digital Converters (ADC), see Figure 25-1 on page 42. The two ADC modules can be operated simultaneously, individually or synchronized.

The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capable of converting up to 2 million samples per second. The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements an optional gain stage is available to increase the dynamic range. In addition several internal signal inputs are available. The ADC can provide both signed and unsigned results.

This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each stage convert one part of the result. The pipeline design enables high sample rate at low clock speeds, and remove limitations on samples speed versus propagation delay. This also means that a new analog voltage can be sampled and a new ADC measurement started while other ADC measurements are ongoing.

ADC measurements can either be started by application software or an incoming event from another peripheral in the device. Four different result registers with individual input selection (MUX selection) are provided to make it easier for the application to keep track of the data. Each result register and MUX selection pair is referred to as an ADC Channel. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.

Both internal and external analog reference voltages can be used. An accurate internal 1.0V reference is available.

An integrated temperature sensor is available and the output from this can be measured with the ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the ADC.

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Figure 25-1. ADC overview

ADC

Channel A

Channel B

Channel C

Channel D

Pin inputsPin inputs

1-64 X

Internal inputs

Channel A MUX selection Channel B MUX selection Channel C MUX selection Channel D MUX selection

Event

Trigger

Configuration

Reference selection

XMEGA A3

Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results will be available in the result registers.

The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.

ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number).

PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.

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26. DAC - 12-bit Digital to Analog Converter

DAC

Channel A

Channel B

Event

Trigger

Configuration

Reference selection

Channel A

Channel B

26.1 Features

• One DAC with 12-bit resolution

• Up to 1 Msps conversion rate for each DAC

• Flexible conversion range

• Multiple trigger sources

• 1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC

• Built-in offset and gain calibration

• High drive capabilities

• Low Power Mode

26.2 Overview

The XMEGA A3 features one two-channel, 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 26-1 on page 43.

A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage as the upper limit for conversion, but it is also possible to use the supply voltage or any applied voltage in-between. The external reference input is shared with the ADC reference input.

XMEGA A3

Figure 26-1. DAC overview

The DAC has one continuous output with high drive capabilities for both resistive and capacitive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H) channels, each with separate data conversion registers.

A DAC conversion may be started from the application software by writing the data conversion registers. The DAC can also be configured to do conversions triggered by the Event System to have regular timing, independent of the application software. DMA may be used for transferring data from memory locations to DAC data registers.

The DAC has a built-in calibration system to reduce offset and gain error when loading with a calibration value from software.

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PORTB each has one DAC. Notation of this peripheral is DACB.

27. AC - Analog Comparator

27.1 Features

• Four Analog Comparators

• Selectable Power vs. Speed

• Selectable hysteresis

– 0, 20 mV, 50 mV

• Analog Comparator output available on pin

• Flexible Input Selection

– All pins on the port – Output from the DAC – Bandgap reference voltage. – Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.

• Interrupt and event generation on

– Rising edge – Falling edge –Toggle

• Window function interrupt and event generation on

– Signal above window – Signal inside window – Signal below window

27.2 Overview

XMEGA A3

XMEGA A3 features four Analog Comparators (AC). An Analog Comparator compares two voltages, and the output indicates which input is largest. The Analog Comparator may be configured to give interrupt requests and/or events upon several different combinations of input change.

Both hysteresis and propagation delays may be adjusted in order to find the optimal operation for each application.

A wide range of input selection is available, both external pins and several internal signals can be used.

The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They have identical behavior but separate control registers.

Optionally, the state of the comparator is directly available on a pin.

PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.

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Figure 27-1. Analog comparator overview

AC0

Pin inputs

Internal inputs

Pin inputs Internal inputs VCC scaled

Interrupt

sensitivity

control

Interrupts

AC1

Pin inputs Internal inputs

Pin inputs Internal inputs VCC scaled

Events

Pin 0 output

XMEGA A3

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27.3 Input Selection

AC0

AC1

Input signal

Upper limit of window

Lower limit of window

Interrupt

sensitivity

control

Interrupts

Events

The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in

Figure 27-1 on page 45.

•

Input selection from pin

• Internal signals available on positive analog comparator inputs

• Internal signals available on negative analog comparator inputs

• Output from 12-bit DAC

27.4 Window Function

The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 27-2.

XMEGA A3

– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator – Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator

– Output from 12-bit DAC

– 64-level scaler of the VCC, available on negative analog comparator input – Bandgap voltage reference

Figure 27-2. Analog comparator window function

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28. OCD - On-chip Debug

28.1 Features

• Complete Program Flow Control

– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor

• Debugging on C and high-level language source code level

• Debugging on Assembler and disassembler level

• 1 dedicated program address or source level breakpoint for AVR Studio / debugger

• 4 Hardware Breakpoints

• Unlimited Number of User Program Breakpoints

• Unlimited Number of User Data Breakpoints, with break on:

– Data location read, write or both read and write – Data location content equal or not equal to a value – Data location content is greater or less than a value – Data location content is within or outside a range – Bits of a data location are equal or not equal to a value

• Non-Intrusive Operation

– No hardware or software resources in the device are used

• High Speed Operation

– No limitation on debug/programming clock frequency versus system clock frequency

28.2 Overview

XMEGA A3

The XMEGA A3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s development tools - provides all the necessary functions to debug an application. It has support for program and data breakpoints, and can debug an application from C and high level language source code level, as well as assembler and disassembler level. It has full Non-Intrusive Operation and no hardware or software resources in the device are used. The ODC system is accessed through an external debugging tool which connects to the JTAG or PDI physical interfaces. Refer to ”Program and Debug Interfaces” on page 48.

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29. Program and Debug Interfaces

29.1 Features

• PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)

• JTAG Interface (IEEE std. 1149.1 compliant)

• Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG)

• Access to the OCD system

• Programming of Flash, EEPROM, Fuses and Lock Bits

29.2 Overview

The programming and debug facilities are accessed through the JTAG and PDI physical interfaces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no general purpose pins are used. JTAG uses four general purpose pins on PORTB.

The PDI is an Atmel proprietary protocol for communication between the microcontroller and Atmel’s or third party development tools.

29.3 IEEE 1149.1 (JTAG) Boundary-scan

The JTAG physical layer handles the basic low-level serial communication over four I/O lines named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and boundary scan.

XMEGA A3

29.3.1 Boundary-scan Order

Table 30-8 on page 53 shows the Scan order between TDI and TDO when the Boundary-scan

chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

29.3.2 Boundary-scan Description Language Files

Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description. BSDL files are available for ATxmega256/192/128/64A3 devices.

See Table 30-8 on page 53 for ATxmega256/192/128/64A3 Boundary Scan Order.

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30. Pinout and Pin Functions

The pinout of XMEGA A3 is shown in ”” on page 2. In addition to general I/O functionality, each pin may have several function. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can be used at time.

30.1 Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function.

30.1.1 Operation/Power Supply

VCC Digital supply voltage

AVCC Analog supply voltage

GND Ground

30.1.2 Port Interrupt functions

SYNC Port pin with full synchronous and limited asynchronous interrupt function

XMEGA A3

ASYNC Port pin with full synchronous and full asynchronous interrupt function

30.1.3 Analog functions

ACn Analog Comparator input pin n

AC0OUT Analog Comparator 0 Output

ADCn Analog to Digital Converter input pin n

DACn Digital to Analog Converter output pin n

AREF Analog Reference input pin

30.1.4 Timer/Counter and AWEX functions

OCnx Output Compare Channel x for Timer/Counter n

OCnx

OCnxLS Output Compare Channel x Low Side for Timer/Counter n

OCnxHS Output Compare Channel x High Side for Timer/Counter n

Inverted Output Compare Channel x for Timer/Counter n

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30.1.5 Communication functions

SCL Serial Clock for TWI

SDA Serial Data for TWI

SCLIN Serial Clock In for TWI when external driver interface is enabled

SCLOUT Serial Clock Out for TWI when external driver interface is enabled

SDAIN Serial Data In for TWI when external driver interface is enabled

SDAOUT Serial Data Out for TWI when external driver interface is enabled

XCKn Transfer Clock for USART n

RXDn Receiver Data for USART n

TXDn Transmitter Data for USART n

MOSI Master Out Slave In for SPI

MISO Master In Slave Out for SPI

SCK Serial Clock for SPI

XMEGA A3

Slave Select for SPI

30.1.6 Oscillators, Clock and Event

TOSCn Timer Oscillator pin n

XTALn Input/Output for inverting Oscillator pin n

CLKOUT Peripheral Clock Output

EVOUT Event Channel 0 Output

30.1.7 Debug/System functions

RESET

PDI_CLK Program and Debug Interface Clock pin

PDI_DATA Program and Debug Interface Data pin

T C K J TAG Tes t C lo ck

TDI JTAG Test Data In

T D O JTAG Te s t D a t a O u t

T M S JTAG Te s t M o d e S e l e c t

Reset pin

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XMEGA A3

30.2 Alternate Pin Functions

The tables below show the main and alternate pin functions for all pins on each port. They also show which peripheral that makes use of or enables the alternate pin function.

Table 30-1. Port A - Alternate functions

PORT A PIN # INTERRUPT ADCA POS ADCA NEG

GND 60

AVC C 61

PA0 62 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF

PA1 63 SYNC ADC1 ADC1 ADC1 AC1 AC1

PA2 64 SYNC/ASYNC ADC2 ADC2 ADC2 AC2

PA3 1 SYNC ADC3 ADC3 ADC3 AC3 AC3

PA4 2 SYNC ADC4 ADC4 ADC4 AC4

PA5 3 SYNC ADC5 ADC5 ADC5 AC5 AC5

PA6 4 SYNC ADC6 ADC6 ADC6 AC6

PA7 5 SYNC ADC7 ADC7 ADC7 AC7 AC0 OUT

ADAA

GAINPOS

ADCA

GAINNEG ACA POS ACA NEG ACA OUT REFA

Table 30-2. Port B - Alternate functions

PORT B PIN # INTERRUPT

PB0 6 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF

PB1 7 SYNC ADC1 ADC1 ADC1 AC1 AC1

PB2 8 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0

PB3 9 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1

PB4 10 SYNC ADC4 ADC4 ADC4 AC4 TMS

PB5 11 SYNC ADC5 ADC5 ADC5 AC5 AC5 TDI

PB6 12 SYNC ADC6 ADC6 ADC6 AC6 TCK

PB7 13 SYNC ADC7 ADC7 ADC7 AC7 AC0 OUT TDO

GND 14

VCC 15

ADCB

POS

ADCB

NEG

ADCB

GAINPOS

ADCB

GAINNEG ACB POS ACB NEG ACB OUT DACB REFB JTAG

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XMEGA A3

Table 30-3. Port C - Alternate functions

PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT

PC0 16 SYNC OC0A OC0ALS SDA

PC1 17 SYNC OC0B OC0AHS XCK0 SCL

PC2 18 SYNC/ASYNC OC0C OC0BLS RXD0

PC3 19 SYNC OC0D OC0BHS TXD0

PC4 20 SYNC OC0CLS OC1A SS

PC5 21 SYNC OC0CHS OC1B XCK1 MOSI

PC6 22 SYNC OC0DLS RXD1 MISO

PC7 23 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT

GND 24

VCC 25

Table 30-4. Port D - Alternate functions

PORT D PIN # INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID CLOCKOUT EVENTOUT

PD0 26 SYNC OC0A

PD1 27 SYNC OC0B XCK0

PD2 28 SYNC/ASYNC OC0C RXD0

PD3 29 SYNC OC0D TXD0

PD4 30 SYNC OC1A SS

PD5 31 SYNC OC1B XCK1 MOSI

PD6 32 SYNC RXD1 MISO

PD7 33 SYNC TXD1 SCK CLKOUT EVOUT

GND 34

VCC 35

Table 30-5. Port E - Alternate functions

PORT E PIN # INTERRUPT TCE0 TCE1 USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT TOSC

PE0 36 SYNC OC0A SDA

PE1 37 SYNC OC0B XCK0 SCL

PE2 38 SYNC/ASYNC OC0C RXD0

PE3 39 SYNC OC0D TXD0

PE4 40 SYNC OC1A SS

PE5 41 SYNC OC1B XCK1 MOSI

PE6 42 SYNC RXD1 MISO TOSC2

PE7 43 SYNC TXD1 SCK CLKOUT EVOUT TOSC1

GND 44

VCC 45

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Table 30-6. Port F - Alternate functions

PORT F PIN # INTERRUPT TCF0 USARTF0

PF0 46 SYNC OC0A

PF1 47 SYNC OC0B XCK0

PF2 48 SYNC/ASYNC OC0C RXD0

PF3 49 SYNC OC0D TXD0

PF4 50 SYNC

PF5 51 SYNC

PF6 54 SYNC

PF7 55 SYNC

GND 52

VCC 53

Table 30-7. Port R - Alternate functions

PORT R PIN # INTERRUPT PROGR XTAL

PDI 56 PDI_DATA

RESET 57 PDI_CLOCK

PRO 58 SYNC XTAL2

PR1 59 SYNC XTAL1

XMEGA A3

Table 30-8. ATxmega256/192/128/64A3 Boundary Scan Order

Bit Number Signal Name Module

149 PQ3.Bidir 148 PQ3.Control 147 PQ2.Bidir 146 PQ2.Control 145 PQ1.Bidir 144 PQ1.Control 143 PQ0.Bidir 142 PQ0.Control 141 PK7.Bidir 140 PK7.Control 139 PK6.Bidir 138 PK6.Control 137 PK5.Bidir 136 PK5.Control 135 PK4.Bidir 134 PK4.Control 133 PK3.Bidir 132 PK3.Control 131 PK2.Bidir 130 PK2.Control 129 PK1.Bidir 128 PK1.Control 127 PK0.Bidir 126 PK0.Control

PORT Q

PORT K

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Bit Number Signal Name Module

125 PJ7.Bidir 124 PJ7.Control 123 PJ6.Bidir 122 PJ6.Control 121 PJ5.Bidir 120 PJ5.Control 119 PJ4.Bidir 118 PJ4.Control 117 PJ3.Bidir 116 PJ3.Control 115 PJ2.Bidir 114 PJ2.Control 113 PJ1.Bidir 112 PJ1.Control 111 PJ0.Bidir 110 PJ0.Control 109 PH7.Bidir 108 PH7.Control 107 PH6.Bidir 106 PH6.Control 105 PH5.Bidir 104 PH5.Control 103 PH4.Bidir 102 PH4.Control 101 PH3.Bidir 100 PH3.Control 99 PH2.Bidir 98 PH2.Control 97 PH1.Bidir 96 PH1.Control 95 PH0.Bidir 94 PH0.Control 93 PF7.Bidir 92 PF7.Control 91 PF6.Bidir 90 PF6.Control 89 PF5.Bidir 88 PF5.Control 87 PF4.Bidir 86 PF4.Control 85 PF3.Bidir 84 PF3.Control 83 PF2.Bidir 82 PF2.Control 81 PF1.Bidir 80 PF1.Control 79 PF0.Bidir 78 PF0.Control 77 PE7.Bidir 76 PE7.Control 75 PE6.Bidir 74 PE6.Control 73 PE5.Bidir 72 PE5.Control 71 PE4.Bidir 70 PE4.Control 69 PE3.Bidir 68 PE3.Control 67 PE2.Bidir 66 PE2.Control 65 PE1.Bidir 64 PE1.Control 63 PE0.Bidir 62 PE0.Control

XMEGA A3

PORT J

PORT H

PORT F

PORT E

8068Q–AVR–02/10

Bit Number Signal Name Module

61 PD7.Bidir 60 PD7.Control 59 PD6.Bidir 58 PD6.Control 57 PD5.Bidir 56 PD5.Control 55 PD4.Bidir 54 PD4.Control 53 PD3.Bidir 52 PD3.Control 51 PD2.Bidir 50 PD2.Control 49 PD1.Bidir 48 PD1.Control 47 PD0.Bidir 46 PD0.Control 45 PC7.Bidir 44 PC7.Control 43 PC6.Bidir 42 PC6.Control 41 PC5.Bidir 40 PC5.Control 39 PC4.Bidir 38 PC4.Control 37 PC3.Bidir 36 PC3.Control 35 PC2.Bidir 34 PC2.Control 33 PC1.Bidir 32 PC1.Control 31 PC0.Bidir 30 PC0.Control 29 PB3.Bidir 28 PB3.Control 27 PB2.Bidir 26 PB2.Control 25 PB1.Bidir 24 PB1.Control 23 PB0.Bidir 22 PB0.Control 21 PA7.Bidir 20 PA7.Control 19 PA6.Bidir 18 PA6.Control 17 PA5.Bidir 16 PA5.Control 15 PA4.Bidir 14 PA4.Control 13 PA3.Bidir 12 PA3.Control 11 PA2.Bidir 10 PA2.Control 9 PA1.Bidir 8 PA1.Control 7 PA0.Bidir 6 PA0.Control 5 PR1.Bidir 4PR1.Control 3 PR0.Bidir 2PR0.Control 1 RESET.Observe_Only RESET 0 PDI_DATA.Observe_Only PDI Data

PORT D

PORT C

PORT B

PORT A

PORT R

XMEGA A3

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31. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in XMEGA A3. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual.

Base Address Name Description

0x0000 GPIO General Purpose IO Registers 0x0010 VPORT0 Virtual Port 0 0x0014 VPORT1 Virtual Port 1 0x0018 VPORT2 Virtual Port 2

0x001C VPORT3 Virtual Port 2

0x0030 CPU CPU 0x0040 CLK Clock Control 0x0048 SLEEP Sleep Controller 0x0050 OSC Oscillator Control 0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator 0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator 0x0070 PR Power Reduction 0x0078 RST Reset Controller 0x0080 WDT Watch-Dog Timer

0x0090 MCU MCU Control 0x00A0 PMIC Programmable MUltilevel Interrupt Controller 0x00B0 PORTCFG Port Configuration 0x00C0 AES AES Module

0x0100 DMA DMA Controller

0x0180 EVSYS Event System 0x01C0 NVM Non Volatile Memory (NVM) Controller

0x0200 ADCA Analog to Digital Converter on port A

0x0240 ADCB Analog to Digital Converter on port B

0x0320 DACB Digital to Analog Converter on port B

0x0380 ACA Analog Comparator pair on port A

0x0390 ACB Analog Comparator pair on port B

0x0400 RTC Real Time Counter

0x0480 TWIC Two Wire Interface on port C 0x04A0 TWIE Two Wire Interfaceon port E

0x0600 PORTA Port A

0x0620 PORTB Port B

0x0640 PORTC Port C

0x0660 PORTD Port D

0x0680 PORTE Port E 0x06A0 PORTF Port F 0x07E0 PORTR Port R

0x0800 TCC0 Timer/Counter 0 on port C

0x0840 TCC1 Timer/Counter 1 on port C

0x0880 AWEXC Advanced Waveform Extension on port C

0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08B0 USARTC1 USART 1 on port C 0x08C0 SPIC Serial Peripheral Interface on port C

0x08F8 IRCOM Infrared Communication Module

0x0900 TCD0 Timer/Counter 0 on port D

0x0940 TCD1 Timer/Counter 1 on port D

0x0990 HIRESD High Resolution Extension on port D 0x09A0 USARTD0 USART 0 on port D 0x09B0 USARTD1 USART 1 on port D 0x09C0 SPID Serial Peripheral Interface on port D 0x0A00 TCE0 Timer/Counter 0 on port E 0x0A40 TCE1 Timer/Counter 1 on port E 0x0A80 AWEXE Advanced Waveform Extensionon port E 0x0A90 HIRESE High Resolution Extension on port E 0x0AA0 USARTE0 USART 0 on port E 0x0AB0 USARTE1 USART 1 on oirt E 0x0AC0 SPIE Serial Peripheral Interface on port E 0x0B00 TCF0 Timer/Counter 0 on port F 0x0B90 HIRESF High Resolution Extension on port F 0x0BA0 USARTF0 USART 0 on port F

XMEGA A3

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XMEGA A3

32. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

Arithmetic and Logic Instructions

ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1

ADC Rd, Rr Add with Carr y Rd ← Rd + Rr + C Z,C,N,V,S,H 1

ADIW Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2

SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1

SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1

SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1

SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1

SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1

ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1

OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1

ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1

EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1

COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1

NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1

INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1

DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1

SER Rd Set Register Rd ← $FF None 1

MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2

MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2

MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2

FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2

FMULS Rd,Rr Fractional Multiply Signed R1:R0

FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2

DES K Data Encryption if (H = 0) then R15:R0

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC(15:0)

EIJMP Extended Indirect Jump to (Z) PC(15:0)

JMP k Jump PC ← k None 3

RCALL k Relative Call Subroutine PC ← PC + k + 1 None 2 / 3

ICALL Indirect Call to (Z) PC(15:0)

EICALL Extended Indirect Call to (Z) PC(15:0)

else if (H = 1) then R15:R0←←

Branch Instructions

PC(21:16)←←Z,0

PC(21:16)←←Z,EIND

PC(21:16)←←Z,0

PC(21:16)←←Z,EIND

← Rd x Rr<<1 (SS) Z,C 2

Encrypt(R15:R0, K) Decrypt(R15:R0, K)

None 2

None 2 / 3

None 3

1/2

(1)

8068Q–AVR–02/10

XMEGA A3

Mnemonics Operands Description Operation Flags #Clocks

CALL k call Subroutine PC ← k None 3 / 4

RET Subroutine Return PC ← STACK None 4 / 5

RETI Interrupt Return PC ← STACK I 4 / 5

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None 2 / 3 / 4

SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None 2 / 3 / 4

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2

BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1 / 2

BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1 / 2

Data Transfer Instructions

MOV Rd, Rr Copy Register Rd ← Rr None 1

MOVW Rd, Rr Copy Register Pair Rd+1:Rd ← Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd ← K None 1

LDS Rd, k Load Direct from data space Rd ← (k) None 2

LD Rd, X Load Indirect Rd ← (X) None 1

LD Rd, X+ Load Indirect and Post-Increment RdX←←(X)

LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1,

Rd ← (X)←←

X + 1

X - 1 (X)

None 1

None 2

LD Rd, Y Load Indirect Rd ← (Y) ← (Y) None 1

LD Rd, Y+ Load Indirect and Post-Increment RdY←←(Y)

Y + 1

None 1

(1)

(1)(2)

8068Q–AVR–02/10

XMEGA A3

Mnemonics Operands Description Operation Flags #Clocks

LD Rd, -Y Load Indirect and Pre-Decrement YRd←←Y - 1

(Y)

None 2

LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 1

LD Rd, Z+ Load Indirect and Post-Increment RdZ←←(Z),

LD Rd, -Z Load Indirect and Pre-Decrement ZRd←←Z - 1,

Z+1

(Z)

None 1

None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

STS k, Rr Store Direct to Data Space (k) ← Rd None 2

ST X, Rr Store Indirect (X) ← Rr None 1

ST X+, Rr Store Indirect and Post-Increment (X)X←←Rr,

ST -X, Rr Store Indirect and Pre-Decrement X

(X)←←

X + 1

X - 1, Rr

None 1

None 2

ST Y, Rr Store Indirect (Y) ← Rr None 1

ST Y+, Rr Store Indirect and Post-Increment (Y)Y←←Rr,

ST -Y, Rr Store Indirect and Pre-Decrement Y

(Y)←←

Y + 1

Y - 1, Rr

None 1

None 2

STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 1

ST Z+, Rr Store Indirect and Post-Increment (Z)Z←←Rr

Z + 1

None 1

ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z - 1 None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Increment RdZ←←(Z),

Z + 1

None 3

ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3

ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3

ELPM Rd, Z+ Extended Load Program Memory and Post-

Increment

RdZ←←(RAMPZ:Z),

Z + 1

None 3

SPM Store Program Memory (RAMPZ:Z) ← R1:R0 None -

SPM Z+ Store Program Memory and Post-Increment

by 2

(RAMPZ:Z)Z←←R1:R0,

Z + 2

None -

IN Rd, A In From I/O Location Rd ← I/O(A) None 1

OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 1

POP Rd Pop Register from Stack Rd ← STACK None 2

Bit and Bit-test Instructions

LSL Rd Logical Shift Left Rd(n+1)

LSR Rd Logical Shift Right Rd(n)

Rd(0)

Rd(7)

Rd(n),

←

Rd(7)

←

Rd(n+1),

←

Rd(0)

←

Z,C,N,V,H 1

Z,C,N,V 1

(1)(2)

(1)

8068Q–AVR–02/10

XMEGA A3

Mnemonics Operands Description Operation Flags #Clocks

ROL Rd Rotate Left Through Carry Rd(0)

ROR Rd Rotate Right Through Carry Rd(7)

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1

BSET s Flag Set SREG(s) ← 1SREG(s)1

BCLR s Flag Clear SREG(s) ← 0SREG(s)1

SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1

CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0C1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0N1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0Z1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0I1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0S1

SEV Set Two’s Complement Overflow V ← 1V1

CLV Clear Two’s Complement Overflow V ← 0V1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0T1

SEH Set Half Carry Flag in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0H1

MCU Control Instructions

BREAK Break (See specific descr. for BREAK) None 1

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep) None 1

WDR Watchdog Reset (see specific descr. for WDR) None 1

Rd(n+1)

Rd(n)

←

Rd(n),

←

Rd(7)

←

Rd(n+1),

←

Rd(0)

←

Z,C,N,V,H 1

Z,C,N,V 1

8068Q–AVR–02/10

Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid

for accesses via the external RAM interface.

2. One extra cycle must be added when accessing Internal SRAM.

33. Packaging information

33.1 64A

PIN 1

PIN 1 IDENTIFIER

XMEGA A3

E1 E

0°~7°

Notes:

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

NOM

MAX

NOTE

8068Q–AVR–02/10

2325 Orchard Parkway

San Jose, CA 95131

TITLE

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

10/5/2001

DRAWING NO.

64A

REV.

33.2 64M2

2325 Orchard Parkway San Jose, CA 95131

TITLE

DRAWING NO.

REV.

64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

64M2

5/25/06

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

NOM

MAX

NOTE

A 0.80 0.90 1.00

A1 – 0.02 0.05

b 0.18 0.25 0.30

D2 7.50 7.65 7.80

8.90 9.00 9.10

E2 7.50 7.65 7.80

e 0.50 BSC

L 0.35 0.40 0.45

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Marked Pin# 1 ID

SEATING PLANE

0.08

1 2 3

K 0.20 0.27 0.40

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Pin #1 Corner

Pin #1 Triangle

Pin #1 Chamfer (C 0.30)

Option A

Option B

Pin #1 Notch (0.20 R)

Option C

Note:

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

7.65 mm Exposed Pad, Micro Lead Frame Package (MLF)

XMEGA A3

8068Q–AVR–02/10

34. Electrical Characteristics

34.1 Absolute Maximum Ratings*

XMEGA A3

Operating Temperature.................................. -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

Storage Temperature ..................................... -65°C to +150°C

age to the device. This is a stress rating only and functional operation of the device at these or

Voltage on any Pin with respect to Ground..-0.5V to V

+0.5V

other conditions beyond those indicated in the operational sections of this specification is not

Maximum Operating Voltage ............................................ 3.6V

implied. Exposure to absolute maximum rating conditions for extended periods may affect

DC Current per I/O Pin ............................................... 20.0 mA

DC Current

and GND Pins................................ 200.0 mA

device reliability.

34.2 DC Characteristics

Table 34-1. Current Consumption

Symbol Parameter Condition Min Typ Max Units

= 1.8V 25

32 kHz, Ext. Clk

1 MHz, Ext. Clk

Active

2 MHz, Ext. Clk

Power Supply Current

(1)

32 MHz, Ext. Clk V

32 kHz, Ext. Clk

1 MHz, Ext. Clk

Idle

2 MHz, Ext. Clk

32 MHz, Ext. Clk V

All Functions Disabled V

All Functions Disabled, T = 85°C V

Power-down mode

ULP, WDT, Sampled BOD

ULP, WDT, Sampled BOD, T=85°C V

RTC 1 kHz from Low Power 32 kHz

Power-save mode

TOSC

RTC from Low Power 32 kHz TOSC V

Reset Current Consumption

without Reset pull-up resistor current VCC = 3.0V 1300

= 3.0V 71

= 1.8V 317

= 3.0V 697

= 1.8V 613 800

= 3.0V 1340 1800

= 3.0V 15.7 18 mA

= 1.8V 3.6

= 3.0V 6.9

= 1.8V 112

= 3.0V 215

= 1.8V 224 350

= 3.0V 430 650

= 3.0V 6.9 8 mA

= 3.0V 0.1

= 3.0V 1.75 5

= 1.8V 1

= 3.0V 1

= 3.0V 2.7 10

= 1.8V 0.55

= 3.0V 0.65

= 3.0V 1.16

µA

8068Q–AVR–02/10

XMEGA A3

Table 34-1. Current Consumption

Symbol Parameter Condition Min Typ Max Units

Module current consumption

RC32M 460

RC32M w/DFLL Internal 32.768 kHz oscillator as DFLL source 594

RC2M 101

RC2M w/DFLL Internal 32.768 kHz oscillator as DFLL source 134

RC32K 27

PLL Multiplication factor = 10x 202

(2)

Watchdog normal mode 1

µA

BOD Continuous mode 128

BOD Sampled mode 1

Internal 1.00 V ref 80

Temperature reference 74

RTC with int. 32 kHz RC as

source

No prescaling 27

RTC with ULP as source No prescaling 1

ADC 250 kS/s - Int. 1V Ref 2.9

DAC Normal Mode 1000 kS/s, Single channel, Int. 1V Ref 1.8

DAC Low-Power Mode 1000 KS/s, Single channel, Int. 1V Ref 0.95

DAC S/H Normal Mode Int.1.1V Ref, Refresh 16CLK 2.9

DAC Low-Power Mode S/H Int. 1.1V Ref, Refresh 16CLK 1.1

AC High-speed 195

AC Low-power 103

USART Rx and Tx enabled, 9600 BAUD 5.4

µA

DMA 128

Timer/Counter Prescaler DIV1 20

AES 223

Note: 1. All Power Reduction Registers set. Typical numbers measured at T = 25°C if nothing else is specified.

2. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V

8068Q–AVR–02/10

=3.0V, Clk

= 1 MHz External clock with no prescaling, T = 25°C.

SYS

34.3 Operating Voltage and Frequency

Table 34-2. Operating voltage and frequency

Symbol Parameter Condition Min Typ Max Units

Clk

CPU

The maximum CPU clock frequency of the XMEGA A3 devices is depending on VCC. As shown in Figure 34-1 on page 65 the Frequency vs. V

Figure 34-1. Maximum Frequency vs. Vcc

CPU clock frequency

MHz

= 1.6V 0 12

= 1.8V 0 12

= 2.7V 0 32

= 3.6V 0 32

curve is linear between 1.8V < VCC<2.7V.

XMEGA A3

MHz

1.6

1.8

Safe Operating Area

2.7

3.6

8068Q–AVR–02/10

XMEGA A3

34.4 Flash and EEPROM Memory Characteristics

Table 34-3. Endurance and Data Retention

Symbol Parameter Condition Min Typ Max Units

Write/Erase cycles

Flash

Data retention

Write/Erase cycles

EEPROM

Data retention

25°C 10K

85°C 10K

25°C 100

55°C 25

25°C 80K

85°C 30K

25°C 100

55°C 25

Table 34-4. Programming time

Symbol Parameter Condition Min Typ

(2)

Chip Erase Flash, EEPROM

Page Erase 6

Flash

EEPROM

Page Write 6

Page WriteAutomatic Page Erase and Write 12

Page Erase 6

Page Write 6

Page WriteAutomatic Page Erase and Write 12

and SRAM Erase 40

Cycle

Year

Cycle

Year

(1)

Max Units

Notes: 1. Programming is timed from the internal 2 MHz oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

8068Q–AVR–02/10

XMEGA A3

34.5 ADC Characteristics

Table 34-5. ADC Characteristics

Symbol Parameter Condition Min Typ Max Units

RES Resolution Programmable: 8/12 8 12 12 Bits

INL Integral Non-Linearity 500 ksps -5 5 LSB

DNL Differential Non-Linearity 500 ksps < ±1 LSB

Gain Error < ±10 mV

Offset Error < ±2 mV

ADC

ADC Clock frequency Max is 1/4 of Peripheral Clock 2000 kHz

clk

Conversion rate 2000 ksps

Conversion time (propagation delay)

Sampling Time 1/2 ADC

(RES+2)/2+GAIN RES = 8 or 12, GAIN = 0 or 1

cycle 0.25 uS

clk

578

Conversion range 0 VREF V

VREF Reference voltage 1.0 V

-0.6V V

Input bandwidth kHz

INT1V Internal 1.00V reference 1.00 V

INTVCC Internal V

SCALEDVCC

AREF

Scaled internal VCC/10 input VCC/10 V

Reference input resistance > 10 MΩ

/1.6 VCC/1.6 V

Start-up time µs

Internal input sampling speed

Temp. sensor, VCC/10, Bandgap

100 ksps

Table 34-6. ADC Gain Stage Characteristics

Symbol Parameter Condition Min Typ Max Units

Gain error 1 to 64 gain < ±1 %

Offset error < ±1

Vrms Noise level at input 64x gain

VREF = Int. 1V 0.12

VREF = Ext. 2V 0.06

ADC

cycles

clk

8068Q–AVR–02/10

Clock rate Same as ADC 1000 kHz

XMEGA A3

34.6 DAC Characteristics

Table 34-7. DAC Characteristics

Symbol Parameter Condition Min Typ Max Units

INL Integral Non-Linearity V

DNL Differential Non-Linearity V

clk

Conversion rate 1000 ksps

AREF External reference voltage 1.1 AV

Reference input impedance >10 MΩ

DC output impedance kΩ

Max output voltage R

Min output voltage R

Offset factory calibration accuracy

Gain factory calibration accuracy

= 1.6-3.6V VREF = Ext. ref 5

VREF = Ext. ref <±1

= 1.6-3.6V

=100kΩ

load

=100kΩ 0.015

load

VREF= AV

Continues mode, VCC=3.0V, VREF = Int 1.00V, T=85°C

AVCC*0.98

±0.5

±2.5

-0.6 V

LSB

34.7 Analog Comparator Characteristics

Table 34-8. Analog Comparator Characteristics

Symbol Parameter Condition Min Typ Max Units

Input Offset Voltage VCC = 1.6 - 3.6V <±10 mV

off

Input Leakage Current VCC = 1.6 - 3.6V < 1000 pA

Hysteresis, No VCC = 1.6 - 3.6V 0 mV

Hysteresis, Small VCC = 1.6 - 3.6V mode = HS 20

Hysteresis, Large VCC = 1.6 - 3.6V mode = HS 40

= 3.0V, T= 85°C mode = HS 100

Propagation delay

= 1.6 - 3.6V mode = HS 110

= 1.6 - 3.6V mode = LP 175

hys1

hys2

hys3

delay

34.8 Bandgap Characteristics

Table 34-9. Bandgap Voltage Characteristics

Symbol Parameter Condition Min Typ Max Units

Bandgap startup time

Bandgap voltage 1.1

As reference for ADC or DAC 1 Clk_PER + 2.5µs

As input to AC or ADC 1.5

nsV

µs

ADC/DAC ref

Variation over voltage and temperature V

8068Q–AVR–02/10

T= 85°C, After calibration 0.99 1 1.01

= 1.6 - 3.6V, T = -40°C to 85°C±5 %

34.9 Brownout Detection Characteristics

XMEGA A3

Table 34-10. Brownout Detection Characteristics

(1)

Symbol Parameter Condition Min Typ Max Units

BOD level 0 falling Vcc 1.62

BOD level 1 falling Vcc 1.9

BOD level 2 falling Vcc 2.17

BOD level 3 falling Vcc 2.43

BOD level 4 falling Vcc 2.68

BOD level 5 falling Vcc 2.96

BOD level 6 falling Vcc 3.22

BOD level 7 falling Vcc 3.49

Hysteresis BOD level 0-5 1 %

Note: 1. BOD is calibrated to BOD level 0 at 85°C, and BOD level 0 is the default level.

34.10 PAD Characteristics

Table 34-11. PAD Characteristics

Symbol Parameter Condition Min Typ Max Units

= 2.4 - 3.6V 0.7*V

RST

Input High Voltage

Input Low Voltage

Output Low Voltage GPIO

Output High Voltage GPIO

Input Leakage Current I/O pin <0.001 1

I/O pin Pull/Buss keeper Resistor 20

Reset pin Pull-up Resistor 20

= 1.6 - 2.4V 0.8*V

= 2.4 - 3.6V -0.5 0.3*V

VCC = 1.6 - 2.4V -0.5 0.2*V

= 15 mA, VCC = 3.3V 0.4 0.76

= 10 mA, VCC = 3.0V 0.3 0.64

= 5 mA, VCC = 1.8V 0.2 0.46

= -8 mA, VCC = 3.3V 2.6 2.9

= -6 mA, VCC = 3.0V 2.1 2.7

= -2 mA, VCC = 1.8V 1.4 1.6

VCC+0.5

µA

kΩ

Input hysteresis 0.5 V

8068Q–AVR–02/10

XMEGA A3

34.11 POR Characteristics

Table 34-12. Power-on Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

POT-

POT+

34.12 Reset Characteristics

Table 34-13. Reset Characteristics

Symbol Parameter Condition Min Typ Max Units

POR threshold voltage falling Vcc 1

POR threshold voltage rising Vcc 1.45

Minimum reset pulse width 90 ns

Reset threshold voltage

VCC = 2.7 - 3.6V 0.45*V

= 1.6 - 2.7V 0.42*V

34.13 Oscillator Characteristics

Table 34-14. Internal 32.768 kHz Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Accuracy

T = 85°C, V After production calibration

Table 34-15. Internal 2 MHz Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Accuracy

T = 85°C, V After production calibration

DFLL Calibration step size T = 25°C, V

Table 34-16. Internal 32 MHz Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Accuracy

DFLL Calibration stepsize T = 25°C, V

T = 85°C, V After production calibration

= 3V,

= 3V 0.15

= 3V,

= 3V 0.2

-0.5 0.5 %

-1.5 1.5

Table 34-17. Internal 32 kHz, ULP Oscillator Characteristics

Symbol Parameter Condition Min Typ Max Units

Output frequency 32 kHz ULP OSC T = 85°C, V

8068Q–AVR–02/10

= 3.0V 26 kHz

Table 34-18. Maximum load capacitance (CL) and ESR recommendation for 32.768 kHz Crystal

Crystal CL [pF] Max ESR [kΩ]

6.5 60

935

Table 34-19. Device wake-up time from sleep

Symbol Parameter Condition

Int. 32.768 kHz RC 130

Idle Sleep, Standby and Extended Standby sleep mode

Int. 2 MHz RC 2

Ext. 2 MHz Clock 2

Int. 32 MHz RC 0.17

Int. 32.768 kHz RC 320

(1)

Min Typ

XMEGA A3

(2)

Max Units

µS

Power-save and Power-down Sleep mode

Notes: 1. Non-prescaled System Clock source.

2. Time from pin change on external interrupt pin to first available clock cycle. Additional interrupt response time is minimum 5 system clock source cycles.

Int. 2 MHz RC 10.3

Ext. 2 MHz Clock 4.5

Int. 32 MHz RC 5.8

8068Q–AVR–02/10

35. Typical Characteristics

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

100

200

300

400

500

600

700

800

900

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency [MHz]

[uA]

3.3 V

3.0 V

2.7 V

048 12 16 20 24 28 32

Frequency [MHz]

[mA]

2.2 V

1.8 V

35.1 Active Supply Current

Figure 35-1. Active Supply Current vs. Frequency

= 0 - 1.0 MHz External clock, T = 25°C

SYS

XMEGA A3

Figure 35-2. Active Supply Current vs. Frequency

= 1 - 32 MHz External clock, T = 25°C

SYS

8068Q–AVR–02/10

Figure 35-3. Active Supply Current vs. Vcc

85 °C 25 °C

-40 °C

100

200

300

400

500

600

700

800

900

1000

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[uA]

85 °C

25 °C

-40 °C

100

120

140

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[uA]

= 1.0 MHz External Clock

SYS

XMEGA A3

Figure 35-4. Active Supply Current vs. VCC

= 32.768 kHz internal RC

SYS

8068Q–AVR–02/10

Figure 35-5. Active Supply Current vs. Vcc

85 °C

25 °C

-40 °C

200

400

600

800

1000

1200

1400

1600

1800

2000

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[uA]

85 °C

25 °C

-40 °C

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[mA]

= 2.0 MHz internal RC

SYS

XMEGA A3

Figure 35-6. Active Supply Current vs. Vcc

= 32 MHz internal RC prescaled to 8 MHz

SYS

8068Q–AVR–02/10

Figure 35-7. Active Supply Current vs. Vcc

85 °C

25 °C

-40 °C

2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6

[V]

[mA]

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

100

150

200

250

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Frequency [MHz]

[uA]

= 32 MHz internal RC

SYS

XMEGA A3

35.2 Idle Supply Current

Figure 35-8. Idle Supply Current vs. Frequency

= 0 - 1.0 MHz, T = 25°C

SYS

8068Q–AVR–02/10

Figure 35-9. Idle Supply Current vs. Frequency

3.3 V

3.0 V

2.7 V

048 12 16 20 24 28 32

Frequency [MHz]

[mA]

1.8 V

2.2 V

85 °C 25 °C

-40 °C

100

150

200

250

300

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[uA]

= 1 - 32 MHz, T = 25°C

SYS

XMEGA A3

Figure 35-10. Idle Supply Current vs. Vcc

= 1.0 MHz External Clock

SYS

8068Q–AVR–02/10

Figure 35-11. Idle Supply Current vs. Vcc

85 °C

25 °C

-40 °C

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[uA]

85 °C

25 °C

-40 °C

100

200

300

400

500

600

700

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[uA]

= 32.768 kHz internal RC

SYS

XMEGA A3

Figure 35-12. Idle Supply Current vs. Vcc

= 2.0 MHz internal RC

SYS

8068Q–AVR–02/10

Figure 35-13. Idle Supply Current vs. Vcc

85 °C

25 °C

-40 °C

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

[mA]

85 °C

25 °C

-40 °C

2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6

[V]

[mA]

= 32 MHz internal RC prescaled to 8 MHz

SYS

XMEGA A3

Figure 35-14. Idle Supply Current vs. Vcc

= 32 MHz internal RC

SYS

8068Q–AVR–02/10

35.3 Power-down Supply Current

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

[uA]

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

0.5

1.5

2.5

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

[uA]

Figure 35-15. Power-down Supply Current vs. Temperature

XMEGA A3

Figure 35-16. Power-down Supply Current vs. Temperature

With WDT and sampled BOD enabled.

8068Q–AVR–02/10

35.4 Power-save Supply Current

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

0.5

1.5

2.5

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

[uA]

85 °C

25 °C

-40 °C

100

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

RESET

[V]

RESET

[uA]

Figure 35-17. Power-save Supply Current vs. Temperature

With WDT, sampled BOD and RTC from ULP enabled

XMEGA A3

35.5 Pin Pull-up

Figure 35-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage

VCC = 1.8V

8068Q–AVR–02/10

Figure 35-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage

85 °C

25 °C

-40 °C

100

120

140

160

0 0.5 1 1.5 2 2.5 3

RESET

[V]

RESET

[uA]

85 °C

25 °C

-40 °C

100

120

140

160

180

0 0.5 1 1.5 2 2.5 3

RESET

[V]

RESET

[uA]

VCC = 3.0V

XMEGA A3

Figure 35-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage

VCC = 3.3V

8068Q–AVR–02/10

35.6 Pin Output Voltage vs. Sink/Source Current

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

-12 -10 -8 -6 -4 -2 0

[mA]

[V]

85 °C

25 °C

-40 °C

0.5

1.5

2.5

3.5

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0

[mA]

[V]

Figure 35-21. I/O Pin Output Voltage vs. Source Current

Vcc = 1.8V

XMEGA A3

Figure 35-22. I/O Pin Output Voltage vs. Source Current

Vcc = 3.0V

8068Q–AVR–02/10

Figure 35-23. I/O Pin Output Voltage vs. Source Current

85 °C

25 °C

-40 °C

0.5

1.5

2.5

3.5

-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0

[mA]

[V]

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

02468 10 12 14 16 18 20

[mA]

[V]

25°C85°C

Vcc = 3.3V

XMEGA A3

Figure 35-24. I/O Pin Output Voltage vs. Sink Current

Vcc = 1.8V

8068Q–AVR–02/10

Figure 35-25. I/O Pin Output Voltage vs. Sink Current

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

02468 10 12 14 16 18 20

[mA]

[V]

85 °C

25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

02468 10 12 14 16 18 20

[mA]

[V]

Vcc = 3.0V

XMEGA A3

Figure 35-26. I/O Pin Output Voltage vs. Sink Current

Vcc = 3.3V

8068Q–AVR–02/10

35.7 Pin Thresholds and Hysteresis

85 °C

25 °C

-40 °C

0.5

1.5

2.5

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

threshold

[V]

85 °C 25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

threshold

[V]

XMEGA A3

Figure 35-27. I/O Pin Input Threshold Voltage vs. V

VIH - I/O Pin Read as “1”

Figure 35-28. I/O Pin Input Threshold Voltage vs. V

VIL - I/O Pin Read as “0”

8068Q–AVR–02/10

XMEGA A3

85 °C 25 °C

-40 °C

0.1

0.2

0.3

0.4

0.5

0.6

0.7

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

threshold

[V]

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

THRESHOLD

[V]

Figure 35-29. I/O Pin Input Hysteresis vs. V

Figure 35-30. Reset Input Threshold Voltage vs. V

VIH - I/O Pin Read as “1”

8068Q–AVR–02/10

XMEGA A3

85 °C

25 °C

-40 °C

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

THRESHOLD

[V]

Rising Vcc

Falling Vcc

1.61

1.62

1.63

1.64

1.65

1.66

1.67

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

BOT

[V]

Figure 35-31. Reset Input Threshold Voltage vs. V

35.8 Bod Thresholds

Figure 35-32. BOD Thresholds vs. Temperature

VIL - I/O Pin Read as “0”

BOD Level = 1.6V

8068Q–AVR–02/10

Figure 35-33. BOD Thresholds vs. Temperature

Rising Vcc

Falling Vcc

2.9

2.92

2.94

2.96

2.98

3.02

3.04

3.06

-40 -30 -20 -10 0 10 20 30 40 50 60 70 8090

Temperature [°C]

BOT

[V]

0326496128 160 192 224 256

RC32KCAL[7..0]

0.05 %

0.20 %

0.35 %

0.50 %

0.65 %

0.80 %

Step size: f [kHz]

BOD Level = 2.9V

XMEGA A3

35.9 Oscillators and Wake-up Time

35.9.1 Internal 32.768 kHz Oscillator

Figure 35-34. Internal 32.768 kHz Oscillator Calibration Step Size

T = -40 to 85°C, VCC= 3V

8068Q–AVR–02/10

35.9.2 Internal 2 MHz Oscillator

-0.30 %

-0.20 %

-0.10 %

0.00 %

0.10 %

0.20 %

0.30 %

0.40 %

0.50 %

0163248 64 8096112128

DFLLRC2MCALA

Step size: f [MHz]

0.00 %

0.50 %

1.00 %

1.50 %

2.00 %

2.50 %

3.00 %

0 8 16 24 32 40 48 56 64

DFLLRC2MCALB

Step size: f [MHz]

Figure 35-35. Internal 2 MHz Oscillator CALA Calibration Step Size

XMEGA A3

T = -40 to 85°C, VCC= 3V

Figure 35-36. Internal 2 MHz Oscillator CALB Calibration Step Size

T = -40 to 85°C, VCC= 3V

8068Q–AVR–02/10

35.9.3 Internal 32 MHZ Oscillator

-0.20 %

-0.10 %

0.00 %

0.10 %

0.20 %

0.30 %

0.40 %

0.50 %

0.60 %

0163248 64 80 96 112 128

DFLLRC32MCALA

Step size: f [MHz]

0.00 %

0.50 %

1.00 %

1.50 %

2.00 %

2.50 %

3.00 %

0 8 16 24 32 40 48 56 64

DFLLRC32MCALB

Step size: f [MHz]

Figure 35-37. Internal 32 MHz Oscillator CALA Calibration Step Size

XMEGA A3

T = -40 to 85°C, VCC= 3V

Figure 35-38. Internal 32 MHz Oscillator CALB Calibration Step Size

T = -40 to 85°C, VCC= 3V

8068Q–AVR–02/10

35.10 Module current consumption

85 °C

25 °C

-40 °C

100

120

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

Module current consumption [uA]

85 °C

25 °C

-40 °C

100

200

300

400

500

600

700

0.4 0.6 0.8 1 1.2 1.4 1.6

[V]

[uA]

Figure 35-39. AC current consumption vs. Vcc

Low-power Mode

XMEGA A3

Figure 35-40. Power-up current consumption vs. Vcc

8068Q–AVR–02/10

35.11 Reset Pulsewidth

85 °C 25 °C

-40 °C

100

120

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

RST

[ns]

25 °C

1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

[V]

MAX

[MHz]

Figure 35-41. Minimum Reset Pulse Width vs. Vcc

XMEGA A3

35.12 PDI Speed

Figure 35-42. PDI Speed vs. Vcc

8068Q–AVR–02/10

36. Errata

36.1 ATxmega256A3

36.1.1 rev. B

XMEGA A3

Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

•

• ADC gain stage output range is limited to 2.4V

• Sampled BOD in Active mode will cause noise when bandgap is used as reference

• Bandgap measurement with the ADC is non-functional when V

• BOD will be enabled after any reset

• Writing EEPROM or Flash while reading any of them will not work

ADC has increased INL error for some operating conditions

•

• DAC has increased INL or noise for some operating conditions

• VCC voltage scaler for AC is non-linear

• Maximum operating frequency below 1.76V is 8 MHz

• Inverted I/O enable does not affect Analog Comparator Output

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

If the bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for the another AC, the first comparator will be affected for up to 1 us and could potentially give a wrong comparison result.

is below 2.7V

Problem fix/Workaround

If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them.

2. ADC gain stage output range is limited to 2.4 V

The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of:

– 1x gain: 2.4 V

– 2x gain: 1.2 V

– 4x gain: 0.6 V

– 8x gain: 300 mV

– 16x gain: 150 mV

– 32x gain: 75 mV

– 64x gain: 38 mV

Problem fix/Workaround

Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V.

8068Q–AVR–02/10

3. Sampled BOD in Active mode will cause noise when bandgap is used as reference

Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator.

XMEGA A3

Problem fix/Workaround

If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode.

4. Bandgap measurement with the ADC is non-functional when V

The ADC cannot be used to do bandgap measurements when V

is below 2.7V

is below 2.7V.

Problem fix/Workaround

If internal voltages must be measured when V

is below 2.7V, measure the internal 1.00V

reference instead of the bandgap.

5. BOD will be enabled after any reset

If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled.

Problem fix/Workaround

Do not set the BOD level higher than VCC even if the BOD is not used.

6. Writing EEPROM or Flash while reading any of them will not work

The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode.

Problem fix/Workaround

Enter IDLE sleep mode within 2.5 uS (Five 2 MHz clock cycles and 80 32 MHz clock cycles) after starting an EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7 mS after the erase or write operation has started, or 13 mS after atomic erase-and-write operation has started, and then enter IDLE sleep mode.

ADC has increased INL error for some operating conditions

Some ADC configurations or operating condition will result in increased INL error.

In differential mode INL is increased to:

– 6 LSB for sample rates above 1 Msps, and up to 8 LSB for 2 Msps sample rate.

– 6 LSB for reference voltage below 1.1V when VCC is above 3.0V.

– 20 LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.

In single ended mode, the INL is increased up to a factor of 3 for the conditions above.

Problem fix/Workaround

None, avoid using the ADC in the above configurations in order to prevent increased INL error.

DAC has increased INL or noise for some operating conditions

Some DAC configurations or operating condition will result in increased output error.

– INL error is increased up to 35 LSB when VCC < 2.0V

– Enabling Sample and Hold, will increase noise and reduce resolution below 8 bit

8068Q–AVR–02/10

XMEGA A3

Problem fix/Workaround

None, avoid using the DAC in the above configurations in order to prevent increased INL error.

9. VCC voltage scaler for AC is non-linear

The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.

Problem fix/Workaround

Use external voltage input for the analog comparator if accurate voltage levels are needed.

10. Maximum operating frequency below 1.76V is 8 MHz

To ensure correct operation, the maximum operating frequency below 1.76V VCC is 8 MHz.

Problem fix/Workaround

None, avoid running the device outside this frequency and voltage limitation.

11. Inverted I/O enable does not affect Analog Comparator Output

The inverted I/O pin function does not affect the Analog Comparator output function.

Problem fix/Workarund

Configure the analog comparator setup to give a inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and externel inverter to change polarity of Analog Comparator Output.

36.1.2 rev. A

•

Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

• ADC gain stage output range is limited to 2.4V

• Sampled BOD in Active mode will cause noise when bandgap is used as reference

• Flash Power Reduction Mode can not be enabled when entering sleep mode

• JTAG enable does not override Analog Comparator B output

• Bandgap measurement with the ADC is non-functional when V

is below 2.7V

• DAC refresh may be blocked in S/H mode

• BOD will be enabled after any reset

• Both DFLLs and both oscillators has to be enabled for one to work

• Operating frequency and voltage limitations

• Inverted I/O enable does not affect Analog Comparator Output

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

Problem fix/Workaround

If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them.

8068Q–AVR–02/10

XMEGA A3

2. ADC gain stage output range is limited to 2.4 V

– 1x gain: 2.4 V

– 2x gain: 1.2 V

– 4x gain: 0.6 V

– 8x gain: 300 mV

– 16x gain: 150 mV

– 32x gain: 75 mV

– 64x gain: 38 mV

Problem fix/Workaround

Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V.

3. Sampled BOD in Active mode will cause noise when bandgap is used as reference

Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator.

Problem fix/Workaround

If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode.

4. Flash Power Reduction Mode can not be enabled when entering sleep mode

If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only wake up on every fourth wake-up request.

If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles.

Problem fix/Workaround

Disable Flash Power Reduction mode before entering sleep mode.

5. JTAG enable does not override Analog Comparator B output

When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT on pin 7 if this is enabled.

Problem fix/Workaround

AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator output for ACA when JTAG is used, or use the PDI as debug interface.

6. Bandgap measurement with the ADC is non-functional when V

The ADC cannot be used to do bandgap measurements when V

is below 2.7V

is below 2.7V.

Problem fix/Workaround

If internal voltages must be measured when V

is below 2.7V, measure the internal 1.00V

reference instead of the bandgap.

8068Q–AVR–02/10

XMEGA A3

MHz

3.6

2.4

Safe operating

area

7. DAC refresh may be blocked in S/H mode

If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel.

Problem fix/Workarund

When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh.

8 BOD will be enabled after any reset

Problem fix/Workaround

Do not set the BOD level higher than VCC even if the BOD is not used.

9 Both DFLLs and both oscillators has to be enabled for one to work

In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscillators, the DFLL for both oscillators and both oscillators has to be enabled for one to work.

Problem fix/Workaround

Enabled both the DFLLs and both oscillators when using automtics runtime calibartion for one of the internal oscillators.

10 Operating Frequency and Voltage Limitation

To ensure correct operation, there is a limit on operating frequnecy and voltage. Figure 36-1

on page 97 shows the safe operating area.

Figure 36-1. Operating Frequnecy and Voltage Limitation

8068Q–AVR–02/10

Problem fix/Workaround

None, avoid using the device outside these frequnecy and voltage limitations.

11. Inverted I/O enable does not affect Analog Comparator Output

The inverted I/O pin function does not affect the Analog Comparator output function.

Problem fix/Workarund

36.2 ATxmega192A3, ATxmega128A3, ATxmega64A3

36.2.1 rev. B

•

Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

• ADC gain stage output range is limited to 2.4V

• Sampled BOD in Active mode will cause noise when bandgap is used as reference

• Bandgap measurement with the ADC is non-functional when V

• BOD will be enabled after any reset

• Writing EEPROM or Flash while reading any of them will not work

• ADC has increased INL error for some operating conditions

• DAC has increased INL or noise for some operating conditions

• VCC voltage scaler for AC is non-linear

• Maximum operating frequency below 1.76V is 8 MHz

• Inverted I/O enable does not affect Analog Comparator Output

is below 2.7V

XMEGA A3

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously

Problem fix/Workaround

If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them.

2. ADC gain stage output range is limited to 2.4 V

– 1x gain: 2.4 V

– 2x gain: 1.2 V

– 4x gain: 0.6 V

– 8x gain: 300 mV

– 16x gain: 150 mV

– 32x gain: 75 mV

8068Q–AVR–02/10

– 64x gain: 38 mV

XMEGA A3

Problem fix/Workaround

Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V.

3. Sampled BOD in Active mode will cause noise when bandgap is used as reference

Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator.

Problem fix/Workaround

If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode.

4. Bandgap measurement with the ADC is non-functional when V

The ADC cannot be used to do bandgap measurements when V

is below 2.7V

is below 2.7V.

Problem fix/Workaround

If internal voltages must be measured when V

is below 2.7V, measure the internal 1.00V

reference instead of the bandgap.

5. BOD will be enabled after any reset

Problem fix/Workaround

Do not set the BOD level higher than VCC even if the BOD is not used.

6. Writing EEPROM or Flash while reading any of them will not work

The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode.

Problem fix/Workaround

8068Q–AVR–02/10

ADC has increased INL error for some operating conditions

Some ADC configurations or operating condition will result in increased INL error.

In differential mode INL is increased to:

– 6 LSB for sample rates above 1 Msps, and up to 8 LSB for 2 Msps sample rate.

– 6 LSB for reference voltage below 1.1V when VCC is above 3.0V.

– 20 LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.

In single ended mode, the INL is increased up to a factor of 3 for the conditions above.

Problem fix/Workaround

None, avoid using the ADC in the above configurations in order to prevent increased INL error.

XMEGA A3

8. DAC has increased INL or noise for some operating conditions

Some DAC configurations or operating condition will result in increased output error.

– INL error is increased up to 35 LSB when VCC < 2.0V

– Enabling Sample and Hold, will increase noise and reduce resolution below 8 bit

Problem fix/Workaround

None, avoid using the DAC in the above configurations in order to prevent increased INL error.

9. VCC voltage scaler for AC is non-linear

The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.

Problem fix/Workaround

Use external voltage input for the analog comparator if accurate voltage levels are needed.

10. Maximum operating frequency below 1.76V is 8 MHz

To ensure correct operation, the maximum operating frequency below 1.76V VCC is 8 MHz.

Problem fix/Workaround

None, avoid running the device outside this frequency and voltage limitation.

36.2.2 rev. A

11. Inverted I/O enable does not affect Analog Comparator Output

The inverted I/O pin function does not affect the Analog Comparator output function.

Problem fix/Workarund

Not sampled.

8068Q–AVR–02/10

100

Atmel ATxmega256A3, ATxmega192A3, ATxmega128A3, ATxmega64A3 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Typical Applications

1. Ordering Information

2. Pinout/Block Diagram

3. Overview

3.1 Block Diagram

4. Resources

4.1 Recommended reading

5. Disclaimer

6. AVR CPU

6.1 Features

6.2 Overview

6.3 Register File

6.4 ALU - Arithmetic Logic Unit

6.5 Program Flow

7. Memories

7.1 Features

7.2 Overview

7.3 In-System Programmable Flash Program Memory

7.4 Data Memory

7.4.1 I/O Memory

7.4.2 SRAM Data Memory

7.4.3 EEPROM Data Memory

7.5 Production Signature Row

7.6 User Signature Row

7.7 Flash and EEPROM Page Size

8. DMAC - Direct Memory Access Controller

8.1 Features

8.2 Overview

9. Event System

9.1 Features

9.2 Overview

10. System Clock and Clock options

10.1 Features

10.2 Overview

10.3 Clock Options

10.3.1 32 kHz Ultra Low Power Internal Oscillator

10.3.2 32.768 kHz Calibrated Internal Oscillator

10.3.3 32.768 kHz Crystal Oscillator

10.3.4 0.4 - 16 MHz Crystal Oscillator

10.3.5 2 MHz Run-time Calibrated Internal Oscillator

10.3.6 32 MHz Run-time Calibrated Internal Oscillator

10.3.7 External Clock input

10.3.8 PLL with Multiplication factor 1 - 31x

11. Power Management and Sleep Modes

11.1 Features

11.2 Overview

11.3 Sleep Modes

11.3.1 Idle Mode

11.3.2 Power-down Mode

11.3.3 Power-save Mode

11.3.4 Standby Mode

11.3.5 Extended Standby Mode

12. System Control and Reset

12.1 Features

12.2 Resetting the AVR

12.3 Reset Sources

12.3.1 Power-On Reset

12.3.2 External Reset

12.3.3 Watchdog Reset

12.3.4 Brown-Out Reset

12.3.5 PDI reset

12.3.6 Software reset

13. WDT - Watchdog Timer

13.1 Features

13.2 Overview

14. PMIC - Programmable Multi-level Interrupt Controller

14.1 Features

14.2 Overview

14.3 Interrupt vectors

15. I/O Ports

15.1 Features

15.2 Overview

15.3 I/O configuration

15.3.1 Push-pull

15.3.2 Pull-down